LTC3560 2.25MHz, 800mA Synchronous Step-Down Regulator in ThinSOT U FEATURES DESCRIPTIO ■ The LTC ®3560 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. Supply current during operation is only 16µA, dropping to <1µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3560 ideally suited for single Li-Ion/Li-Polymer battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Efficiency: Up to 95% Low Output Ripple (<20mVP-P): Burst Mode® Operation: IQ = 16µA 2.5V to 5.5V Input Voltage Range 2.25MHz Constant Frequency Operation Synchronizable to External Clock No Schottky Diode Required Stable with Ceramic Capacitors Low Dropout Operation: 100% Duty Cycle 0.6V Reference Allows Low Output Voltages Shutdown Mode Draws < 1µA Supply Current ±2% Output Voltage Accuracy Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected Low Profile (1mm) ThinSOTTM Package Switching frequency is internally set at 2.25MHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications the LTC3560 can be externally synchronized from 1MHz to 3MHz. Burst Mode operation is inhibited during synchronization or when the SYNC/MODE pin is pulled high, preventing low frequency ripple from interfering with audio circuitry. U APPLICATIO S ■ ■ ■ ■ Cellular Telephones Wireless and DSL Modems Digital Still Cameras Media Players Portable Instruments , LTC, LT and Burst Mode are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466, 6611131 U ■ The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.6V feedback reference voltage. The LTC3560 is available in a low profile (1mm) ThinSOT package. TYPICAL APPLICATIO 100 1 90 80 0.1 2.2µH CIN 10µF CER VIN SW LTC3560 10pF RUN VOUT 2.5V COUT 10µF CER SYNC/MODE VFB GND 806k 255k 3405A F01a EFFICIENCY (%) VIN 2.7V TO 5.5V 60 50 0.01 40 30 POWER LOSS (W) 70 0.001 20 VIN = 3.6V VIN = 4.2V VIN = 5.5V 10 0 0.1 1 10 100 LOAD CURRENT (mA) 0.0001 1000 3560 F01b Figure 1a. High Efficiency Step-Down Converter Figure 1b. Efficiency vs Load Current 3560f 1 LTC3560 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage .................................. – 0.3V to 6V SYNC/MODE, RUN, VFB Voltages ............... – 0.3V to VIN SW Voltage (DC) ......................... – 0.3V to (VIN + 0.3V) P-Channel Switch Source Current (DC) (Note 6) ... 1.2A N-Channel Switch Sink Current (DC) (Note 6) ....... 1.2A Peak SW Sink and Source Current (Note 6)........... 2.1A Operating Temperature Range (Note 2) .. – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C TOP VIEW RUN 1 6 SYNC/MODE GND 2 5 VFB SW 3 4 VIN S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 125°C, θJA = 250°C/ W ORDER PART NUMBER LTC3560ES6 S6 PART MARKING LTCFY Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 3.6V unless otherwise specified. SYMBOL PARAMETER IVFB Feedback Current CONDITIONS MIN IPK Peak Inductor Current VIN = 3V, VFB = 0.5V, Duty Cycle < 35% VFB Regulated Feedback Voltage (Note 4) ● ∆VFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 4) ● VLOADREG Output Voltage Load Regulation VIN Input Voltage Range IS Input DC Bias Current Pulse Skipping Mode Burst Mode® Operation Shutdown (Note 5) VFB = 0.63V, Mode = High, ILOAD = 0A VFB = 0.63V, Mode = Low, ILOAD = 0A VRUN = 0V, VIN = 5.5V fOSC Oscillator Frequency VFB = 0.6V fSYNC SYNC Frequency Range RPFET RDS(ON) of P-Channel FET ISW = 100mA 0.23 0.35 Ω RNFET RDS(ON) of N-Channel FET ISW = –100mA 0.21 0.35 Ω ILSW SW Leakage VRUN = 0V, VSW = 0V or 5.5V, VIN = 5.5V ±0.01 ±1 µA VRUN RUN Threshold ● IRUN RUN Leakage Current ● SYNC/MODE Leakage Current tSOFTSTART Soft-Start Time MAX UNITS ±30 nA 1.0 1.5 2.0 A 0.588 0.6 0.612 0.04 0.4 0.5 ● 2.5 ● 1.8 ● 1 ● VSYNC/MODE SYNC/MODE Threshold ISYNC/MODE TYP ● 0.3 0.3 ● VFB from 10% to 90% Full Scale Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 0.6 V %/V % 5.5 V 200 16 0.1 300 30 1 µA µA µA 2.25 2.7 MHz 3 MHz 1 1.5 V ±0.01 ±1 µA 1.0 1.5 V ±0.01 ±1 µA 0.9 1.2 ms Note 2: The LTC3560E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 3560f 2 LTC3560 ELECTRICAL CHARACTERISTICS Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3560: TJ = TA + (PD)(250°C/W) Note 4: The LTC3560 is tested in a proprietary test mode that connects VFB to the output of the error amplifier. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: Guaranteed by long-term current density limitations. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. U W TYPICAL PERFOR A CE CHARACTERISTICS (From Figure1a Except for the Resistive Divider Resistor Values) Efficiency vs Input Voltage IOUT = 10mA IOUT = 1mA 85 80 EFFICIENCY (%) EFFICIENCY (%) 90 IOUT = 900mA 75 70 65 55 90 90 80 80 70 70 60 50 40 30 IOUT = 0.1mA 2.5 3 4 4.5 3.5 INPUT VOLTAGE (V) 5 VOUT = 3.3V 0 0.1 1 10 100 OUTPUT CURRENT (mA) 5.5 Efficiency vs Output Current 90 80 80 70 70 60 50 40 30 10 0 0.1 0 0.1 1000 1 10 100 OUTPUT CURRENT (mA) 1000 3560 G03 1 10 100 OUTPUT CURRENT (mA) 3560 G02 0.615 Burst Mode OPERATION PULSE SKIP MODE 40 20 10 VIN = 3.6V 0.610 60 50 1000 Reference Voltage vs Temperature 30 VIN = 2.7V VIN = 3.6V VIN = 4.2V VIN = 2.7V VIN = 3.6V VIN = 4.2V VIN = 5.5V 10 100 VOUT = 1.3V 20 40 Efficiency vs Output Current EFFICIENCY (%) EFFICIENCY (%) 90 50 3560 G24 3560 G01 100 60 20 VIN = 3.6V VIN = 4.2V VIN = 5.5V 10 VOUT = 1.8V VOUT = 1.8V 30 20 60 50 100 EFFICIENCY (%) IOUT = 100mA 100 REFERENCE VOLTAGE (V) 95 Efficiency vs Output Current Efficiency vs Output Current 100 0.605 0.600 0.595 0.590 VIN = 4.2V VIN = 3.6V VOUT = 1.8V 0 1 0.1 10 100 OUTPUT CURRENT (mA) 1000 3560 G04 0.585 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3560 G05 3560f 3 LTC3560 U W TYPICAL PERFOR A CE CHARACTERISTICS (From Figure 1a Except for the Resistive Divider Resistor Values) Oscillator Frequency vs Temperature VIN = 3.6V OSCILLATOR FREQUENCY (MHz) OSCILLATOR FREQUENCY (MHz) 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 Output Voltage vs Load Current 2.4 1.84 2.3 1.83 OUTPUT VOLTAGE (V) 2.50 Oscillator Frequency vs Supply Voltage 2.2 2.1 2.0 VIN = 3.6V 1.82 1.81 Burst Mode OPERATION 1.80 PULSE SKIP MODE 1.79 1.9 2.05 2.00 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 1.78 1.8 125 2 2.5 3 4.5 5 3.5 4 INPUT VOLTAGE (V) 3560 G06 RDS(ON) vs Input Voltage 0.35 0.30 RDS(ON) (Ω) 0.30 0.20 VIN = 2.7V DYNAMIC SUPPLY CURRENT (µA) 300 0.35 SYNCHRONOUS SWITCH VIN = 3.6V 0.25 VIN = 4.2V 0.20 0.15 0.10 0.15 0.05 0.10 1 4 3 5 2 INPUT VOLTAGE (V) 6 0 –50 –25 7 0 50 75 25 TEMPERATURE (°C) 150 100 50 Burst Mode OPERATION 125 2 3 2.5 4.5 5 3.5 4 INPUT VOLTAGE (V) 6 5.5 3560 G12 Switch Leakage vs Input Voltage 1000 RUN = 0V 900 120 800 SWITCH LEAKAGE (nA) DYNAMIC SUPPLY CURRENT (µA) VIN = 3.6V VOUT = 1.2V ILOAD = 0A PULSE SKIPPING MODE 100 50 25 75 0 TEMPERATURE (°C) 100 80 MAIN SWITCH 60 40 20 Burst Mode OPERATION 0 –50 –25 100 140 150 50 PULSE SKIPPING MODE Switch Leakage vs Temperature 300 1200 200 3560 G09 Dynamic Supply Current vs Temperature 200 250 0 3560 G10 250 1000 VOUT = 1.2V ILOAD = 0A SYNCHRONOUS SWITCH MAIN SWITCH 100 125 3560 G11 SWITCH LEAKAGE (pA) 0 400 600 800 LOAD CURRENT (mA) Dynamic Supply Current 0.40 0.25 200 3560 G08 RDS(ON) vs Temperature MAIN SWITCH 0 3560 G07 0.40 RDS(0N) (Ω) 6 5.5 0 –50 –25 SYNCHRONOUS SWITCH 700 600 500 MAIN SWITCH 400 300 SYNCHRONOUS SWITCH 200 100 0 50 25 75 0 TEMPERATURE (°C) 100 125 3560 G13 0 1 3 4 2 INPUT VOLTAGE (V) 5 6 3560 G14 3560f 4 LTC3560 U W TYPICAL PERFOR A CE CHARACTERISTICS (From Figure 1a Except for the Resistive Divider Resistor Values) Burst Mode Operation Pulse Skipping Mode Operation Start-Up from Shutdown RUN 2V/DIV SW 2V/DIV SW 2V/DIV VOUT 20mV/DIV AC COUPLED VOUT 1V/DIV VOUT 20mV/DIV AC COUPLED IL 200mA/DIV IL 200mA/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 25mA 2µs/DIV 3560 G15 IL 500mA/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 25mA Load Step 500ns/DIV 3560 G16 VIN = 3.6V VOUT = 1.8V ILOAD = 800mA Load Step VOUT 200mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV VIN = 3.6V 20µs/DIV VOUT = 1.8V ILOAD = 0A TO 800mA PULSE SKIPPING MODE 3560 G18 VIN = 3.6V 20µs/DIV VOUT = 1.8V ILOAD = 50mA TO 800mA PULSE SKIPPING MODE 3560 G19 VIN = 3.6V 20µs/DIV VOUT = 1.8V ILOAD = 100mA TO 800mA PULSE SKIPPING MODE Load Step Load Step VOUT 200mV/DIV AC COUPLED VOUT 200mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV 3560 G21 VIN = 3.6V 20µs/DIV VOUT = 1.8V ILOAD = 50mA TO 800mA Burst Mode OPERATION 3560 G20 Load Step VOUT 200mV/DIV AC COUPLED VIN = 3.6V 20µs/DIV VOUT = 1.8V ILOAD = 0A TO 800mA Burst Mode OPERATION 3560 G17 Load Step VOUT 200mV/DIV AC COUPLED VOUT 200mV/DIV AC COUPLED 500µs/DIV 3560 G22 20µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 100mA TO 800mA Burst Mode OPERATION 3560 G23 3560f 5 LTC3560 U U U PI FU CTIO S RUN (Pin 1): Run Control Input. Forcing this pin above 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1µA supply current. Do not leave RUN floating. VFB (Pin 5): Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. SYNC/MODE (Pin 6): External Clock Synchronization and Mode Select Input. To synchronize with an external clock, apply a clock with a frequency between 1MHz and 3MHz. To select pulse skipping mode, tie to VIN. Grounding this pin selects Burst Mode operation. Do not leave this pin floating. GND (Pin 2): Ground Pin. SW (Pin 3): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. VIN (Pin 4): Main Supply Pin. Must be closely decoupled to GND, Pin 2, with a 10µF or greater ceramic capacitor. W FU CTIO AL DIAGRA U U SYNC/MODE 6 SLOPE COMP 0.65V OSC OSC 4 VIN FREQ SHIFT – + 5 0.6V – EA 0.4V EN SLEEP – + Q R Q RUN 0.6V REF SHUTDOWN 5Ω + ICOMP BURST S RS LATCH VIN 1 – + SWITCHING LOGIC AND BLANKING CIRCUIT ANTISHOOTTHRU 3 SW + VFB IRCMP 2 GND – 3560 BD 3560f 6 LTC3560 U OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC3560 uses a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. The VFB pin, described in the Pin Functions section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.6V reference, which in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. The main control loop is shut down by grounding RUN, resetting the internal soft-start. Re-enabling the main control loop by pulling RUN high activates the internal soft-start, which slowly ramps the output voltage over approximately 0.9ms until it reaches regulation. Burst Mode Operation The LTC3560 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. To enable Burst Mode operation, simply connect the SYNC/MODE pin to GND. To disable Burst Mode operation and enable PWM pulse skipping mode, connect the SYNC/MODE pin to VIN or drive it with a logic high (VMODE > 1.5V). In this mode, the efficiency is lower at light loads, but becomes comparable to Burst Mode operation when the output load exceeds 100mA. The advantage of pulse skipping mode is lower output ripple and less interference to audio circuitry. When the converter is in Burst Mode operation, the peak current of the inductor is set to approximately 150mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 16µA. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA amplifier’s output rises above the sleep threshold signaling the BURST comparator to trip and turn the top MOSFET on. This process repeats at a rate that is dependent on the load demand. Frequency Synchronization When the LTC3560 is clocked by an external source, Burst Mode operation is disabled; the LTC3560 then operates in PWM pulse-skipping mode. In this mode, when the output load is very low, current comparator ICOMP may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. Increasing the output load slightly allows constant frequency PWM operation to resume. This mode exhibits low output ripple as well as low audio noise and reduced RF interference while providing reasonable low current efficiency. Dropout Operation As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. Another important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3560 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). 3560f 7 LTC3560 U OPERATIO (Refer to Functional Diagram) Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3560 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. U W U U APPLICATIO S I FOR ATIO The basic LTC3560 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. current to prevent core saturation. Thus, a 960mA rated inductor should be enough for most applications (800mA + 160mA). For better efficiency, choose a low DC-resistance inductor. Inductor Selection The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 200mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. For most applications, the value of the inductor will fall in the range of 1µH to 3.3µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in equation 1. A reasonable starting point for setting ripple current is ∆IL = 320mA (40% of 800mA). ⎛ V ⎞ 1 VOUT ⎜ 1 − OUT ⎟ ∆IL = ( f)(L) ⎝ VIN ⎠ Inductor Core Selection (1) The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost Table 1. Representative Surface Mount Inductors MANUFACTURER Toko Sumida TDK Coilcraft Cooper EPCO PART NUMBER A960AW-1R2M-518LC A960AW-2R3M-518LC A997AS-3R3M-DB318L CDRH2D11/HP-1R5 CDRH3D11/HP-1R5 CDRH2D18/HP-2R2 CDRH2D14-3R3 VLF3010AT-1R5M1R2 VLF3010AT-2R2M1R0 D01608C-222 LP01704-222M SD3112-2R2 B82470A1222M MAX DC VALUE CURRENT DCR HEIGHT 1.2µH 1.8A 46mΩ 1.8mm 2.3µH 1.5A 63mΩ 1.8mm 3.3µH 1.2A 70mΩ 1.8mm 1.5µH 1.35A 64mΩ 1.2mm 1.5µH 2A 80mΩ 1.2mm 2.2µH 1.6A 48mΩ 2.0mm 3.3µH 1.2A 100mΩ 1.55mm 1.5µH 1.2A 68mΩ 1.0mm 2.2µH 1.0A 100mΩ 1.0mm 2.2µH 2.3A 70mΩ 3.0mm 2.2µH 2.4A 120mΩ 1.0mm 2.2µH 1.1A 140mΩ 1.2mm 2.2µH 1.6A 90mΩ 1.2mm 3560f 8 LTC3560 U W U U APPLICATIO S I FOR ATIO more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3560 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3560 applications. supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. CIN and COUT Selection Using Ceramic Input and Output Capacitors In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3560’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. 1/ 2 VOUT (VIN − VOUT )] [ CIN required IRMS ≅ IOMAX VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ∆VOUT is determined by: ⎛ 1 ⎞ ∆VOUT ≅ ∆IL ⎜ ESR + ⎟ ⎝ 8fC OUT ⎠ where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ∆IL increases with input voltage. If tantalum capacitors are used, it is critical that the capacitors are surge tested for use in switching power However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The output voltage is set by a resistive divider according to the following formula: ⎛ R2 ⎞ VOUT = 0.6 V ⎜ 1+ ⎟ ⎝ R1⎠ (2) The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 2. 3560f 9 LTC3560 U W U U APPLICATIO S I FOR ATIO 0.6V ≤ VOUT ≤ 5.5V R2 VFB LTC3560 R1 GND 3560 F02 Figure 2. Setting the LTC3560 Output Voltage Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3560 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 3. 1 VOUT = 2.5V Burst Mode OPERATION 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. 0.1 POWER LOST (W) 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 0.01 Thermal Considerations 0.001 0.0001 0.1 VIN = 3.6V VIN = 4.2V VIN = 5.5V 1 10 100 LOAD CURRENT (mA) 1000 3560 F03 Figure 3. Power Lost vs Load Current In most applications the LTC3560 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3560 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, 3560f 10 LTC3560 U W U U APPLICATIO S I FOR ATIO both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3560 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(θJA) where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: T J = TA + TR value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. where TA is the ambient temperature. PC Board Layout Checklist As an example, consider the LTC3560 in dropout at an input voltage of 2.7V, a load current of 800mA and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is approximately 0.31Ω. Therefore, power dissipated by the part is: When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3560. These items are also illustrated graphically in Figures 4 and 5. Check the following in your layout: PD = ILOAD2 • RDS(ON) = 198mW For the SOT-23 package, the θJA is 250°C/ W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.198)(250) = 120°C which is below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady-state 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the (–) plates of CIN and COUT as close as possible. 5. Keep the switching node, SW, away from the sensitive VFB node. Design Example As a design example, assume the LTC3560 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.8A but most of the time it will be in 3560f 11 LTC3560 U W U U APPLICATIO S I FOR ATIO 1 RUN SYNC/MODE 6 LTC3560 2 – GND VFB 5 COUT VOUT R2 3 + L1 SW VIN R1 4 CFWD CIN VIN 3560 F04 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 4. LTC3560 Layout Diagram VIA TO GND R1 VOUT VIN VIA TO VIN VIA TO VOUT R2 PIN 1 L1 CFWD LTC3560 SW COUT CIN GND 3560 F05 Figure 5. LTC3560 Suggested Layout standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using equation (1), L= ⎛ V ⎞ 1 VOUT ⎜ 1 − OUT ⎟ ( f)(∆IL ) ⎝ VIN ⎠ (3) Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 320mA and f = 2.25MHz in equation (3) gives: L= 2.5V ⎛ 2.5V ⎞ 1− ≅ 1.4µH 2.25MHz(320mA) ⎜⎝ 4.2V ⎟⎠ CIN will require an RMS current rating of at least 0.4A ≅ ILOAD(MAX)/2 at temperature and COUT will require an ESR of less than 0.1Ω. In most cases, a ceramic capacitor will satisfy this requirement. For the feedback resistors, choose R1 = 309k. R2 can then be calculated from equation (2) to be: ⎛V ⎞ R2 = ⎜ OUT − 1⎟ R1= 978.5k ; use 976k ⎝ 0.6 ⎠ Figure 6 shows the complete circuit along with its efficiency curve. A 1.5µH inductor works well for this application. For best efficiency choose a 960mA or greater inductor with less than 0.2Ω series resistance. 3560f 12 LTC3560 U W U U APPLICATIO S I FOR ATIO 100 90 VOUT = 2.5V 80 Burst Mode OPERATION VIN 2.7V TO 4.2V 4 CIN* 10µF CER VIN SW 3 10pF LTC3560 1 6 1.5µH** COUT* 10µF CER RUN SYNC/MODE VFB 5 GND 2 VOUT 2.5V 976k EFFICIENCY (%) 70 PULSE SKIPPING 60 50 40 30 20 VIN = 3.6V VIN = 4.2V 10 309k 3560 F06a * TDK C2012X5R0J106M **TDK VLF3010AT-1R5N1R2 0 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 3560 F06b Figure 6a Figure 6b VOUT 200mV/DIV AC COUPLED VOUT 200mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV VIN = 3.6V 20µs/DIV VOUT = 2.5V ILOAD = 100mA TO 800mA Burst Mode OPERATION Figure 6c 3560 F06c 20µs/DIV VIN = 3.6V VOUT = 2.5V ILOAD = 100mA TO 800mA PULSE SKIPPING MODE 3560 F06d Figure 6d 3560f 13 LTC3560 U W U U APPLICATIO S I FOR ATIO 100 90 VIN 2.7V TO 4.2V 4 CIN* 10µF CER 3MHz CLK VIN SW 1µH** 3 10pF LTC3560 1 6 COUT* 10µF CER RUN SYNC/MODE VFB 5 GND 2 VOUT 1.2V 301k EFFICIENCY (%) 80 70 60 50 40 30 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 301k 0 3560 F07a 1 *TDK C2012X5R0J106M **MURATA LQH32CN1R0M33 10 100 LOAD CURRENT (mA) 1000 3560 F07b Figure 7a Figure 7b VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED IL 500mA/DIV IL 500mA/DIV ILOAD 500mA/DIV ILOAD 500mA/DIV VIN = 3.6V 20µs/DIV VOUT = 1.2V ILOAD = 300A TO 800mA Figure 7c 3560 F07c 20µs/DIV VIN = 3.6V VOUT = 1.2V ILOAD = 0mA TO 500mA 3560 F07d Figure 7d 3560f 14 LTC3560 U PACKAGE DESCRIPTIO S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.90 BSC S6 TSOT-23 0302 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 3560f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3560 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20µA, ISD = <1µA, ThinSOT Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, ISD = <1µA, ThinSOT Package LTC3407/LTC3407-2 Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD = <1µA, MS10E, DFN Packages LTC3409 600mA (IOUT), 1.7MHz/2.6MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65µA, ISD = <1µA, DFN Package LTC3410/LTC3410B 300mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26µA, ISD = <1µA, SC70 Package LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD = <1µA, MS10, DFN Packages LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD = <1µA, TSSOP-16E Package LTC3441/LTC3442 LTC3443 1.2A (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converters 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50µA, ISD = <1µA, DFN Package LTC3531/LTC3531-3 LTC3531-3.3 200mA (IOUT), 1.5MHz, Synchronous Buck-Boost DC/DC Converters 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16µA, ISD = <1µA, ThinSOT, DFN Packages LTC3532 500mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35µA, ISD = <1µA, MS10, DFN Packages LTC3548/LTC3548-1 LTC3548-2 Dual 400mA/800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD = <1µA, MS10E, DFN Packages LTC3561 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240µA, ISD = <1µA, DFN Package 3560f 16 Linear Technology Corporation LT 1106 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006