CY7C1338G PRELIMINARY 4-Mbit (128K x 32) Flow-Through Sync SRAM Functional Description[1] Features • • • • • • • • • • • 128K X 32 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) Provide high-performance 2-1-1-1 access rate User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable Lead-Free 100-pin TQFP and 119-ball BGA packages “ZZ” Sleep Mode option The CY7C1338G is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1338G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram ADDRESS REGISTER A0, A1, A A[1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQD BYTE DQD BYTE BWD WRITE REGISTER WRITE REGISTER DQC BYTE DQC BYTE BWC WRITE REGISTER WRITE REGISTER DQB BYTE DQB BYTE BWB MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs WRITE REGISTER WRITE REGISTER DQA BYTE WRITE REGISTER DQA BYTE BWA WRITE REGISTER BWE INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE ZZ SLEEP CONTROL Note: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05521 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 21, 2004 CY7C1338G PRELIMINARY Selection Guide 133 MHz 6.5 225 40 Maximum Access Time Maximum Operating Current Maximum Standby Current 117 MHz 7.5 220 40 100 MHz 8.0 205 40 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Pin Configurations Document #: 38-05521 Rev. *A A A 35 36 37 38 39 40 41 42 45 46 47 48 49 50 A1 A0 NC NC VSS VDD NC NC A A A A A A A 44 34 A 43 81 82 83 84 BWE OE ADSC ADSP ADV 85 86 GW 89 87 CLK 91 88 VDD VSS 93 90 BWA CE3 94 92 BWC BWB 95 CE2 BWD 96 98 97 A CE1 99 A 31 VSSQ VDDQ DQD DQD NC A VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD CY7C1338G 33 BYTE D DQC DQC VSSQ VDDQ DQC DQC NC VDD NC A BYTE C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 VDDQ VSSQ DQC DQC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A NC DQC DQC 100 100-Pin TQFP NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC BYTE B VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA BYTE A VSSQ VDDQ DQA DQA NC Page 2 of 17 CY7C1338G PRELIMINARY Pin Configurations (continued) 119-Ball BGA 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B C NC NC CE2 A A A ADSC VDD A A NC A NC NC D DQC NC VSS NC VSS NC DQB E F DQC VDDQ DQC DQC VSS VSS CE1 OE VSS VSS DQB DQB DQB VDDQ G H J DQC DQC VDDQ DQC DQC VDD BWC VSS NC ADV GW VDD BWB VSS NC DQB DQB VDD DQB DQB VDDQ K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD NC BWA DQA DQA M N VDDQ DQD DQD DQD VSS VSS BWE A1 VSS VSS DQA DQA VDDQ DQA P DQD NC VSS A0 VSS NC DQA R T NC NC A MODE VDD NC A A A A NC NC NC U VDDQ NC NC NC NC NC VDDQ ZZ Pin Definitions Name I/O Description A0, A1, A InputAddress Inputs used to select one of the 128K address locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. BWA,BWB BWC,BWD GW InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. BWE InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be Synchronous asserted LOW to conduct a byte write. CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. CE2 CE3 OE ADV InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it automatically Synchronous increments the address in a burst cycle. Document #: 38-05521 Rev. *A Page 3 of 17 PRELIMINARY CY7C1338G Pin Definitions (continued) Name ADSP ADSC I/O Description InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted Synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a tri-state condition. VDD VSS Power Supply Power supply inputs to the core of the device. Ground Ground for the core of the device. VDDQ I/O Power Power supply for the I/O circuitry. Supply VSSQ I/O Ground Ground for the I/O circuitry. MODE InputStatic NC Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0) is 6.5 ns (133-MHz device). The CY7C1338G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Document #: 38-05521 Rev. *A Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:D])are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BWA controls DQA and BWB controls DQB. BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Page 4 of 17 CY7C1338G PRELIMINARY Single Write Accesses Initiated by ADSC Sleep Mode This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) indicate a write access. ADSC is ignored if ADSP is active LOW. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. During byte writes, BWA controls DQA, BWB controls DQB, BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1338G provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. Max. Unit IDDZZ Snooze mode standby current ZZ > VDD – 0.2V 40 mA tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to snooze current This parameter is sampled tRZZI ZZ Inactive to exit snooze current This parameter is sampled Document #: 38-05521 Rev. *A 2tCYC ns 2tCYC 0 ns ns Page 5 of 17 CY7C1338G PRELIMINARY Truth Table [2, 3, 4, 5, 6] Cycle Description Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK Deselected Cycle, Power-down None H Deselected Cycle, Power-down None L Deselected Cycle, Power-down None L Deselected Cycle, Power-down None L Deselected Cycle, Power-down None X Snooze Mode, Power-down X DQ X L X L X X X L-H tri-state L X L L X X X X L-H tri-state X H L L X X X X L-H tri-state L X L H L X X X L-H tri-state X X L H L X X X L-H tri-state None X X X H X X X X X Read Cycle, Begin Burst External L H L L L X X X L L-H Q X tri-state Read Cycle, Begin Burst External L H L L L X X X H L-H tri-state Write Cycle, Begin Burst External L H L L H L X L X L-H D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H tri-state Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H tri-state Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H tri-state Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H tri-state Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H tri-state Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05521 Rev. *A Page 6 of 17 CY7C1338G PRELIMINARY Partial Truth Table for Read/Write[2, 7] Function GW BWE Read H H X X X X Read H L H H H H Write Byte A H L H H H L Write Byte B H L H H L H BWD BWC BWB BWA Write Bytes B, A H L H H L L Write Byte C H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, B H L L L H H Write Bytes D, B, A H L L L H L Write Bytes D, C, A H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Note: 7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05521 Rev. *A Page 7 of 17 CY7C1338G PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Range Ambient Temperature] DC Voltage Applied to Outputs in tri-state ............................................ –0.5V to VDDQ + 0.5V Commercial 0°C to +70°C Industrial –40°C to +85°C VDD VDDQ 3.3V −5%/+10% 2.5V –5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range [8, 9] Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage Output HIGH Voltage VOH VOL VIH VIL IX IOZ IOS IDD ISB1 ISB2 ISB3 ISB4 Test Conditions VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA Input HIGH Voltage VDDQ = 3.3V VDDQ = 2.5V Input LOW Voltage[8] VDDQ = 3.3V VDDQ = 2.5V Input Load Current (except ZZ and GND ≤ VI ≤ VDDQ MODE) Input Current of MODE Input = VSS Input = VDD Input Current of ZZ Input = VSS Input = VDD Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled Output Short Circuit Current VDD = Max., VOUT = GND VDD Operating Supply Current VDD = Max., IOUT = 0 mA, 7.5-ns cycle, 133 MHz f = fMAX= 1/tCYC 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz Automatic CE Power-Down Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz Current—TTL Inputs VIN ≥ VIH or VIN ≤ VIL, f = fMAX, 8.0-ns cycle, 117 MHz inputs switching 10-ns cycle, 100 MHz Automatic CE Power-Down Max. VDD, Device Deselected, All speeds Current—CMOS Inputs VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static Automatic CE Power-Down Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz Current—CMOS Inputs VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 8.0-ns cycle, 117 MHz f = fMAX, inputs switching 10-ns cycle, 100 MHz Automatic CE Power-Down Max. VDD, Device Deselected, All speeds Current—TTL Inputs VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static CY7C1338G Min. Max. Unit 3.135 3.6 V 2.375 VDD V 2.4 V 2.0 V 0.4 V 0.4 V 2.0 VDD + 0.3V V 1.7 VDD + 0.3V V –0.3 0.8 V –0.3 0.7 V −5 5 µA 30 5 –300 225 220 205 90 85 80 40 µA µA µA µA µA µA mA mA mA mA mA mA mA 75 70 65 45 mA mA mA mA –30 5 –5 –5 Shaded areas contain advance information. Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05521 Rev. *A Page 8 of 17 CY7C1338G PRELIMINARY Thermal Resistance[10] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions TQFP Package BGA Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TBD TBD °C/W TBD TBD °C/W Capacitance[10] Parameter Description Test Conditions TQFP Package TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V 5 5 pF Clock Input Capacitance 5 5 pF Input/Output Capacitance 5 7 pF CIN Input Capacitance CCLK CI/O BGA Package Unit AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω VT = 1.5V 2.5V I/O Test Load (a) INCLUDING JIG AND SCOPE (b) (c) 10% R =1538Ω (a) INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF VT = 1.25V ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω ≤ 1ns ≤ 1ns R = 1667Ω 2.5V OUTPUT 90% 10% 90% 10% ≤ 1ns ≤ 1ns (b) (c) Switching Characteristics Over the Operating Range [11, 12, 13, 14, 15, 16] 133 MHz Parameter tPOWER Description VDD(Typical) to the first Access[11] Min. Max. 117 MHz Min. Max. 100 MHz Min. Max. Unit 1 1 1 ms Clock tCYC Clock Cycle Time 7.5 8.5 10 ns tCH Clock HIGH 2.5 3.0 4.0 ns tCL Clock LOW 2.5 3.0 4.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 6.5 2.0 7.5 2.0 8.0 2.0 ns ns Shaded areas contain advance information. Notes: 10. Tested initially and after any design or process change that may affect these parameters. 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05521 Rev. *A Page 9 of 17 CY7C1338G PRELIMINARY Switching Characteristics Over the Operating Range (continued)[11, 12, 13, 14, 15, 16] 133 MHz Parameter Description [12, 13, 14] tCLZ Clock to Low-Z tCHZ Clock to High-Z[12, 13, 14] tOEV OE LOW to Output Valid tOELZ OE LOW to Output Low-Z[12, 13, 14] tOEHZ OE HIGH to Output Min. Max. 0 117 MHz Min. 0 3.5 100 MHz Min. 3.5 0 3.5 Max. Unit 3.5 ns 3.5 ns 0 3.5 3.5 0 High-Z[12, 13, 14] Max. ns 0 3.5 ns 3.5 ns Setup Times tAS Address Set-up Before CLK Rise 1.5 2.0 2.0 ns tADS ADSP, ADSC Set-up Before CLK Rise 1.5 2.0 2.0 ns tADVS ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise 1.5 2.0 2.0 ns tWES 1.5 2.0 2.0 ns tDS Data Input Set-up Before CLK Rise 1.5 1.5 1.5 ns tCES Chip Enable Set-up 1.5 2.0 2.0 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise GW,BWE, BWX Hold After CLK Rise 0.5 0.5 0.5 ns tWEH 0.5 0.5 0.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 ns Hold Times Document #: 38-05521 Rev. *A Page 10 of 17 CY7C1338G PRELIMINARY Timing Diagrams Read Cycle Timing[17] tCYC CLK t tADS t CL CH tADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 t WES t WEH GW, BWE,BW [A:D] tCES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OELZ tCDV t CHZ tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05521 Rev. *A Page 11 of 17 CY7C1338G PRELIMINARY Timing Diagrams (continued) Write Cycle Timing[17, 18] t CYC CLK t tADS t CH CL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BW[A:D] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note: 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document #: 38-05521 Rev. *A Page 12 of 17 CY7C1338G PRELIMINARY Timing Diagrams (continued) Read/Write Timing[17, 19, 20] tCYC CLK t CH tADS tADH tAS tAH t CL ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) t t WES WEH BWE, BW[A:D] tCES tCEH CE ADV OE tDS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH tOELZ D(A3) tCDV Q(A2) Back-to-Back READs Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH. Document #: 38-05521 Rev. *A Page 13 of 17 CY7C1338G PRELIMINARY Timing Diagrams (continued) ZZ Mode Timing [21, 22] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 117 100 Package Name Package Type Operating Range CY7C1338G-133AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial CY7C1338G-133BGC BG119 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-133BGXC BG119 Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm) Ordering Code CY7C1338G-133AXI A101 CY7C1338G-133BGI BG119 Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-133BGXI BG119 Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-117AXC A101 CY7C1338G-117BGC BG119 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-117BGXC BG119 Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) CY7C1338G-117AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) CY7C1338G-117BGI BG119 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-117BGXI BG119 Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-100AXC A101 CY7C1338G-100BGC BG119 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-100BGXC BG119 Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) CY7C1338G-100AXI A101 CY7C1338G-100BGI BG119 Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) CY7C1338G-100BGXI BG119 Lead-Free 119-Ball PBGA (14 x 22 x 2.4mm) Industrial Commercial Industrial Commercial Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BGX package will be available in 2005. Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05521 Rev. *A Page 14 of 17 CY7C1338G PRELIMINARY Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 1.60 MAX. 0° MIN. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 0.10 R 0.08 MIN. 0.20 MAX. SEATING PLANE GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05521 Rev. *A A 51-85050-*A Page 15 of 17 PRELIMINARY CY7C1338G Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05521 Rev. *A Page 16 of 17 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1338G PRELIMINARY Document History Page Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM Document Number: 38-05521 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 224369 See ECN RKF New data sheet *A 278513 See ECN VBL Deleted 66 MHz Changed TQFP to PB-Free TQFP in Ordering Info section Added PB-Free BG package Document #: 38-05521 Rev. *A Page 17 of 17