DATA SHEET MOS FIELD EFFECT POWER TRANSISTORS µPA1703 SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE DESCRIPTION PACKAGE DIMENSIONS This product is N-Channel MOS Field Effect Transis- (in millimeter) tor designed for power management applications of notebook computers. 8 5 FEATURES 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain • Super Low On-Resistance RDS(on)1 = 10.5 mΩ MAX. (VGS = 10 V, ID = 5.0 A) RDS(on)2 = 17 mΩ MAX. (VGS = 4 V, ID = 5.0 A) Ciss = 2180 pF TYP. 1 0.05 MIN. (Power SOP8) 4.4 5.37 MAX. 0.8 +0.10 –0.05 • Small and Surface Mount Package 6.0 ±0.3 4 0.15 1.8 MAX. • Built-in G-S Protection Diode 1.44 • Low Ciss 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, all terminals are connected) Drain to Source Voltage VDSS 30 V Gate to Source Voltage VGSS ±20 V Drain Current (DC) ID(DC) ±10 A ID(pulse) ±40 A PT 2.0 W Channel Temperature Tch 150 °C Storage Temperature Tstg −55 to °C Drain Current (pulse) Notes1 Total Power Dissipation (TA = 25 °C) Notes2 +150 Notes 1. 2. Drain Body Diode Gate Gate Protection Diode Source PW ≤ 10 µs, Duty Cycle ≤ 1 % Mounted on ceramic substrate of 1200 mm2 × 0.7 mm The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device acutally used, an addtional protection circuit is externally required if voltage exceeding the rated voltage may be applied to this device. Document No. D11494EJ1V0DS00 (1st edition) Date Published December 1996 N Printed in Japan © 1996 µPA1703 ELECTRICAL CHARACTERISTICS (TA = 25 °C, all terminals are connected) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Drain to Source On-state Resistance RDS(on)1 VGS = 10 V, ID = 5.0 A 8.5 10.5 mΩ RDS(on)2 VGS = 4 V, ID = 5.0 A 12 17 mΩ Gate to Source Cutoff Voltage VGS(off) VDS = 10 V, ID = 1 mA 1.0 1.6 2.0 V Forward Transfer Admittance | yfs | VDS = 10 V, ID = 5.0 A 8.0 18 Drain Leakage Current IDSS VDS = 30 V, VGS = 0 10 µA Gate to Source Leakage Current IGSS VGS = ±20 V, VDS = 0 ±10 µA Input Capacitance Ciss VDS = 10 V 2180 pF Output Capacitance Coss VGS = 0 890 pF Reverse Transfer Capacitance Crss f = 1 MHz 370 pF Turn-On Delay Time td(on) ID = 5.0 A 25 ns Rise Time tr VGS(on) = 10 V 210 ns Turn-Off Delay Time td(off) VDD = 15 V 120 ns Fall Time tf RG = 10 Ω 75 ns Total Gate Charge QG ID = 10 A 40 nC Gate to Source Charge QGS VDD = 24 V 5.6 nC Gate to Drain Charge QGD VGS = 10 V 9.6 nC Body Diode Forward Voltage VF(S-D) IF = 10 A, VGS = 0 0.73 V Reverse Recovery Time trr IF = 10 A, VGS = 0 46 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 45 nC Test Circuit 1 Switching Time Test Circuit 2 Gate Charge D.U.T. D.U.T. VGS RL VGS RG RG = 10 Ω PG. Wave Form 0 PG. VDD I D Wave Form 90 % 90 % t = 1 µs Duty Cycle ≤ 1 % 10 % 0 10 % tr td(on) ton IG = 2 mA RL 50 Ω VDD 90 % ID t 2 VGS(on) 10 % ID VGS 0 S td(off) tf toff µPA1703 TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 0 20 40 60 80 2.0 1.6 1.2 0.8 0.4 0 100 120 140 160 Mounted on ceramic substrate of 1 200 mm2 × 0.7 mm 2.4 TA - Ambient Temperature - °C 20 40 60 80 100 120 140 160 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 ) on R t VG (a Note: Mounted on ceramic substrate of 1 200 mm2 × 0.7 mm ID(pulse) 1 m s ID(DC) 10 10 m s 10 0 m s Po we 1 DC rD iss ipa tio n 0.1 0.1 Lim ite TA = 25 °C Single Pulse d 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1 000 rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A ( DS d ite V) Lim 10 = S 100 10 1 0.1 Mounted on ceramic substrate of 1 200 mm2 × 0.7 mm Single Pulse Channel to Ambient 0.01 0.001 10 µ 100 µ 1m 10 m 100 m 1 10 100 1 000 PW - Pulse Width - s 3 µPA1703 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 100 Pulsed Pulsed ID - Drain Current - A ID - Drain Current - A 50 10 Tch = –25 °C 25 °C 75 °C 125 °C 1 0.1 4 2 6 30 0 8 1 0.1 10 1 100 RDS(on) - Drain to Source On-State Resistance - mΩ ID - Drain Current - A 4 RDS(on) - Drain to Source On-State Resistance - mΩ VDS = 10 V Pulsed Pulsed 30 20 VGS = 4 V 10 VGS = 10 V 0 1 10 ID - Drain Current - A 0.8 0.6 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 30 Pulsed 20 ID = 5.0 A 10 0 100 5 10 15 VGS - Gate to Source Voltage - V DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT GATE TO SOURCE CUTOFF VOLTAGE vs. CHANNEL TEMPERATURE VGS(off) - Gate to Source Cutoff Voltage - V | yfs | - Forward Transfer Admittance - S 10 0.4 0.2 VDS - Drain to Source Voltage - V FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT Tch = –25 °C 25 °C 75 °C 125 °C 4V 20 VGS - Gate to Source Voltage - V 100 VGS = 10 V 10 VDS = 10 V 0 40 VDS = 10 V ID = 1 mA 2.0 1.5 1.0 0.5 0 –50 0 50 100 150 Tch - Channel Temperature - °C SOURCE TO DRAIN DIODE FORWARD VOLTAGE DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE Pulsed 20 ISD - Diode Forward Current - A VGS = 4 V 15 10 10 V 5 100 VGS = 4 V VGS = 0 10 1 0.1 ID = 5.0 A 0 –50 0 50 100 0 150 Tch - Channel Temperature - °C CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE SWITCHING CHARACTERISTICS td(on), tr, td(off), tf - Switching Time - ns Ciss, Coss, Crss - Capacitance - pF 10 000 VGS = 0 f = 1 MHz Ciss 1 000 Coss Crss 100 10 0.1 1 10 1 000 tr td(off) 100 tf td(on) 10 1 0.1 100 VDS - Drain to Source Voltage - V 10 10 IF - Diode Current - A 100 40 VDS - Drain to Source Voltage - V trr - Reverse Recovery Time - ns di/dt = 100 A/µ s VGS = 0 1 1 DYNAMIC INPUT/OUTPUT CHARACTERISTICS 100 1 0.1 VDD = 15 V VGS(on) = 10 V RG = 10 Ω 10 100 ID - Drain Current - A REVERSE RECOVERY TIME vs. DRAIN CURRENT 1 000 1.5 1.0 0.5 VSD - Source to Drain Voltage - V ID = 10 A 14 30 12 10 20 VGS VDD = 24 V 15 V 6V 8 6 4 10 2 VDS 0 10 20 30 40 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-State Resistance - mΩ µPA1703 0 QG - Gate Charge - nC 5 µPA1703 REFERENCE Document Name 6 Document No. NEC semiconductor device reliability/quality control system C11745E Quality grade on NEC semiconductor devices C11531E Semiconductor device mounting technology manual C10535E Semiconductor device package manual C10943X Guide to quality assurance for semiconductor devices MEI-1202 Application circuits using Power MOS FET TEA-1035 Safe operating area of Power MOS FET TEA-1037 µPA1703 [MEMO] 7