NEC UPA1709G

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA1709
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
This product is N-Channel MOS Field Effect Transistor designed for DC/DC converters and power management
switch.
FEATURES
PACKAGE DRAWING (Unit : mm)
• Low on-resistance
8
RDS(on)1 = 9.3 mΩ (TYP.) (VGS = 10 V, ID = 4.5 A)
5
RDS(on)2 = 13.8 mΩ (TYP.) (VGS = 4.5 V, ID = 4.5 A)
1,2,3 ; Source
; Gate
4
5,6,7,8 ; Drain
• Low Ciss : Ciss = 1850 pF (TYP.)
• Built-in G-S protection diode
• Small and surface mount package (Power SOP8)
PACKAGE
µ PA1709G
Power SOP8
4.4
1.27
0.40
+0.10
–0.05
VDSS
40
V
Gate to Source Voltage (VDS = 0 V)
VGSS
±25
V
Drain Current (DC)
ID(DC)
±9.0
A
ID(pulse)
±36
A
PT
2.0
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to + 150
°C
Total Power Dissipation (TA = 25°C)
Note2
0.10
0.12 M
Drain to Source Voltage (VGS = 0 V)
Drain Current (pulse)
0.5 ±0.2
0.78 Max.
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Note1
0.8
+0.10
–0.05
0.15
PART NUMBER
6.0 ±0.3
4
5.37 Max.
0.05 Min.
1.8 Max.
ORDERING INFORMATION
1.44
1
EQUIVARENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Notes 1. PW ≤ 10 µ s, Duty Cycle ≤ 1 %
2
2. Mounted on ceramic substrate of 1200 mm x 0.7 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Document No.
G13436EJ1V0DS00 (1st edition)
Date Published November 1998 NS CP(K)
Printed in Japan
©
1998
µ PA1709
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
Drain to Source On-state Resistance
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
RDS(on)1
VGS = 10 V, ID = 4.5 A
9.3
12.5
mΩ
RDS(on)2
VGS = 4.5 V, ID = 4.5 A
13.8
20.0
mΩ
VGS(off)
VDS = 10 V, ID = 1 mA
1.5
2.0
2.5
V
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 4.5 A
8.0
14
Drain Leakage Current
IDSS
VDS = 40 V, VGS = 0 V
10
µA
Gate to Source Leakage Current
IGSS
VGS = ±25 V, VDS = 0 V
±10
µA
Input Capacitance
Ciss
VDS = 10 V
1850
pF
Output Capacitance
Coss
VGS = 0 V
790
pF
330
pF
ID = 4.5 A
27
ns
VGS(on) = 10 V
95
ns
110
ns
70
ns
ID = 9.0 A
43.0
nC
VDD = 32 V
6.0
nC
Gate to Source Cut-off Voltage
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
Rise Time
f = 1 MHz
tr
Turn-off Delay Time
VDD = 20 V
td(off)
Fall Time
RG = 10 Ω
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
VGS = 10 V
14.0
nC
VF(S-D)
IF = 9.0 A, VGS = 0 V
0.78
V
trr
IF = 9.0 A, VGS = 0 V
47
ns
Qrr
di/dt = 100 A/ µ s
44
nC
QGD
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
TEST CIRCUIT 2 GATE CHARGE
TEST CIRCUIT 1 SWITCHING TIME
D.U.T.
IG = 2 mA
D.U.T.
VGS
RL
VGS
PG.
RG
RG = 10
Wave Form
0
VGS (on)
10 %
90 %
PG.
VDD
90 %
ID
90 %
ID
VGS
0
I
D
Wave Form
t= 1 s
Duty Cycle
2
0
10 %
10 %
tr
td (on)
t
ton
1%
S
td (off)
tf
toff
50
RL
VDD
µ PA1709
TYPICAL CHARACTERISTICS (TA = 25 °C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
100
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
2.8
80
60
40
20
0
20
40
60
80
2.0
1.6
1.2
0.8
0.4
0
100 120 140 160
Mounted on ceramic
substrate of
1200 mm2 0.7 mm
2.4
TA - Ambient Temperature - ˚C
20
40
60
80
100 120 140 160
TA - Ambient Temperature - ˚C
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD BIAS SAFE OPERATING AREA
100
Mounted on ceramic
=
1
m
ID - Drain Current - A
10
m
s
0m
n
io
at
ip
C
D
iss
rD
s
we
1
Pulsed
50
s
ID(DC)
10
R
(V DS(o
G n)
S
= 1Lim
0 V ite
) d
10
PW
ID(pulse)
Po
40
VGS = 10 V
4.5 V
30
20
10
d
TA = 25 ˚C
0.1 Single Pulse
0.1
0
ite
m
Li
ID - Drain Current - A
substrate of 1200 mm2 0.7 mm
1
10
100
VDS - Drain to Source Voltage - V
0
0.4
0.8
VDS - Drain to Source Voltage - V
FORWARD TRANSFER CHARACTERISTICS
ID - Drain Current - A
100
Pulsed
10
TA = 150 ˚C
125 ˚C
75 ˚C
25 ˚C
-25 ˚C
-50 ˚C
1
0.1
0
2
4
VDS = 10 V
8
6
VGS - Gate to Source Voltage - V
3
µ PA1709
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - ˚C/W
1 000
Rth(CH-A) = 62.5 ˚C/W
100
10
1
0.1
0.01
Mounted on ceramic
substrate of 1200 mm2
Single Pulse
0.001
100
10
1m
10 m
100 m
1
10
0.7 mm
100
1 000
PW - Pulse Width - s
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
10
Pulsed
TA = -50 ˚C
-25 ˚C
25 ˚C
75 ˚C
125 ˚C
150 ˚C
1
VDS = 0 V
0.1
0.1
1
100
10
ID- Drain Current - A
RDS(on) - Drain to Source On-state Resistance - m
|yfs| - Forward Transfer Admittance - S
100
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
Pulsed
60
40
20
ID = 4.5 A
0
VGS - Gate to Source Voltage - V
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
4
Pulsed
30
20
VGS = 4.5 V
10
10 V
0
1
10
ID - Drain Current - A
100
VGS(off) - Gate to Source Cut-off Voltage - V
RDS(on) - Drain to Source On-state Resistance - m
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
40
15
10
5
VDS = 10 V
ID = 1 mA
2.6
1.8
1.0
-40
0
40
80
Tch - Channel Temperature - ˚C
120
µ PA1709
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
Pulsed
40
100
ISD - Diode Forward Current - A
30
VGS = 4.5 V
20
10 V
10
ID = 4.5 A
0
-50
50
0
100
VGS = 10 V
10
0V
1
0.1
150
0
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
Coss
Crss
100
1
10
100
td(on), tr, td(off), tf - Switching Time - ns
1 000
10
0.1
tr
td(off)
100
tf
td(on)
10
VDS = 20 V
VGS = 10 V
RG = 10
1
0.1
1
REVERSE RECOVERY TIME vs.
DIODE CURRENT
VDS - Drain to Source Voltage - V
di/dt = 100 A/ s
VGS = 0 V
100
10
1
0.1
1
10
ID - Diode Current - A
10
100
ID - Drain Current - A
VDS - Drain to Source Voltage - V
1 000
1.5
1.0
1 000
VGS = 0 V
f = 1 MHz
Ciss
trr - Reverse Recovery Time - ns
Ciss, Coss, Crss - Capacitance - pF
10 000
0.5
VSD - Source to Drain Voltage - V
Tch - Channel Temperature - ˚C
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
80
ID = 9.0 A
VDD = 32 V
14
20 V
12
60
8V
VGS
10
40
8
6
4
20
2
VDS
0
20
40
60
VGS - Gate to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - m
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
80
QG - Gate Charge - nC
5
µ PA1709
[MEMO]
6
µ PA1709
[MEMO]
7
µ PA1709
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document.
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Anti-radioactive design is not implemented in this product.
M4 96. 5