P4C187/P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Three-State Output High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35/45 ns (Commercial) – 12/15/20/25/35 /45 ns (Industrial) – 15/20/25/35/45/55/70/85 ns (Military) TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) Low Power Operation Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C187L) – 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 22-Pin 290x490 mil LCC – 28-Pin 350x550 mil LCC Separate Data I/O DESCRIPTION The P4C187/P4C187L are 65, 536-bit ultra high speed static RAMs organized as 64K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V for the Low Power version, typically drawing 10µA. Access times as fast as 10 nanoseconds are available, Functional Block Diagram greatly enhancing system speeds. CMOS reduces power consumption to a low 743mW active, 193/83mW standby for TTL/CMOS inputs and only 5.5 mW standby for the P4C187L. The P4C187/P4C187L are available in 22-pin 300 mil DIP, 24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages providing excellent board level densities. Pin ConfigurationS DIP (P3, D3, C3) SOJ (J4) LCC configurations at end of datasheet Document # SRAM111 REV D Revised October 2013 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS Maximum Ratings(1) Sym Parameter RECOMMENDED OPERATING CONDITIONS Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% Industrial -40°C to +85°C 0V 5.0V ± 10% Military -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter 1.0 W CIN Input Capacitance COUT Output Capacitance PT Power Dissipation Commercial CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Conditions Typ Unit VIN=0V 5 pF VOUT=0V 7 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter P4C187 Test Conditions P4C187L Min Max Min Max Unit VIH Input High Voltage 2.2 VCC + 0.5 2.2 VCC + 0.5 V VIL Input Low Voltage -0.5(3) 0.8 -0.5(3) 0.8 V VHC CMOS Input High Voltage VCC - 0.2 VCC + 0.5 VCC - 0.2 VCC + 0.5 V VLC CMOS Input Low Voltage -0.5(3) 0.2 -0.5(3) 0.2 V VCD Input Clamp Diode Voltage VCC = Min, IIN = 18 mA -1.2 -1.2 V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min 0.4 0.4 V VOH Output High Voltage (TTL Load) IOH = -4 mA, VCC = Min Input Leakage Current VCC = Max, VIN = GND to VCC ILI VCC = Max, CE = VIH, VOUT = GND to VCC ILO Output Leakage Current ISB Standby Power Supply Current (TTL Input Levels) CE ≥ VIH, VCC = Max, f = Max, CE ≥ VHC, VCC = Max, f = 0, ISB1 Standby Power Supply Current (CMOS Input Levels) Outputs Open 2.4 MIL -10 2.4 +10 -5 V +5 µA -5 +5 N/A N/A -10 +10 -5 +5 IND/COM -5 +5 N/A N/A MIL — 40 — 40 IND/COM — 35 — N/A MIL — 20 — 1.0 IND/COM — 15 — N/A IND/COM MIL µA mA Outputs Open VIN ≤ VLC or VIN ≥ VHC mA N/A = Not applicable Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. Document # SRAM111 REV D 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4.This parameter is sampled and not 100% tested. Page 2 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym Parameter Temperature Range -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Unit Dynamic Operating Current* Commercial 180 170 160 155 ICC Industrial N/A 180 170 160 150 N/A N/A N/A N/A N/A mA 155 150 N/A N/A N/A N/A mA Military N/A N/A 170 160 155 150 145 145 145 145 mA * VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL. DATA RETENTION CHARACTERISTICS (P4C187L Military Temperature Only) Sym Parameter Test Conditions Min Typ* VCC= 2.0V Max VCC= 3.0V 2.0V Unit 3.0V VDR VCC for Data Retention 2.0 V ICCDR Data Retention Current CE ≥ VCC -0.2V, tCDR Chip Deselect to Data Retention Time VIN ≥ VCC -0.2V 0 ns tR† Operation Recovery Time or VIN ≤ 0.2V tRC§ ns 10 15 600 900 µA * TA = +25°C § tRC = Read Cycle Time † This Parameter is guaranteed but not tested DATA RETENTION WAVEFORM AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Sym Parameter tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 45 55 70 85 ns tAC Chip Enable Access Time 10 12 15 20 25 35 45 55 70 85 ns tOH Output Hold from Address Change 2 2 2 2 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 5 0 15 6 0 10 Document #SRAM111 REV D 20 8 0 12 25 10 0 15 35 12 0 20 45 17 0 25 55 20 0 35 70 25 0 45 85 30 0 55 ns 35 0 70 Unit ns ns 85 ns Page 3 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2(6) Notes: 5.CE is LOW and WE is HIGH for READ cycle. 6.WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7.Transition is measured ± 200 mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM111 REV D 8.Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Sym Parameter tWC Write Cycle Time 10 12 15 20 25 35 45 55 70 85 ns tCW Chip Enable Time to End of Write 8 10 12 15 20 25 30 35 40 45 ns tAW Address Valid to End of Wrtite 8 10 12 15 20 25 30 35 40 45 ns tAS Address Set-up Time 0 0 0 0 0 0 0 0 0 0 ns tWP Write Pulse Width 8 10 12 15 20 25 30 35 40 40 ns tAH Address Hold Time from End of Write 0 0 0 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 6 7 10 13 15 20 25 30 35 40 ns tDH Data Hold Time 0 0 0 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 6 0 7 0 8 0 12 0 15 0 17 0 20 0 25 0 30 0 35 0 Unit ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(9) Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document #SRAM111 REV D Page 5 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS Timing Waveform of Write Cycle No. 2 (CE Controlled)(10) AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Figure 1. Output Load Mode CE WE Output Power Standby H X High Z Standby Read L H DOUT Active Write L L High Z Active Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C187/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor Document # SRAM111 REV D is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 6 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS LCC PIN CONFIGURATIONS 22-Pin LCC (L3) Document # SRAM111 REV D 28-Pin LCC (L5) Page 7 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS ORDERING INFORMATION Document #SRAM111 REV D Page 8 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS SIDEBRAZED DUAL IN-LINE PACKAGE C3 Pkg # # Pins 22 (300 mil) Symbol Min Max A 0.100 0.200 b 0.014 0.023 b2 0.030 0.060 C 0.008 0.015 D 1.050 1.260 E 0.260 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - CERDIP DUAL IN-LINE PACKAGE Pkg # D3 # Pins 22 (300 mil) Symbol Min Max A - 0.225 b 0.015 0.020 b2 0.045 0.065 C 0.009 0.012 D 1.060 1.110 E 0.290 0.320 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 - α 0° 15° Document # SRAM111 REV D Page 9 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS SOJ SMALL OUTLINE IC PACKAGE J4 Pkg # # Pins 24 (300 mil) Symbol Min Max A 0.128 0.148 A1 0.082 - b 0.016 0.020 C 0.007 0.010 D 0.620 0.630 e 0.050 BSC E 0.335 BSC E1 E2 Q 0.292 0.300 0.267 BSC 0.025 - Pkg # L3 # Pins 22 RECTANGULAR LEADLESS CHIP CARRIER Symbol Min Max A 0.060 0.080 A1 0.050 0.068 B1 0.022 0.028 D 0.284 0.296 D1 0.150 BSC D2 0.075 BSC D3 - 0.296 E 0.484 0.496 E1 0.300 BSC E2 0.150 BSC E3 - 0.496 e 0.050 BSC h R = .012 j R = .012 L 0.039 0.051 L1 0.039 0.051 L2 0.058 0.072 ND 4 NE 7 Document # SRAM111 REV D Page 10 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS RECTANGULAR LEADLESS CHIP CARRIER L5 Pkg # # Pins 28 Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.342 0.358 D1 0.200 BSC D2 0.100 BSC D3 - 0.358 E 0.540 0.560 E1 0.400 BSC E2 0.200 BSC E3 - 0.558 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.045 0.055 L2 0.075 0.095 ND 5 NE 9 Pkg # P3 # Pins 22 (300 Mil) Symbol Min Max A - 0.210 A1 0.015 - b 0.014 0.022 b2 0.045 0.070 C 0.008 0.014 D 1.145 1.165 E1 0.240 0.280 E 0.300 0.325 e PLASTIC DUAL IN-LINE PACKAGE 0.100 BSC eB - 0.430 L 0.115 0.150 α 0° 15° Document # SRAM111 REV D Page 11 P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS REVISIONS DOCUMENT NUMBER SRAM 110 DOCUMENT TITLE P4C116 / P4C116L ULTRA HIGH SPEED 2K X 8 STATIC CMOS RAMS REV ISSUE DATE ORIGINATOR OR 1997 DAB New Data Sheet A Oct-2005 JDB Changed logo to Pyramid B Apr-2007 JDB Added 55, 70, and 85ns speeds C Oct-2011 JDB Minor correction on LCC pinout; reformatting D Oct-2013 JDB Minor correction to Write Cycle 1 timing diagram Document #SRAM111 REV D DESCRIPTION OF CHANGE Page 12