CY23020-1 20-output, 200-MHz Zero Delay Buffer Features Description • • • • • • • 335 ps max Total Timing Budget™ (TTB)™ window 2.5V or 3.3V outputs 20 LVCMOS outputs 50 MHz to 200 MHz output frequency 50 MHz to 200 MHz input frequency Integrated phase-locked loop (PLL) with lock indicator Spread Aware™—designed to work with SSFTG reference signals • 3.3V core power supply • Available in 48-pin TSSOP and QFN packages The CY23020-1-1 is a high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The device features a guaranteed TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. The CY23020-1 outputs are three-state when S1 = S2 = 0 for reduced power. When S1 = 1 and S2 = 0 the PLL is bypassed and the CY23020-1 functions as a fan-out buffer. Block Diagram Pin Configurations LOCKED 1 48 VDDC NC 2 47 Div REF GNDC FBIN– 3 46 REF– FBIN+ 4 45 REF+ VDD 5 44 VDD FBOUT 6 43 Q19 Q1 7 42 Q18 GND 8 41 GND Q2 9 40 Q17 Q3 10 39 Q16 Q17 VDD 11 38 VDD Q18 Q4 12 Q19 Q5 13 GND 14 Q6 15 Q7 Q1 PLL Q2 FBIN C1 C1C1 C1 S1:2 Output Control Logic RANGE MUL 48 47 46 45 44 F B O U T + V D D F B I N + F B I N - N C 43 L O C K 42 V D D C 41 V S S C 40 R E F - 39 R E F + 38 V D D 37 Q 1 9 Q 18 36 1 Q1 2 VSS VSS 35 3 Q2 Q 17 34 4 Q3 Q 16 33 5 VDD 6 Q4 7 Q5 Q 14 30 8 VSS VSS 9 Q6 Q 13 28 10 Q7 Q 12 27 11 VDD 12 CY23020-1 LOCK FBOUT 37 Q15 36 Q14 35 GND 34 Q13 16 33 Q12 VDD 17 32 VDD Q8 18 31 Q11 Q9 19 30 Q10 GND 20 29 GND S2 21 28 GNDC S1 22 27 VDDC MUL 23 26 C1 RANGE 24 25 GND 48-pin TSSOP VDD 32 4 8 -p in Q F N Q 15 31 Q 9 Q8 13 V S S 14 S 2 15 S 1 16 Cypress Semiconductor Corporation Document #: 38-07120 Rev. *B M U L R A N G E G N D C 1 17 18 19 20 • V D D C V S S C V S S Q 1 0 21 22 23 24 3901 North First Street • 29 VDD 26 Q 11 25 San Jose • CA 95134 • 408-943-2600 Revised November 5, 2002 CY23020-1 Pin Definitions[2] Pin No. Pin Name Pin Type TSSOP QFN REF+ REF– 45 46 39 40 I Reference Inputs: Output signals are synchronized to the crossing point of REF+ and REF– signals. Therefore REF– must be tied to VREF as defined in the DC characteristics table. In DC mode, the REF+/REF– inputs must be held at opposite logical states. For optimal performance, the impedances seen by these two inputs must be equal. FBIN+ FBIN– 4 3 46 45 I Feedback Inputs: Input FBIN+ must be fed by one of the outputs to ensure proper functionality. If the trace between FBIN+ and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the clock signal at REF+ input. FBIN– must be tied to VREF as defined in the DC characteristics table. In DC mode, FBIN+/FBIN– inputs must be held at opposite logical states. For best performance, the impedances seen by these two inputs must be equal. FBOUT 6 48 O Feedback Output: In order to complete the phase locked loop, an output must be connected back to the FBIN+ pin. Any of the outputs may actually be used as the feedback source. 7, 9, 10, 12, 13, 15, 16, 18, 19, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43 1,3,4,6,7,9,1 0,12,13,24,2 5,27,28,30,3 1,33,34,36,3 7 O Outputs: Refer to Tables 1–4 for the configuration of these outputs. RANGE1 24 18 I Frequency Range Selection Input: To determine the correct connection for this pin, refer to Table 2. This should be a static input LOCK 1 43 O PLL Locked Output: When this output is HIGH, the PLL in the CY23020-1 is in steady state operation mode (Locked). When this signal is LOW, the PLL is in the process of locking onto the reference signal. 22, 21 16,15 I Output/PLL Enable Selection bits: To determine appropriate settings, refer to Table 1. 5,11,26, 32 P Power Connection Q1:19 S1:2 VDD VDDC 27, 48 GNDC 28, 47 21, 42 Pin Description P Analog Power Connection: Connect to 3.3V. G Analog Ground Connection: Connect to common system ground plane. VDD 5, 11, 17, 32, 38, 44 38,47 P Output Buffer Power Connections: Connect to 2.5 or 3.3V, whichever is to be the reference for the output signals. GND 8, 14, 20, 25, 29, 35, 41 19 G Ground Connections: Connect to common system ground plane. 2,8,14,23,29 ,35 G Ground Connections VSS VSSC 22,41 G Ground Connections MUL[1] 23 17 I Multiplication Factor Select: When set HIGH, the outputs will run at twice the speed of the reference signal. This should be a static input C1[1] 26 20 I Output Configuration Bit: Establishes either 2.5V or 3.3V Full Swing Operation. To determine appropriate setting, refer to Table 3. This should be a static input NC 2 44 NC Do Not Connect: This pin must be left floating. This pin is used by the factory for testing purposes. Note: 1. RANGE and MUL have a ~100k pull-down. C1 has a 50k pull-down. These inputs (RANGE, MUL, C1) are static. 2. There are no power-up sequence requirements on the power supply pins of the CY23020-1. Document #: 38-07120 Rev. *B Page 2 of 10 CY23020-1 Table 1. Output Configuration S1 S2 Qx source PLL 0 0 Three-state 0 1 Reserved 1 0 Reference input Shutdown 1 1 PLL output Active Shutdown Table 2. Frequency Range Setting Range Output Frequency Range 0 50–100 MHz 1 100–200 MHz Table 3. Output Configuration Setting C1 Output Type 0 3.3V Full swing 1 2.5V Full swing Table 4. Frequency Multiplication Table MUL Output Frequency 0 FOUT = FREF 1 FOUT = FREF x 2 Spread Aware Many systems are designed to utilize Spread Spectrum Modulation clock technology. This technology is used to dramatically reduce Electro Magnetic Interference (EMI) in digital systems. Cypress has pioneered SSFTG development, and this product is designed to pass any SSFTG modulation that is present on the REF+ pin to its output clock signals. This capability also enhances the part to produce clocks with significantly smaller jitter and tracking skew on its output clocks. This is especially beneficial in systems that have downstream PLLs present. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, “EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.” How to Implement Zero Delay Typically, zero delay buffers (ZDBs) multiply (fan-out) single clock signals quantity while simultaneously reducing or mitigating the time delay associated with passing the clock through a buffering device. In many cases the output clock is Document #: 38-07120 Rev. *B adjusted, in phase, to occur later or more often before the device’s input clock to compensate for a design’s physical delay inadequacies. Most commonly this is done using a simple PCB trace as a time delay element. The longer the trace the earlier the output clock edges occur with respect to the reference input clock edges. In this way such effects as undesired transit time of a clock signal across a PCB can be compensated for. Inserting Other Devices in Feedback Path Due to the fact that the device has an external feedback path the user has a wide range of control over its output to input skewing effect. One of these is to be able to synchronize the outputs of an external clock that is resultant from any of the output clocks. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 1, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin (B), the signals at the destination device(s) (C) will be driven high at the same time the Reference clock provided to the ZDB goes high. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. There are constraints when inserting other devices. If the devices contain Phase-Locked Loops (PLLs) or excessively long delay times they can easily cause the overall clocking system to become unstable as the components interact. For these designs it is advisable to contact Cypress for applications support. Reference Signal Zero Delay Buffer Feedback Input ASIC/ Buffer C B A Figure 1. Output Buffer in the Feedback Path Component Characterization Set-up 24 O hm o n c h ip o u tp u t b u ffe r 4 in c h 5 0 o h m T lin e 5 pf Figure 2. Termination Networks Page 3 of 10 CY23020-1 Vref Source Cbyp Cbyp 50Ω FBIN- Ref- FBIN+ Ref+ FBOUT Q19 Q1 Q18 Q2 . . . Q17 . . . Q9 Q10 RS CL 50Ω RS CL Figure 3. Establishing Reference Voltages The CY23020-1 uses a differential input receiver to increase it’s rejection of common mode input noise and thus increase device performance. To ensure that any noise appears equally on both the REF– and REF+ pins, it is necessary to match the external impedance and circuitry seen at these pins. Figure 3 shows how this may be accomplished. The reference voltage, VREF can be generated by a resistor divider from a power supply. This potential will adjust the FBIN+ input’s triggering Document #: 38-07120 Rev. *B threshold. The reference voltage should be well bypassed so as to not introduce any single ended noise to the device. Note that the impedance (50 ohms) is also matched to the FBIN+ line. The 50 ohm resistor is used to create a “like” load on the REF– input clock signal and matches the 50-ohm source impedance of the REF+ input signal. If the input impedance is significantly different than 50 ohms, the reference resistor should be adjusted accordingly. Page 4 of 10 CY23020-1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condiParameter tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Description Test Conditions Unit VDD Voltage on any VDD pin with respect to GND –0.5 to +5.0 V VIN Voltage on any input pin with respect to GND –0.5 to VDD + 0.5 V TSTG Storage Temperature –65 to +150 °C TA Operation Temperature (TSSOP) 0 to +70 °C Operation Temperature (QFN) –40 to +85 °C TJ Junction Temperature +150 max °C PD Package Power Dissipation (TSSOP) 1 W Full Swing DC Electrical Characteristics VDDC = 3.3V ±5%, VDD = 2.5V ±5% or 3.3V ±5% Parameter Description Test Conditions VIH REF+, FBIN+ Inputs only VIL REF+, FBIN+ Inputs only VIH Logic Inputs only VIL Logic Inputs only IIH Output Current in HIGH state VIN = VDD, (MUL, C1, and RANGE) VIN = VDD, (REF±, FBIN×, S1, S2) Min. Typ. Max. Unit 2.0 V 0.8 V 0.7 × VDDC V 0.3 × VDDC V 100 µA 10 IIL Output Current in LOW state VIN = 0V 10 IPD Power-down Current 100 CIN Input Capacitance PLL disable mode, S1:S2 = 0 µA 5 pF 2.5V Full Swing DC Electrical Characteristics VDDC = 3.3V ±5%, VDD = 2.5V ±5% Parameter Description Test Conditions Min. IDD Supply Current IOH Output Current in HIGH State Measured at pin, no load network, VOH = VDD – 0.35V IOL Output Current in LOW State Measured at pin, no load network, VOL = 0.35V VREF External Reference Voltage Single-ended inputs, see Figure 3 Typ. Unloaded, 200 MHz Max. Unit 225 mA –14 mA 14 mA 1.19 1.50 V 3.3V Full Swing DC Electrical Characteristics VDDC = 3.3V ±5%, VDD = 3.3V ±5% Parameter Description IDD Supply Current Test Conditions Unloaded, 200 MHz IOH Output Current in HIGH State measured at pin, no load network, VOH = 2.4V IOL Output Current in LOW State measured at pin, no load network, VOL = 0.4V VREF External Reference Voltage Single-ended inputs, see Figure 3 Document #: 38-07120 Rev. *B Min. Typ. Max. Unit 240 mA –18 mA 14 0.34 × VDD mA 0.46 × VDD V Page 5 of 10 CY23020-1 Full Swing AC Electrical Characteristics VDDC = 3.3V ±5%, VDD = 2.5V ±5% or VDD = 3.3V ±5%, Load: (See term. diagram, CL= 5 pF) TSSOP Package Parameter FIN Description Input Frequency FOUT Output Frequency tISR Input Slew Rate (+ or –) tR Test Conditions Min. 50 Typ. Max. Unit 200 MHz 50 200 MHz Measured between 20% and 80% of input swing 1 6.5 V/ns Output Rise Rate Measured between 20% and 80% of output swing 1 6.5 V/ns tF Output Fall Rate Measured between 80% and 20% of output swing 1 6.5 V/ns tIDC Input Duty Cycle Tested at 50% swing 40 60 % tD Output Duty Cycle Measured at VDD/2, FOUT < 167 MHz Measured at VDD/2, FOUT >167 MHz 45 43 55 57 % tPD REF–FBIN skew Fout = Fref, VDD = 2.5V Fout = Fref, VDD = 3.3V –175 –175 175 225 ps tPD2 REF–FBIN skew Fout = Frefx2, VDD = 2.5V Fout = Frefx2, VDD = 3.3V –175 –225 175 225 ps tSK Output-Output Skew 85 ps Refin to any output, Fout = Fref 335 ps Refin to any output, Fout = Fref × 2 All outputs active, Fout = Fref 385 95 ps ps All outputs active, Fout = Fref 15 ps [3, 4] tTB Total Timing Budget window tJC tJC_RMS Peak Cycle-Cycle Jitter (1000 cycles max) RMS Cycle-Cycle Jitter tJP Period Jitter p-p All outputs active, Fout = Fref 95 ps tJP_RMS RMS Period Jitter All outputs active, Fout = Fref 15 ps tJL I/O Phase Jitter p-p All outputs active, Fout = Fref 150 ps tJLRMS RMS I/O Phase Jitter All outputs active, Fout = Fref 30 ps tJC2 Peak Cycle-Cycle Jitter (1000 cycles max) All outputs active, Fout = Fref × 2 145 ps tJCRMS2 RMS Cycle-Cycle Jitter All outputs active, Fout = Fref × 2 25 ps tJP2 Period Jitter p-p All outputs active, Fout = Fref × 2 150 ps tJPRMS2 RMS Period Jitter All outputs active, Fout = Fref × 2 40 ps tJL2 I/O Phase Jitter p-p All outputs active, Fout = Fref × 2 150 ps tJLRMS2 RMS I/O Phase Jitter All outputs active, Fout = Fref × 2 30 ps PSRR (Core) I/O Phase Jitter Sensitivity to Power Supply Variations 1Vpp modulation of 10 kHz–10MHz 300 pspp /V PSRR (Output) I/O Phase Jitter Sensitivity to Power Supply Variations 1Vpp modulation of 10 kHz–10MHz 700 pspp /V tLOCK Power-up lock time 1 ms tPWD Power-down time 1 ms tTSK Spread Spectrum Tracking skew 100 ps Notes: 3. MAX(TPD_MAX – TPD_MIN, TPD_MAX,(–1)*TPD_MIN) where TPD _MAX is the longest delay of refin to any output measured over at least 1000 cycles and TPD_MIN is the minimum (may be negative) delay observed over all outputs over at least 1000 cycles. 4. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect this parameter. Document #: 38-07120 Rev. *B Page 6 of 10 CY23020-1 Full Swing AC Electrical Characteristics VDDC =3.3V ±5%, VDD = 2.5V ±5% or VDD = 3.3V ±5%, Load: (See term. diagram, CL= 5 pf) QFN Package Parameter Description Test Conditions Min. 50 50 Typ. Max. Unit 200 MHz 200 MHz FIN FOUT Input Frequency Output Frequency tISR tR Input Slew Rate (+ or –) Output Rise Rate Measured between 20% and 80% of input swing Measured between 20% and 80% of output swing 1 1 6.5 6.5 V/ns V/ns tF tIDC Output Fall Rate Input Duty Cycle Measured between 80% and 20% of output swing Tested at 50% swing 1 40 6.5 60 V/ns % tD tPD Output Duty Cycle REF–FBIN skew Measured at VDD/2 Fout = Fref, VDD = 2.5V 45 –175 55 175 % ps tPD2 REF–FBIN skew Fout = Fref, VDD = 3.3V Fout = Frefx2, VDD = 2.5V –100 –175 175 175 ps Fout = Frefx2, VDD = 3.3V –150 tSK Output-Output Skew 175 85 ps tTB Total Timing Budget window[3,4] Refin to any output, Fout = Fref All outputs active, Fout = Fref × 2 335 385 ps ps tJC All outputs active, Fout = Fref 95 ps tJC_RMS Peak Cycle-Cycle Jitter (1000 cycles max) RMS Cycle-Cycle Jitter All outputs active, Fout = Fref 12 ps tJP tJP_RMS Period Jitter p-p RMS Period Jitter All outputs active, Fout = Fref All outputs active, Fout = Fref 95 17 ps ps tJL I/O Phase Jitter p-p All outputs active, Fout = Fref 170 ps tJLRMS RMS I/O Phase Jitter All outputs active, Fout = Fref 22 ps tJC2 Peak Cycle-Cycle Jitter (1000 cycles max) All outputs active, Fout = Fref × 2 145 ps tJCRMS2 RMS Cycle-Cycle Jitter All outputs active, Fout = Fref × 2 24 ps tJP2 Period Jitter p-p All outputs active, Fout = Fref × 2 170 ps tJPRMS2 RMS Period Jitter All outputs active, Fout = Fref × 2 28 ps tJL2 I/O Phase Jitter p-p All outputs active, Fout = Fref × 2 170 ps tJLRMS2 RMS I/O Phase Jitter All outputs active, Fout = Fref × 2 PSRR (Core) I/O Phase Jitter Sensitivity to Power Supply Variations 1Vpp modulation of 10 kHz–10MHz 300 28 pspp /V ps PSRR (Output) I/O Phase Jitter Sensitivity to Power Supply Variations 1Vpp modulation of 10 kHz–10MHz 700 pspp /V tLOCK Power-up lock time 1 ms tPWD Power-down time 1 ms tTSK Spread Spectrum Tracking skew 100 ps Document #: 38-07120 Rev. *B Page 7 of 10 CY23020-1 Ordering Information Base Part # Package TSSOP[5] Temperature Range CY23020ZC–1 48-pin CY23020ZC–1T 48-pin TSSOP—Tape and Reel Commercial, 0°C to +70°C CY23020LFI–1 48- pin QFN Industrial, –40°C to +85°C CY23020LFI–1T 48-pin QFN—Tape and Reel Industrial, –40°C to +85°C Commercial, 0°C to +70°C Package Diagrams 48-Lead Thin Shrunk Small Outline Package, Type II (6 mm × 12 mm) Z48 51-85059-B Note: 5. Theta J = 95° C/W for TSSOP package. Document #: 38-07120 Rev. *B Page 8 of 10 CY23020-1 Package Diagrams (continued) 48-Lead QFN (7x7 mm) LF48 51-85152-*A Spread Aware, Total Timing Budget, and TTB are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07120 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY23020-1 Document Title: CY23020-1 20-output, 200-MHz Zero Delay Buffer Document Number: 38-07120 REV. ECN No. Issue Date Orig. of Change ** 109287 10/30/01 SZV New Data Sheet *A 113758 07/22/02 CTK Updated to reflect latest characteristics data *B 118945 11/06/02 HWT Added the QFN Package in this device Document #: 38-07120 Rev. *B Description of Change Page 10 of 10