2 CY29972 3.3V, 125-MHz Multi-Output Zero Delay Buffer Table 1. Frequency Table[1] Features • • • • • • • • • • • • Output frequency up to 125 MHz 12 Clock outputs: frequency configurable 350 ps max. output-to-output skew Configurable output disable Two reference clock inputs for dynamic toggling Oscillator or crystal reference input Spread-spectrum-compatible Glitch-free output clocks transitioning 3.3V power supply Pin-compatible with MPC972 Industrial temperature range: –40°C to +85°C 52-pin TQFP package VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 0 0 0 0 FVC0 8x 0 0 0 1 12x 0 0 1 0 16x 0 0 1 1 20x 0 1 0 0 16x 0 1 0 1 24x 0 1 1 0 32x 0 1 1 1 40x 1 0 0 0 4x 1 0 0 1 6x 1 0 1 0 8x 1 0 1 1 10x 1 1 0 0 8x 1 1 0 1 12x 1 1 1 0 16x 1 1 1 1 20x Note: 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. Block Diagram Pin Configuration D Q Sync Frz D Q Sync Frz FB_OUT D Q Sync Frz SYNC FB_SEL1 SYNC VSS Output Disable Circuitry QC0 Data Generator VDDC SCLK SDATA 2 QC1 FB_SEL(0,1) SELC0 Sync Pulse SELC1 /2 0 1 QC2 2 14 15 16 17 18 19 20 21 22 23 24 25 26 QC3 /4, /6, /8, /10 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 QC2 VDDC 2 /2, /4, /6, /8 39 38 37 36 35 34 33 32 31 30 29 28 27 CY29972 QC3 SELB(0,1) QC0 QC1 /4, /6, /8, /10 SELB1 Sync Frz 1 2 3 4 5 6 7 8 9 10 11 12 13 VSS 2 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 XIN XOUT VDD INV_CLK SELA(0,1) SELC(0,1) D Q /4, /6, /8, /12 SELB0 QB3 Power-On Reset SELA1 QB2 MR#/OE SELA0 QB0 QB1 FB_SEL2 QA3 Sync Frz VDDC QA3 D Q QA2 QA2 FB_IN VSS QA0 QA1 LPF QA1 Sync Frz VDDC 0 1 0 1 VCO QA0 TCLK1 TCLK_SEL Phase Detector VSS D Q TCLK0 VCO_SEL XIN XOUT VCO_SEL PLL_EN REF_SEL 12 INV_CLK Cypress Semiconductor Corporation Document #: 38-07290 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 22, 2002 CY29972 Pin Description[2] Pin Name 11 XIN I 12 XOUT O 9 TCLK0 I PU I PU 10 TCLK1 44, 46, 48, 50 QA(3:0) PWR I/O Type Description Oscillator Input. Connect to a crystal. Oscillator Output. Connect to a crystal. External Reference/Test Clock Input. External Reference/Test Clock Input. VDDC O Clock Outputs. See Table 2 for frequency selections. 32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. 25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. 42, 43 SELA(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2. 40, 41 SELB(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2. 19, 20 SELC(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2. 5, 26, 27 FB_SEL(2:0) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. 52 VCO_SEL I PU VCO Divider Select Input. When set low, the VCO output is divided by 2. When set high, the divider is bypassed. See Table 1. 31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL. 6 PLL_EN I PU PLL Enable Input. When asserted high, PLL is enabled. And when low, PLL is bypassed. 7 REF_SEL I PU Reference Select Input. When high, the crystal oscillator is selected. And when low, TCLK (0,1) is the reference clock. 8 TCLK_SEL I PU TCLK Select Input. When LOW, TCLK0 is selected and when high TCLK1 is selected. 2 MR#/OE I PU Master Reset/Output Enable Input. When asserted low, resets all of the internal flip-flops and also disables all of the outputs. When pulled high, releases the internal flip-flops from reset and enables all of the outputs. 14 INV_CLK I PU Inverted Clock Input. When set high, QC(2,3) outputs are inverted. When set low, the inverter is bypassed. 3 SCLK I PU Serial Clock Input. Clocks data at SDATA into the internal register. 4 SDATA I PU Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 VDDC 3.3V power supply for output clock buffers. 13 VDD 3.3V power supply for PLL. 1, 15, 24, 30, 35, 39, 47, 51 VSS Common ground. Note: 2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. Document #: 38-07290 Rev. *A Page 2 of 8 CY29972 Description The CY29972 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output (FB_OUT) provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies up to125 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input (FB_IN) is connected to the feedback output (FB_OUT). The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs (refer to Frequency Table). The VCO frequency is then divided to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see Table 3 below). For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain the desired output relationships but will provide an enhanced PLL lock range. The CY29972 is also capable of providing inverted output clocks. When INV_CLK is asserted HIGH, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29972 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew. Table 2. VCO_SEL SELA1 SELA0 QA SELB1 SELB0 QB SELC1 SELC0 QC 0 0 0 VCO/8 0 0 VCO/8 0 0 VCO/4 0 0 1 VCO/12 0 1 VCO/12 0 1 VCO/8 0 1 0 VCO/16 1 0 VCO/16 1 0 VCO/12 0 1 1 VCO/24 1 1 VCO/20 1 1 VCO/16 1 0 0 VCO/4 0 0 VCO/4 0 0 VCO/2 1 0 1 VCO/6 0 1 VCO/6 0 1 VCO/4 1 1 0 VCO/8 1 0 VCO/8 1 0 VCO/6 1 1 1 VCO/12 1 1 VCO/10 1 1 VCO/8 Glitch-Free Output Frequency Transitions levels of any or all of the following pins changed “on the fly” while it is operating: SELA, SELB, SELC, and VCO_SEL. Customarily, when output buffers have their internal counters changed “on the fly,” their output clock periods will: SYNC Output 1. contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequencies to which the cycles are being transitioned. 2. contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequencies to which the cycles are being transitioned. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic Document #: 38-07290 Rev. *A In situations where output frequency relationships are not integer multiples of each other, the SYNC output provides a signal for system synchronization. The CY29972 monitors the relationship between the QA and QC output clocks. It provides a LOW-going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of QA and QC outputs, even though under some relationships the lower frequency clock could be used as a synchro- Page 3 of 8 CY29972 VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC Figure 1. Timing Diagram Document #: 38-07290 Rev. *A Page 4 of 8 CY29972 Power Management The individual output enable/freeze control of the CY29972 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial Start Bit data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Figure 2. Table 3. Suggested Oscillator Crystal Parameters Symbol Characteristic Min Typ Max Units Conditions TC Frequency Tolerance ±100 PPM Note 3 TS Frequency Temperature Stability ±100 PPM (TA –10 to +60°C)[3] TA Aging 5 PPM/Yr CL Load Capacitance 20 – pF Effective Series Resistance (ESR) 40 80 Ohms RESR (first 3 years @ 25°C)[3] The crystal’s rated load.[3] Note 44 Notes: 3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifications. 4. Larger values may cause this device to exhibit oscillator start-up problems. Document #: 38-07290 Rev. *A Page 5 of 8 CY29972 Maximum Ratings [5] Maximum input voltage relative to VSS: .............. VSS – 0.3V Maximum input voltage relative to VDD: ............... VDD + 0.3V Storage temperature: .............................–65 × C to +150 × C Operating temperature:............................–40 × C to +85 × C Maximum ESD protection ................................................ 2kV Maximum power supply: .................................................5.5V Maximum input current: .............................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD . Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C Parameter VIL Description Input Low Voltage Test Conditions Min. VSS Typ. – Max. 0.8 Unit V VIH IIL Input High Voltage Input Low Current[6] 2.0 – – VDD –120 V µA IIH VOL Input High Current Output Low Voltage[7] 10 0.5 µA V VOH IDDQ Output High Voltage[7] Quiescent Supply Current IOH = –20mA 10 15 V mA IDDA PLL Supply Current IDD Dynamic Supply Current VDD only QA and QB @ 60 MHz, QC @ 120 MHz, CL = 30 pF 15 225 20 mA QA and QB @ 25 MHz, QC @ 50 MHz, CL = 30pF CIN Input Pin Capacitance 125 4 IOL = 20mA 2.4 – – mA - pF Notes: 5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Inputs have pull-up/pull-down resistors that effect input current. 7. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. AC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C[8] Parameter Description Tr / Tf TCLK Input Rise/Fall Fref Reference Input Frequency Conditions Min Typ Note 9 Unit 3.0 ns Note 9 MHz Fxtal Crystal Oscillator Frequency 10 25 MHz FrefDC Reference Input Duty Cycle 25 75 % Fvco PLL VCO Lock Range 200 480 MHz Tlock Maximum PLL Lock Time 10 ms ns Tr / Tf see Table 3 Max [10] Output Clocks Rise / Fall Time Fout Maximum Output Frequency FoutDC Output Duty Cycle[10] 0.8V to 2.0V 0.15 1.2 Q (÷2) - 125 Q (÷4) 120 Q (÷6) 80 Q (÷8) [10] MHz 60 TCYCLE/2 – 750 TCYCLE/2 + 750 ps tpZL, tpZH Output Enable Time (all outputs) 2 10 ns tpLZ, tpHZ Output Disable Time[10](all outputs) 2 8 ns 350 ps [10] (peak to peak) TCCJ Cycle to Cycle Jitter TSKEW Any Output to Any Output Skew[10,11] Tpd Propagation Delay[11,12] TCLK0 ± 100 250 QFB = (÷8) TCLK1 ps –270 130 530 –330 70 470 ps Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. Maximum and minimum input reference is limited by VC0 lock range. 10. Outputs loaded with 30 pF each. 11. 50W transmission line terminated into VDD/2. 12. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter. Document #: 38-07290 Rev. *A Page 6 of 8 CY29972 Ordering Information Part Number Package Type Production Flow CY29972AI 52-pin TQFP Industrial, –40°C to +85°C Package Drawing and Dimensions Inches D Symbol Min. Nom. Max. A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 - 0.041 0.95 - 1.05 D - 0.0472 - - 12.00 - 0.394 - - 10.00 - - 0.015 0.22 - 0.38 D1 b 0.009 e D1 Millimeters L Min. Nom. 0.026 BSC 0.018 - 0.030 Max. 0.65 BSC 0.45 - 0.75 10° A1 A2 A L e b All product and company names are the trademarks of their respective holders. Document #: 38-07290 Rev. *A Page 7 of 8 CY29972 Revision History Document Title: 3.3V, 125 MHz Multi-Output Zero Delay Buffer Document Number: 38-07290 ECN NO. Issue Date Orig. of Change ** 111101 02/07/02 BRK New Data Sheet *A 122882 12/22/02 RBI Added power up requirements to Maximum Ratings REV. Document #: 38-07290 Rev. *A Description of Change Page 8 of 8