NCP5810 Dual 1 W Output AMOLED Driver Supply The NCP5810 is a dual−output DC/DC converter which can generate both a positive and a negative voltage. Both PWM converters achieve high efficiency for portable application. Thanks to the high output voltage accuracy and signal integrity the NCP5810 is particularly suitable for powering applications such as AMOLED display drivers. The output voltage of the inverter is fully configurable using external feedback resistors, where the output voltage of the boost is internally fixed. The switching regulator operates at 1.75 MHz which allows the use of small inductors and ceramic capacitors. In addition both converters are internally compensated which simplifies the design and reduces the PCB component count. Cycle−by−cycle peak current limit and thermal shut down provide value added features to protect the device. The NCP5810 is housed in a low profile space efficient 3 x 3 x 0.55 mm LLGA package. http://onsemi.com 1 12 PIN LLGA MU SUFFIX CASE 513AD MARKING DIAGRAM Features • • • • • • • • • 5810 AYWG G High Overall Efficiency: 83% (Refer to Figure 4) Low Noise 1.75 MHz PWM DC/DC Converter Positive Output Fixed + 4.6 V Negative Output from − 2.0 to − 15.0 V High Output Voltage Accuracy Excellent Line Transient Rejection Soft Start to Limit Inrush Current Enable Control Facility with True−Shut Down Small LLGA 3 x 3 x 0.55 mm Package 5810 = Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) Typical Applications • AMOLED Driver Supply ♦ ♦ ♦ ♦ ♦ Cellular Phones MP3 Player Digital Cameras Personal Digital Assistant and Portable Media Player GPS VOUTP 1 12 LXP SWP 2 11 PVIN PGND 3 10 SWN NCP5810 AGND 4 9 EN VREF 5 8 AVIN VS 6 7 FBN (Top View) 12−pin 3 x 3 x 0.55 mm LLGA Exposed pad must be soldered to PCB Ground plane ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2007 April, 2007 − Rev. 0 1 Publication Order Number: NCP5810/D NCP5810 L1 4.7 mH VBAT U1 12 LXP 11 PVIN SWP VOUTP C1 4.7 mF 3 ENABLE 9 8 VOUTP 1 C3 4.7 mF PGND NCP5810 EN VS 6 AVIN D1 C2 1 mF 4 FBN AGND VREF VBAT 2 5 SWN 7 C4 4.7 mF L2 4.7 mH R2 56 k C5 0.1 mF D1: ON NSR0320MW2 L1, L2: TDK VLF3010AT−4R7 C1: 4.7 mF 6.3 V X5R C2: 1 mF 6.3 V X5R 0603 C1,C3,C4: 4.7 mF 6.3 V X5R 0805 VOUTN 10 R1 536 k C6 10 pF Figure 1. Typical Application Circuit Option of powering CINP 4.7 mF Vbat L1 4.7 mH CINA 1 mF AVIN PVIN D2 SWP LXP VOUTP Thermal Shut down VOUTP MP0 COUTP 4.7 mF ENABLE BOOST PWM CONTROLLER EN Bangap 1.26 V MN1 Osc 1.75 Mhz VS MP1 SWN NEGATIVE BUCK PWM CONTROLLER D1 VOUTN 4.7 mH L2 Verf 1.26 V COUTN 4.7 mF R1 AGND FBN PGND VREF 0.1 mF Figure 2. Simplified Block Diagram http://onsemi.com 2 R2 10 pF NCP5810 PIN FUNCTION DESCRIPTION Pin Pin Name Type Description 1 VOUTP OUTPUT Positive Power Output: A filter capacitor is necessary on this pin for the stability of the loop, to smooth the current flowing into the load, and limit the noise created by the fast transients present in this circuitry. A 4.7 mF ceramic bypass capacitor to GND is recommended. Cares must be observed to avoid EMI through the PCB copper tracks connected to this pin. 2 SWP POWER Switch LXP: Positive power switch pin where one end of the L1 inductor is connected. Typical application uses a 4.7 mH inductor. 3 PGND POWER Power Ground: This pin is the power ground and carries the high switching current. A high quality ground must be provided to avoid any noise spikes/uncontrolled operation. Cares must be observed to avoid high−density current flow in a limited PCB copper track. 4 AGND POWER Analog Ground: This pin is the analog ground of the device notably used by VREF. 5 VREF OUTPUT Voltage Reference: This output provides a 1.265 V voltage reference used notably for the negative feedback resistive network. 6 VS INPUT Positive Output Voltage Sense: This pin is the output voltage sense input for the positive boost converter and must be connected to COUTP bypass capacitor. 7 FBN INPUT Feedback Negative: This pin is the feedback voltage input for the negative Buck−Boost inverter. The middle point of a resistive bridge divider must be connected here. The resistive network must be connected between VREF and the anode of external Schottky. 8 AVIN POWER Analog Power Supply: The external voltage supply is connected to this pin. A 4.7 mF ceramic capacitor must be connected across this pin and the power ground to achieve the specified output power parameters. 9 EN INPUT Enable: An active high logic level on this pin enables the circuit. A built−in pull−down resistor disables the device if the pin is left open. Also in disable condition the device provide a true cut−off from PVIN to VOUTP and SWN. 10 SWN INPUT Switch Negative: Negative power switch pin where one end of the L2 inductor is connected. Typical application uses a 4.7 mH inductor. 11 PVIN POWER Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must bypass this input to the ground. This capacitor should be placed as close a possible to this input. 12 LXP POWER Switch LXP: The inductor should be connected between this node and SWP. This output supplies power from PVIN and give a true−cut off function in disable condition. http://onsemi.com 3 NCP5810 MAXIMUM RATINGS (Note 1) Symbol Value Unit Vbat 7.0 V Human Body Model (HBM) ESD Rating are (Note 3) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 3) ESD MM 200 V ENP, ENN −0.3 ≤ Vin ≤ Vbat+0.3 1 V mA RqJC 12 °C/W Operating Ambient Temperature Range TA −40 to +85 °C Operating Junction Temperature Range TJ −40 to +125 °C Rating Power Supply Voltage (Note 2) Digital Input Voltage Digital Input Current LLGA 3x3 mm package (Notes 6 and 7) Thermal Resistance Junction−to−Case Maximum Junction Temperature TJMAX +150 °C Storage Temperature Range TSTG −65 to +150 °C Moisture Sensitivity (Note 5) MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTES: 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C 2. According to JEDEC standard JESD22−A108B. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins. 4. Latchup Current Maximum Rating: ±100 mA per JEDEC standard: JESD78., class II 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. 6. The thermal shutdown set to 165°C (typical) avoids irreversible damage on the device due to power dissipation. 7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max output current and external components selected. RqCA + 125 * TA * R qJC PD http://onsemi.com 4 NCP5810 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and VIN between 2.7 V to 4.6 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.7 V (Unless otherwise noted) Characteristic Symbol Min Typ Max Unit VOUTP 4.55 4.6 4.65 V IPEAKP_MAX 530 700 800 mA Switches P0 ON Resistance P0MOS RDSON − 320 640 mW Switches N1 ON Resistance N1MOS RDSON − 300 600 mW N1MOS L − 0.05 0.5 mA EFF − 85 − % 0 0 270 − − 145 POSITIVE BOOST DC/DC CONVERTER Positive Operational Output Voltage Range Maximum Inductor Peak Current Switches N1 Leakage Current At VIN = 4.2 V Efficiency (Notes 8, 9) Positive Output Current Available (Notes 9, 10) VIN ≥ 3.1 V VIN ≥ 2.9 V, TA between 0 to +85°C IOUTP mA Output Voltage Line Regulation IOUTP = 0 mA 2.7 < VIN < 4.6 LINE_RP − − 10 mV Output Voltage Line Transient Overshoot (Note 12) LINE_TP − 4 − mV Power Supply Ripple Rejection (Notes 9, 13) 1.0 Hz to 1.0 kHz 1.0 kHz to 10 kHz PSRRP − − 60 40 − − LOAD_RP − − 0.5 %/100mA LTRP − − 100 mV VOUTN −15 − −2.0 V IPEAKN_MAX 620 800 920 mA P2MOS RDSON − 700 1400 mW P2MOS L − 0.05 0.5 mA EFF − 80 − % − 0 175 − − 100 Output Voltage Load Regulation (Note 14) Output Voltage Load Transient Response: Overshoot and Undershoot Vs. Steady State Voltage (Notes 9, 15) dB NEGATIVE BUCK DC/DC CONVERTER Typical Negative Operational Output Voltage Range Peak Inductor Current (Note 9) Switches P2 ON Resistance Switches P2 Leakage Current At VIN = 4.2 V Efficiency (Notes 8, 9) Negative Output Power Available (Notes 9, 10) @ VOUTN = −5.4 V VIN ≥ 3.1 V VIN ≥ 2.9, TA between 0 to +85°C POUTN mA Output Voltage Reference 0 mA < IREF < 100 mA OVR −1 % 1.265 +1 % V Feedback Voltage Threshold in Steady State: 2.7 < VIN < 4.6 FBVN −2 % 0.632 +2 % mV Feedback Input Current FBICN −50 − 50 nA Output Voltage Line Regulation at IOUTN = 0 mA (Note 11) 2.7 < VIN < 4.6 LINE_RN − − 20 mV Output Voltage Line Transient Overshoot (Note 12) LINE_TN − 4 − mV Power Supply Ripple Rejection (Notes 9, 13) 1.0 Hz to 1.0 kHz 1.0 kHz to 10 kHz PSRRN − − 60 40 − − LOAD RN − − 0.5 %/100mA LTRN − − 100 mV Load Regulation (Notes 11, 14) Load Transient Response: Overshoot and Undershoot Vs. Steady State Voltage (Notes 9, 15) http://onsemi.com 5 dB NCP5810 ELECTRICAL CHARACTERISTICS (Min & Max Limits apply for TA between −40°C to +85°C and VIN between 2.7 V to 4.6 V. Typical values are referenced to TA = +25°C and VIN = 3.7 V, unless otherwise noted) Rating Symbol Min Typ Max Unit VIN 2.7 − 4.6 V Internal Oscillator Frequency, TA = 25°C, VIN = 3.7 V FOSC 1.6 1.75 1.9 MHz Maximum Duty Cycle MDCY 87 90 − % Stand by Current at IOUTP = IOUTN = 0 mA, EN = Low VIN = 4.2 V, TA between 0 to +85°C ISTB − − 2.0 mA Quiescent Current @ VOUTN = −5.4 V @ TA = +25°C Switching (Note 9) No Switching IQ − − 1.5 1.0 3.0 − Operational Power Supply mA Soft Start Time to limit the Inrush Current SST − 1.0 − ms Thermal Shut Down Protection TSD − 165 − °C Thermal Shut Down Protection Hysteresis TSDH − 15 − °C VIL − − 0.4 V Voltage Input Logic Low Voltage Input Logics High EN pin Pull Down Resistance VIH 1.2 − − V RENP 280 400 670 kW NOTES: 8. Efficiency is defined by 100 * (Pout / Pin), Vin = 3.1 to 4.2 V, L = VLF3010AT−4R7MR70 (DCR = 280 mW max, Isat = 700 mA), Load = 15 to 30 mA, Voutn = −5.4 V. 9. Guaranteed by design and characterized. 10. Typical application circuit and components depicted Figure 1. 11. Tested at 25°C and guaranteed from −40°C to +85°C by characterization. 12. Line drop and rise between 3.4 to 2.9 V in 50 ms at IOUT = 25 mA, VOUTN = −5.4 V. 13. Ripple = 0.2 V p−p at 25°C, Cout = 4.7 mF, IOUT = 0 to 100 mA, VIN = 3.7 V. 14. IOUT from 0 to 100 mA. 15. Load step 10 to 90 mA and 90 to 10 mA, rising and falling edge in 10 ms, Cout = 4.7 mF, VIN = 3.7 V. http://onsemi.com 6 NCP5810 TYPICAL OPERATING CHARACTERISTICS 80 80 VIN = 3.7 V EFFICIENCY (%) EFFICIENCY (%) VIN = 4.5 V 70 VIN = 3.7 V VIN = 2.9 V 60 VOUTN = −5.4 V 50 0 50 100 150 200 70 VIN = 2.9 V 60 VOUTN = −5.4 V 50 250 0 50 100 150 200 IOUT (mA) IOUT (mA) Figure 3. Efficiency vs. IOUT Figure 4. Efficiency vs. IOUT, L = MURAWA CXFU0208−4R7 plus Optional D2 NSR0320MW2 L = MURAWA CXFU0208−4R7 250 Figure 5. Line Transient Response VOUTP at 100 mA Figure 6. Line Transient Response VOUTN = −5.4 V, 1 VBAT, 500 mV/div DC, from 3.5 to 3.0 V in 50 ms 2 VOUTP, 10 mV/div AC, T = 400 ms/div 100 mA 1 VBAT, 500 mV/div DC, from 3.5 to 3.0 V in 50 ms 2 VOUTN, 10 mV/div AC, T = 400 ms/div Figure 7. Continuous Conduction Mode (CCM) Figure 8. Discontinuous Current Mode (DCM) 1 SWP, 5 V/div DC, 4 ILP, 100 mA/div, DC, IOUTP = 100 mA 1 SWP, 5 V/div, DC 4 ILP, 50 mA/div, DC, IOUTP = 20 mA Figures 7 and 8 have been done at VBAT = 3.7 V, VOUTN = −5.4 V http://onsemi.com 7 NCP5810 TYPICAL OPERATING CHARACTERISTICS Figure 9. Continuous Conduction Mode (CCM) Figure 10. Discontinuous Current Mode (DCM) 1 SWN, 5 V/div DC, 4 ILN, 100 mA/div, DC, IOUTN = 100 mA 1 SWN, 5 V/div, DC 4 ILN, 50 mA/div, DC, IOUTN = 20 mA Figure 11. Positive Output Voltage Ripple in CCM Figure 12. Negative Output Voltage Ripple in CCM 1 VOUTP, 10 mV/div AC, 4 ILP, 100 mA/div DC, IOUTP = 100 mA 1 VOUTN, 10 mV/div AC, 4 ILN, 100 mA/div DC, IOUTN = 100 mA VOUTP VOUTN Figure 13. Start−Up After Enable 1 VOUTP, 2 V/div, 2 VOUTN, 2 V/div, 3 EN pin, 2 V/div Figures 9 through 12 have been done at VBAT = 3.7 V and schematic depict Figure 1 http://onsemi.com 8 NCP5810 DETAILED OPERATING DESCRIPTION Option of powering V Bat L1 2.7 to 5.5 V CINA 1 mF AVIN PVIN AVIN BAND GAP 1.245 V THERMAL PROTECTION CINP 4.7 mF 4.7 mH LXP SWP SCHOTTKY MPO VOUTP VOUTP TSD COUTP ENABLE 4.7 mF X5R 10V True Cut−Off − FBP ERROR AMP NMOS FBP MAX DP 1.260 V + TSD − OPAMP PWM COMPP + 1 2 3 4 5 6 7 8RST MN1 Driver RAMP COMP SENSE CURRENT SET CLOCK ONE SHOT + IPEAK MAX P IPEAK COMP OSC Ipeak Max Threshold P − 1.75 Mhz ENABLE ENABLE EN − IPEAK MAX N 400 k Ipeak Max Threshold N IPEAK COMP PIVIN + SENSE CURRENT FBN + FBN ERROR − AMP PWM COMPN TSD − 623 mV + NSR0320 SWN D1 MP1 1 2 3 4 5 6 7 8 VOUTN RST COUTN LX2 4.7 mH MAX DN 4.7 mF X5R 10V R3 OPAMP VREF R4 1.260 V ONE S SET PGND AGND AGND PGND Figure 14. Functional Block Diagram Boost Operation Detailed Descriptions The NCP5810 is a dual−output DC/DC converter which can generate both a positive and a negative voltage. The output voltage of the inverter is fully configurable using external feedback resistors. The switching regulator operates at 1.75 MHz which allows the use of small inductors and ceramic capacitors. The both converters are internally compensated which simplifies the design and reduces the PCB component count. Cycle−by−cycle peak current limit and thermal provide value added features to protect the device. The internal oscillator provides a 1.75 MHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. During this phase the low side MN1 switch is turned on thus increasing the current through the inductor L1. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMPP compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the MN1 power switch is turned off until the rising edge of the next clock cycle. In http://onsemi.com 9 NCP5810 High Output Voltage Accuracy addition, there are five functions which can reset the flip−flop logic to switch off the MN1. The MAX DP monitors the pulse width and if it exceeds 88% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. IPEAK COMP compares the sensed inductor current with the IPEAK_MAX threshold set at 700 mA (nom). If the current exceeds this value, the controller turns off the NMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage. The boost regulator is internally compensated and provides a minimum of 45° phase margin. NCP5810 integrates a very accurate internal voltage reference (1% nom). Combined with the use of precision feedback resistors, the NCP5810 will achieve highly precise output voltages. Excellent Line Transient Rejection and High Power Supply Rejection Ratio High output voltage accuracy and signal integrity makes the NCP5810 the perfect solution for biasing Active Matrix OLED displays. In order to have a steady, clean display, OLEDs have to be biased by a very accurate voltage with high immunity to line and load transients. Both regulators have been specifically designed with high loop gain and high phase margin to satisfy the great constraints of AMOLED driving. The boost converter features a high power supply rejection ratio of 60 dB (nom). PSRR is defined by Buck−Boost Inverter Operation Figure 9 depicts the two intervals of the buck−boost operation in Continuous Conduction Mode (CCM) in a simplified way. During the first interval, the internal PMOS power switch is turned on and the external Schottky diode is reverse biased. The inductor stores energy through the battery while the load is supplied by the output capacitor to maintain regulation. During the second interval, the switch is turned off and the diode is forward biased, this allows the energy stored in the inductor to be supplied to both the load and the capacitor. In CCM, the voltage ratio of a buck−boost inverter converter can be expressed as: VOUT_N VIN + ǒOutputRipple Ǔ VinRipple * 20LOG Enable This input logic allows enabling and disabling the converter. An active high logic level on this pin enables the device. A built−in pull−down resistor disables the device if the pin is left open. D where D + TON TSW 1*D True Shut Down When in disable condition, the switch MP0 is turned off and truly isolates the battery from the output. The True shut down eliminates the leakage current from the battery to the load and significantly reduces battery consumption during disable condition, thus increasing battery life. The internal oscillator provides a 1.75 MHz clock signal to trigger the PWM controller on each rising edge (SET signal) which starts a cycle. During this phase the high side PMOS switch is turned on thus increasing the current through the inductor. The switch current is measured by the SENSE CURRENT and added to the RAMP COMP signal. Then PWM COMPN compares the output of the adder and the signal from ERROR AMP. When the comparator threshold is exceeded, the PMOS power switch is turned off until the rising edge of the next clock cycle. In addition, there are five functions which can reset the flip−flop logic to switch off the NMOS. The MAX DUTY CYCLE COMP monitors the pulse width and if it exceeds 88% (nom) of the cycle time the switch will be turned off. This limits the switch from being on for more than one cycle. IPEAK COMP compares the sensed inductor current with the IPEAK_MAX threshold set at 800 mA (nom). If the current exceeds this value, the controller turns off the PMOS switch for the remainder of the cycle. This is a safety function to prevent any excessive current that could overload the inductor and the power stage. The buck−boost inverter is internally compensated and provides a minimum of 45° phase margin. Inrush Current Limiting Circuitry Before the NCP5810 boost converter is turned on, it is unknown whether the output capacitor COUTP is charged or discharged. If the output capacitor is discharged, a common boost converter shows high inductor inrush current at start−up. The internal circuitry of the NCP5810 has been carefully designed to limit the amplitude of the inrush current at start−up. Thermal Shutdown When the IC junction temperature exceeds 165°C (nom), the power section of the device is disabled. Normal operation will resume when the junction temperature drops below 150°C (nom). Design Procedure Buck−Boost Inverter Output Voltage Setting The output voltage of the buck−boost inverter is also adjusted using external feedback resistors, and can be set from −2 V down to −15 V. Unlike for the boost converter, the lower feedback resistor R2 does not use the ground as a reference but uses the reference voltage (nom 1.265 V). Sequencing The sequencing is designed internally. The positive output first comes up, and then the negative output does. http://onsemi.com 10 NCP5810 typically for each DC/DC converter, it is recommended to use a 4.7 mH low profile inductor. Some recommended inductors include but are not limited to: R2 is placed between the feedback pin FBN (nom 632 mV) and the reference pin REF. As for the boost converter, the current flowing out of the feedback resistors must be as low as possible to ensure high efficiency in low load conditions. Nevertheless the feedback resistor impedance must not be too high to keep good voltage accuracy. Therefore it is recommended to use values in the 10 kW to 100 kW range for the lower resistor R2. The upper feedback resistor R1 can calculated using the following equation: R1 + R 2 ǒ But : VFBN + TDK: VLF3010AT−4R7MR70 (1.0 mm) TDK: MLP3216S2R7T (0.6 mm) SUMIDA: CDH2D09BNP (1.0 mm) MURAWA CXFU0208−4R7 (0.8 mm) Ǔ Schottky Diode Selection V OUTN * V FBN VFBN * VREF An external diode is required for the rectification of the negative output. The reverse voltage rating of the selected diode must be equal to or greater than the difference between the output voltage of the inverter and the input voltage. The average current rating of the diode must be greater than the maximum output load current. The peak current rating must be larger than the maximum peak inductor current. It is recommended to use a Schottky diode with lower forward voltage to minimize the power dissipation and therefore to maximize the efficiency of the converter. Also a particular care must be observed for parasitic capacitance versus reverse voltage and leakage current versus junction diode temperature. Both parameters are impacting the efficiency in low load condition and switching quiescent current. Some recommended Schottky diodes include but are not limited to: ON SEMICONDUCTOR: NSR0320MW2 VREF 2 So: R1 + R2 ǒ 1) 2 ŤV OUTNŤ V REF Ǔ For example, should one need –5.4 V for VOUTN, if a 56 kW ±1% is selected of R2, R1 should be selected according to the following equation: R1 + 56 5.4Ǔ + 536 kW "1% ǒ1 ) 21.265 Inductor Selection Three different electrical parameters need to be considered when selecting an inductor, the absolute value of the inductor, the saturation current and the DCR. During normal operation, the NCP5810 is intended to operate in Continuous Conduction Mode (CCM). The two equations below can be used to calculate the peak current for each converters: IPEAK_P + I OUT_P hP (1 * DP) ) ON SEMICONDUCTOR: RB521S30 ROHM: RSX051VA−30 PHILIPS: PMEG2005AEL V IN D P 2 LP F Input and Output Capacitors COUTP and COUTN store energy during the TOFF phase and sustain the load during the TON phase. In order to minimize the output ripple, a 4.7 mF low ESR multi−layer ceramic capacitor type X5R is recommended. To achieve high performances (signal integrity) two 4.7 mF 6.3 V X5R should be used to bypass the input supply, CINP and CINA. Also a particular care must be observed for DC−bias effects in ceramic capacitor. Actually smaller the case−size and higher the DC bias voltage, the bigger drop in capacitance. For a stability viewpoint the percentage drop in capacitance for the chosen input or output operating voltage must be limit to 20%. Some recommended capacitors include but are not limited to: For the boost converter IPEAK_N + I OUT_N hN DN (1 * DN) ) V IN D N 2 LN F For the buck−boost inverter Where VIN is the battery voltage, IOUT_X is the load current, L the inductor value, F the switching frequency, and DX the duty cycle. The global converter efficiency h varies with load current. A good approximation is to use h = 0.8 from the boost and h = 0.75 for the buck−boost inverter. It is important to ensure that the inductor current rating is high enough such that it not saturate. As the inductor size is reduced, the peak current for a given set of conditions increases along with higher current ripple so it is not possible to deliver maximum output power at lower inductor values. Finally an acceptable DCR must be selected regarding losses in the coil and must be lower than 300 mW to limit excessive voltage drop. In addition, as DCR is reduced, overall efficiency will improve. The inductor value should range between 2.7 mH and 6.8 mH, 4.7 mF 6.3 V 0603 TDK: C1608X5R0J475MT TDK: CGB4B1X5R0J475M (0.5 mm) 4.7 mF 10 V 0805 TDK: C2012X5R1A475MT MURATA: GRM219R61A475KE http://onsemi.com 11 NCP5810 ORDERING INFORMATION Device NCP5810MUTXG Package Shipping† LLGA−12 3x3 mm (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Demo Board Available: • The NCP5810GEVB/D evaluation board that configures the device in typical application to supply constant voltage. http://onsemi.com 12 NCP5810 PACKAGE DIMENSIONS 12 PIN LLGA MU SUFFIX CASE 513AD ISSUE A A D PIN ONE REFERENCE 2X 0.15 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B ÇÇÇ ÇÇÇ ÇÇÇ E MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.20 0.30 3.00 BSC 2.75 2.85 3.00 BSC 1.65 1.75 0.50 BSC 0.20 −−− 0.35 0.45 DIM A A1 b D D2 E E2 e K L 0.15 C TOP VIEW 0.10 C A 12X 0.08 C SIDE VIEW A1 C SEATING PLANE SOLDERING FOOTPRINT* 3.30 12X D2 0.56 1 1 6 e 0.25 PITCH 0.40 12X 12X K L E2 12 7 12X b 2.78 11X 0.10 C A B 0.05 C 0.28 NOTE 3 1.73 DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP5810/D