NCP2821 2.65 W Filterless with Selectable Gain Class−D Audio Amplifier NCP2821 is a cost effective mono audio power amplifier designed for portable communication device applications such as mobile phones. The internal gain setting between 6 dB and 12 dB will also save external gain setting resistors. To achieve a typical audio mono application, you only need an external capacitor for filtering the power supply. The NCP2821 processes analog inputs with a PWM technique that lowers significantly output noise and THD. This part is capable of delivering 2.65 W of continuous average power to a 4.0 BTL load from a 5.0 V power supply. Operating on a single 3 V supply, the output power stage can provide 500 mW to an 8.0 BTL load with less than 1% THD+N. For cellular handsets or PDAs it offers space and cost savings because no output filter is required when using inductive transducers. Its improved Class−D technology makes it suitable for portable devices. With 90% efficiency and very low shutdown current, it increases widely the lifetime of your battery compared to a ClassAB solution. It also minimizes the junction temperature. It fully rejects “pop & click” noises with a fast start−up time of 9 ms. Added to a −65 dB PSRR, the NCP2821 audio power amplifier is specifically designed to provide high quality output power from low supply voltage, requiring only 1 external capacitor. http://onsemi.com MARKING DIAGRAM 1 9−PIN FLIP−CHIP CSP FC SUFFIX CASE 499AL MAU A Y WW G 9−Pin Flip−Chip CSP • Optimized PWM Output Stage: Filterless Capability • Selectable Gain of 6 dB or 12 dB: No Need for External Gain Setting Resistors A1 A2 A3 INP GS OUTM B1 B2 B3 VP VP GND C1 C2 C3 INM • Efficiency up to 90% and Low Quiescent Current Maximum Battery Life and Minimum Heat High Output Power Capability: 1.4 W with 8.0 Load Wide Supply Voltage Range: 2.5−5.5 V Operating Voltage High Performance, THD+N of 0.05% Excellent PSRR (−65 dB): No Need for Voltage Regulation Surface Mounted Package 9−Pin Flip−Chip CSP Fully Differential Capability: No Need for Input Coupling Capacitor Very Fast Turn On Time: 9.0 ms (typ) “Pop and Click” Noise Protection Circuitry A1 = Device Code = Assembly Location = Year = Work Week = Pb−Free Package PIN CONNECTIONS Features • • • • • • • • MAUG AYWW SD OUTP (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 18 of this data sheet. 1 F Audio Input from DAC Input from Micro controller VP INP INM OUTM GS SD OUTP Applications • • • • Cellular Phone Personal Computer PDAs Portable Electronic Devices GND Cs 1.6 mm 2.7 mm Solution Size © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 0 1 Publication Order Number: NCP2821/D NCP2821 BATTERY Cs Vp Negative Differential Input INM Ri Rf OUTP Vih Data Processor Gain Control Vil RL = 8 RAMP GENERATOR GS CMOS Output Stage GS OUTM Rf INP Ri 300 k Positive Differential Input Shutdown Control SD Vih Vil Figure 1. Typical Application PIN DESCRIPTION Pin No. Symbol Type A1 INP I Positive Differential Input. Description A2 GS I Gain Select Input. A3 OUTM O Negative BTL Output. B1 Vp I Power Analog Positive Supply. Range: 2.5 V – 5.5 V. B2 Vp I Power Analog Positive Supply. Range: 2.5 V – 5.5 V. B3 GND I Analog Ground. C1 INM I Negative Differential Input. C2 SD I Shutdown Input. C3 OUTP O Positive BTL Output. http://onsemi.com 2 GND NCP2821 MAXIMUM RATINGS Rating Symbol Max Unit Vp 6.0 V Op Vp 2.5 to 5.5 V Input Voltage Vin −0.3 to Vp +0.3 V Power Dissipation (Note 1) Pd Internally Limited − Operating Ambient Temperature TA −40 to +85 °C Supply Voltage Operating Supply Voltage Max Junction Temperature TJ 150 °C Storage Temperature Range Tstg −65 to +150 °C Thermal Resistance Junction−to−Air RJA 90 (Note 2) °C/W − − > 2000 > 200 V − $100 mA ESD Protection Human Body Model (HBM) (Note 3) Machine Model (MM) (Note 4) Latchup Current @ TA = 85°C (Note 5) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. The thermal shutdown is set to 160°C (typical) avoiding irreversible damage to the device due to power dissipation. 2. For the 9−Pin Flip−Chip CSP package, the RJA is highly dependent of the PCB Heatsink area. For example, RJA can equal 195°C/W with 50 mm2 total area and also 135°C/W with 500 mm2. When using ground and power planes, the value is around 90°C/W, as specified in table. 3. Human Body Model: 100 pF discharged through a 1.5 k resistor following specification JESD22/A114. 4. Machine Model: 200 pF discharged through all pins following specification JESD22/A115. 5. Latchup Testing per JEDEC Standard JESD78. SD and GS are qualified at 70 mA versus 100 mA for the other pins. http://onsemi.com 3 NCP2821 ELECTRICAL CHARACTERISTICS (Limits apply for TA = +25°C unless otherwise noted) Symbol Conditions Min Typ Max Unit Operating Supply Voltage VP TA = −40°C to +85°C 2.5 − 5.5 V Supply Quiescent Current Idd VP = 3.6 V, RL = 8.0 VP = 5.5 V, No Load VP from 2.5 V to 5.5 V, No Load TA = −40°C to +85°C − − − − 2.5 3.1 − − − − − 4.5 mA Shutdown Current Isd Vp = 4.2 V, TA = +25°C − 0.5 Vp = 5.5 V, TA = +25°C Vp = 2.5 V to 5.5 V TA = −40°C to +85°C − − − 0.8 − − Characteristic A − − 1.4 A SD Voltage High Vsdih 1.2 − − V SD Voltage Low Vsdil − − 0.4 V GS Voltage High Vgsih 1.2 − − V GS Voltage Low Vgsil − − 0.4 V Differential Input Resistance Rin G = 6 dB − 150 − k G = 12 dB − 75 − Switching Frequency Gain k FSW Vp = 2.5 V to 5.5 V TA = −40°C to +85°C kHz 200 250 G RL = 8.0 , VGS = High 5.5 6 6.5 RL = 8.0 , VGS = Low 11.5 12 12.5 dB 200 300 − k 300 dB Resistance from SD to Gnd RSD Output Offset Voltage Vos TA = −40°C to +85°C −25 2.5 +25 mV Turn On Time TON Vp = 2.5 V to 5.5 V − 9 − ms Turn Off Time TOFF Vp = 2.5 V to 5.5 V − 5 − ms − 160 − Thermal Shutdown Temperature Tsd Output Noise Voltage Vn RMS Output Power RMS Output Power Po Po − − − 63 40 − − − RL = 8 , f = 1 kHz, THD+N < 1% Vp = 2.5 V Vp = 3.0 V Vp = 3.6 V Vp = 4.2 V Vp = 5.0 V − − − − − 0.32 0.48 0.7 0.97 1.38 − − − − − RL = 8 , f = 1 kHz, THD+N < 10% Vp = 2.5 V Vp = 3.0 V Vp = 3.6 V Vp = 4.2 V Vp = 5.0 V − − − − − 0.4 0.59 0.87 1.19 1.7 − − − − − RL = 4 , f = 1 kHz, THD+N < 1% Vp = 2.5 V Vp = 3.0 V Vp = 3.6 V Vp = 4.2 V Vp = 5.0 V − − − − − 0.49 0.72 1.06 1.62 2.12 − − − − − RL = 4 , f = 1 kHz, THD+N < 10% Vp = 2.5 V Vp = 3.0 V Vp = 3.6 V Vp = 4.2 V Vp = 5.0 V − − − − − 0.6 0.9 1.33 2.0 2.65 − − − − − http://onsemi.com 4 °C Vrms Vp = 3.6 V F = 20Hz to 20kHz No weighting filter A weighting filter W W W W NCP2821 ELECTRICAL CHARACTERISTICS (Limits apply for TA = +25°C unless otherwise noted) Characteristic Total Harmonic Distortion + Noise Symbol Conditions THD+N Vp = 5.0 V, RL = 8 , f = 1 kHz, Pout = 0.25 W Vp = 3.6 V, RL = 8 , f = 1 kHz, Pout = 0.25 W Efficiency Common Mode Rejection Ratio CMRR Power Supply Rejection Ratio Ci Audio Input Signal − Max − 0.05 − Unit % − 0.09 − RL = 8 , f = 1 kHz Vp = 5 V, Pout = 1.2 W Vp = 3.6 V, Pout = 600 mW − − 91 90 − − RL = 4 , f = 1 kHz Vp = 5 V, Pout = 2 W Vp = 3.6 V, Pout = 600 mW − − 82 81 − − % % dB −62 −59 −53 Vpripple_pk−pk = 200 mV, RL = 8 , Inputs AC grounded, Vp = 3.6 V f = 217 Hz f = 1 kHz dB − −63 −63 − − NCP2821 Ri INP Ci Typ Vp = 2.5 V to 5.5 V, G = 6 dB Vic = 0.5 V to Vp − 0.8 V Vp = 3.6 V, Vic = 1 Vpp G = 6 dB, f = 1 kHz G = 12 dB, f = 1 kHz PSRR + Min + OUTM Load Ri INM Measurement Input − OUTP VP 30 kHz Low Pass Filter GND 4.7 F + Power Supply − Figure 2. Test Setup for Graphs NOTES: 1. Unless otherwise noted, Ci = 100 nF and Ri= 150 k. Thus, the gain setting is 2 V/V and the cutoff frequency of the input high pass filter is set to 10 Hz. Input capacitors are shorted for CMRR measurements. 2. To closely reproduce a real application case, all measurements are performed using the following loads: RL = 8 means Load = 15 H + 8 + 15 H RL = 4 means Load = 15 H + 4 + 15 H Very low DCR 15 H inductors (50 m) have been used for the following graphs. Thus, the electrical load measurements are performed on the resistor (8 or 4 ) in differential mode. 3. For Efficiency measurements, the optional 30 kHz filter is used. An RC low−pass filter is selected with (100 , 47 nF) on each PWM output. http://onsemi.com 5 NCP2821 TYPICAL CHARACTERISTICS 100 100 90 90 EFFICIENCY (%) DIE TEMPERATURE (°C) NCP2821 80 70 60 50 40 Class AB 30 Vp = 5 V RL = 8 20 10 0 80 Class AB 70 Vp = 5 V RL = 8 60 50 40 30 NCP2821 20 0 0.5 1.0 0 0.2 0.4 Pout (W) 1.4 55 DIE TEMPERATURE (°C) NCP2821 80 EFFICIENCY (%) 1.2 60 90 70 60 50 40 Class AB 30 20 Vp = 3.6 V RL = 8 10 50 Class AB 45 Vp = 3.6 V RL = 8 40 35 30 25 NCP2821 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 Pout (W) 0.3 0.4 0.5 0.6 0.7 Pout (W) Figure 6. Die Temperature vs. P out Vp = 3.6 V, RL = 8 , f = 1 kHz @ TA = +25°C Figure 5. Efficiency vs. P out Vp = 3.6 V, RL = 8 , f = 1 kHz 160 90 80 140 DIE TEMPERATURE (°C) NCP2821 70 EFFICIENCY % 1.0 Figure 4. Die Temperature vs. Pout Vp = 5 V, RL = 8 , f = 1 kHz @ TA = +25°C 100 60 50 Class AB 40 30 20 Vp = 5 V RL = 4 10 0 0.8 Pout (W) Figure 3. Efficiency vs. Pout Vp = 5 V, RL = 8 , f = 1 kHz 0 0.6 Class AB 120 100 Vp = 5 V RL = 4 80 60 40 NCP2821 20 0 0.5 1.0 1.5 2.0 0 2.5 Pout (W) 0.5 1.0 1.5 Pout (W) Figure 8. Efficiency vs. Pout Vp = 5 V, RL = 4 , f = 1 kHz Figure 7. Die Temperature vs. Pout Vp = 5 V, RL = 4 , f = 1 kHz @ TA = +25°C http://onsemi.com 6 2.0 NCP2821 TYPICAL CHARACTERISTICS 100 90 80 90 EFFICIENCY % 70 DIE TEMPERATURE (°C) NCP2821 60 50 40 Class AB 30 Vp = 3.6 V RL = 4 20 10 0 Class AB 80 70 Vp = 3.6 V RL = 4 60 50 40 NCP2821 30 20 0 0.2 0.6 0.4 1.0 0.8 0 1.2 0.2 0.4 Pout (W) Vp = 5.0 V RL = 8 f = 1 kHz 0.1 1.0 Vp = 4.2 V RL = 8 f = 1 kHz 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.01 0 1.6 0.2 0.4 Pout (W) 1.0 1.2 10 Vp = 3.6 V RL = 8 f = 1 kHz THD+N (%) THD+N (%) 0.8 Figure 12. THD+N vs. Pout Vp = 4.2 V, RL = 8 , f = 1 kHz 10 0.1 0.01 0 0.6 Pout (W) Figure 11. THD+N vs. Pout Vp = 5 V, RL = 8 , f = 1 kHz 1.0 1.0 10 THD+N (%) THD+N (%) 10 0.01 0 0.8 Figure 10. Die Temperature vs. Pout Vp = 3.6 V, RL = 4 , f = 1 kHz @ TA = +25°C Figure 9. Efficiency vs. Pout Vp = 3.6 V, RL = 4 , f = 1 kHz 1.0 0.6 Pout (W) 1.0 Vp = 3 V RL = 8 f = 1 kHz 0.1 0.2 0.4 0.6 0.01 0 0.8 Pout (W) 0.1 0.2 0.3 0.4 Pout (W) Figure 14. THD+N vs. Pout Vp = 3 V, RL = 8 , f = 1 kHz Figure 13. THD+N vs. Pout Vp = 3.6 V, RL = 8 , f = 1 kHz http://onsemi.com 7 0.5 0.6 NCP2821 TYPICAL CHARACTERISTICS 1.0 10 Vp = 5 V RL = 4 f = 1 kHz Vp = 2.5 V RL = 8 f = 1 kHz THD+N (%) THD+N (%) 10 0.1 0.01 0 0.1 0.2 0.3 0.5 1.0 Figure 16. THD+N vs. Pout Vp = 5 V, RL = 4 , f = 1 kHz 2.5 10 Vp = 4.2 V RL = 4 f = 1 kHz 1.0 Vp = 3.6 V RL = 4 f = 1 kHz 0.1 0.5 1.0 1.5 0.01 0 2.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Pout (W) Figure 17. THD+N vs. Pout Vp = 4.2 V, RL = 4 , f = 1 kHz Figure 18. THD+N vs. Pout Vp = 3.6 V, RL = 4 , f = 1 kHz 10 10 Vp = 2.5 V RL = 4 f = 1 kHz THD+N (%) Vp = 3 V RL = 4 f = 1 kHz THD+N (%) 2.0 Figure 15. THD+N vs. Pout Vp = 2.5 V, RL = 8 , f = 1 kHz Pout (W) 1.0 0.1 0 1.5 Pout (W) THD+N (%) THD+N (%) 0 Pout (W) 0.1 0.01 0 0.1 0.01 0.4 10 1.0 1.0 0.2 0.4 0.6 0.8 1.0 0.1 0 1.0 Pout (W) 0.1 0.2 0.3 0.4 0.5 Pout (W) Figure 20. THD+N vs. Power Out Vp = 2.5 V, RL = 4 , f = 1 kHz Figure 19. THD+N vs. Power Out Vp = 3 V, RL = 4 , f = 1 kHz http://onsemi.com 8 0.6 NCP2821 TYPICAL CHARACTERISTICS 2.0 3.0 RL = 8 f = 1 kHz RL = 4 f = 1 kHz 2.5 1.5 Pout (W) Pout (W) 2.0 THD+N = 10% 1.0 THD+N = 1% THD+N = 10% 1.5 THD+N = 1% 1.0 0.5 0.5 3.0 3.5 4.0 4.5 0 2.5 5.0 3.0 3.5 4.0 4.5 5.0 POWER SUPPLY (V) POWER SUPPLY (V) Figure 21. Output Power vs. Power Supply RL = 8 @ f = 1 kHz Figure 22. Output Power vs. Power Suppy RL = 4 @ f = 1 kHz 10 10 1.0 1.0 THD+N (%) THD+N (%) 0 2.5 Vp = 2.5 V Vp = 3.6 V 0.1 Vp = 3.6 V Vp = 2.5 V 0.1 Vp = 5 V Vp = 5 V 100 1000 10000 0.01 10 100000 Figure 24. THD+N vs. Frequency RL = 4 , Pout = 250 mW @ f = 1 kHz −30 −30 −40 −40 Vp = 5 V Inputs to GND RL = 8 −70 100 1000 10000 Vp = 3.6 V Inputs to GND RL = 4 −70 100000 100000 Vp = 5 V −50 −60 Vp = 3.6 V −80 10 10000 Figure 23. THD+N vs. Frequency RL = 8 , Pout = 250 mW @ f = 1 kHz −20 −60 1000 FREQUENCY (Hz) −20 −50 100 FREQUENCY (Hz) PSSR (dB) PSSR (dB) 0.01 10 −80 10 100 1000 10000 100000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. PSRR vs. Frequency Inputs Grounded, RL = 8 , Vripple = 200 mvpkpk Figure 26. PSRR vs. Frequency Inputs grounded, RL = 4 , Vripple = 200 mVpkpk http://onsemi.com 9 NCP2821 −20 3.5 −30 3.0 QUIESCENT CURRENT (mA) CMMR (dB) TYPICAL CHARACTERISTICS −40 −50 −60 Vp = 3.6 V RL = 8 −70 −80 10 100 1000 10000 2.5 2.0 Thermal Shutdown Vp = 3.6 V RL = 8 1.5 1.0 0.5 0 120 100000 130 FREQUENCY (Hz) 160 Figure 28. Thermal Shutdown vs. Temperature Vp = 5 V, RL = 8 , 900 2.8 RL = 8 800 QUIESCENT CURRENT (mA) SHUTDOWN CURRENT (nA) 150 TEMPERATURE (°C) Figure 27. PSRR vs. Frequency Vp = 3.6 V, RL = 8 , Vic = 200 mvpkpk 700 600 500 400 300 200 100 0 2.5 3.5 4.5 RL = 8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 5.5 3.5 4.5 5.5 POWER SUPPLY (V) POWER SUPPLY (V) Figure 29. Shutdown Current vs. Power Supply RL = 8 Figure 30. Quiescent Current vs. Power Supply RL = 8 1000 1000 Vp = 5 V RL = 8 100 NOISE (Vrms) Vp = 3.6 V RL = 8 NOISE (Vrms) 140 No Weighting 100 No Weighting With A Weighting 10 10 100 With A Weighting 1000 10000 10 10 FREQUENCY (Hz) 100 1000 10000 FREQUENCY (Hz) Figure 31. Noise Floor, Inputs AC Grounded with 1 F Vp = 3.6 V Figure 32. Noise Floor, Inputs AC Grounded with 1 F Vp = 5 V http://onsemi.com 10 NCP2821 8 11 TURN OFF TIME (mS) TURN ON TIME (mS) TA = +85°C 10 TA = +25°C 9 TA = −40°C 8 7 TA = +25°C TA = −40°C 6 5 TA = +85°C 7 6 2.5 3.5 4.5 4 2.5 5.5 3.5 4.5 5.5 POWER SUPPLY (V) POWER SUPPLY (V) Figure 33. Turn on Time Figure 34. Turn off Time Output differential voltage Turn on time Output differential voltage Turn off time Shutdown signal Shutdown signal 0 2 4 6 8 10 12 (ms) 14 16 18 20 0 Figure 35. Turn on sequence Vp = 3.6 V, RL = 8 1 2 3 4 5 6 (ms) 7 8 Figure 36. Turn off sequence Vp = 3.6 V, RL = 8 http://onsemi.com 11 9 10 NCP2821 DESCRIPTION INFORMATION Detailed Description The basic structure of the NCP2821 is composed of one analog pre−amplifier, a pulse width modulator and an H−bridge CMOS power stage. The first stage is externally configurable with gain−setting resistor Ri and the internal fixed feedback resistor Rf (the closed−loop gain is fixed by the ratios of these resistors) and the other stage is fixed. The load is driven differentially through two output stages. The differential PWM output signal is a digital image of the analog audio input signal. The human ear is a band pass filter regarding acoustic waveforms, the typical values of which are 20 Hz and 20 kHz. Thus, the user will hear only the amplified audio input signal within the frequency range. The switching frequency and its harmonics are fully filtered. The inductive parasitic element of the loudspeaker helps to guarantee a superior distortion value. (5.0 ms). This method to turn on the device is optimized in terms of rejection of “pop and click” noises. Thus, the total turn on time to get full power to the load is 9 ms (typical) (see Figure 35). The device has the same behavior when it is turned−off by a logic low on the shutdown pin. No power is delivered to the load 5 ms after a falling edge on the shutdown pin (see Figure 36). Due to the fast turn on and off times, the shutdown signal can be used as a mute signal as well. Shutdown Function The device enters shutdown mode when the shutdown signal is low. During the shutdown mode, the DC quiescent current of the circuit does not exceed 1.5 A. Current Breaker Circuit The maximum output power of the circuit corresponds to an average current in the load of 820 mA. In order to limit the excessive power dissipation in the load if a short−circuit occurs, a current breaker cell shuts down the output stage. The current in the four output MOS transistors are real−time controlled, and if one current exceeds the threshold set to 1.5 A, the MOS transistor is opened and the current is reduced to zero. As soon as the short−circuit is removed, the circuit is able to deliver the expected output power. This patented structure protects the NCP2821. Since it completely turns off the load, it minimizes the risk of the chip overheating which could occur if a soft current limiting circuit was used. Power Amplifier The output PMOS and NMOS transistors of the amplifier have been designed to deliver the output power of the specifications without clipping. The channel resistance (Ron) of the NMOS and PMOS transistors is typically 0.3. Turn On and Turn Off Transitions In order to eliminate “pop and click” noises during transition, the output power in the load must not be established or cutoff suddenly. When a logic high is applied to the shutdown pin, the internal biasing voltage rises quickly and, 4 ms later, once the output DC level is around the common mode voltage, the gain is established slowly http://onsemi.com 12 NCP2821 APPLICATION INFORMATION NCP2821 PWM Modulation Scheme is applied, OUTP duty cycle is greater than 50% and OUTM is less than 50%. With this configuration, the current through the load is 0 A most of the switching period and thus power losses in the load are lowered. The NCP2821 uses a PWM modulation scheme with each output switching from 0 to the supply voltage. If Vin = 0 V outputs OUTM and OUTP are in phase and no current is flowing through the differential load. When a positive signal OUTP OUTM +Vp 0V −Vp Load Current 0A Figure 37. Output Voltage and Current Waveforms into an Inductive Loudspeaker DC Output Positive Voltage Configuration Voltage Gain Optional Output Filter The first stage is an analog amplifier. The second stage is a comparator: the output of the first stage is compared with a periodic ramp signal. The output comparator gives a pulse width modulation signal (PWM). The third and last stage is the direct conversion of the PWM signal with MOS transistors H−bridge into a powerful output signal with low impedance capability. With an 8 load, the total gain of the device is typically set to: − 12 dB if a low level is applied to the GS pin − 6 dB if a high level is applied to the GS pin This filter is optional due to the capability of the speaker to filter by itself the high frequency signal. Nevertheless, the high frequency is not audible and filtered by the human ear. An optional filter can be used for filtering high frequency signal before the speaker. In this case, the circuit consists of two inductors (15 H) and two capacitors (2.2 F) (Figure 38). The size of the inductors is linked to the output power requested by the application. A simplified version of this filter requires a 1 F capacitor in parallel with the load, instead of two 2.2 F connected to ground (Figure 39). Cellular phones and portable electronic devices are great applications for Filterless Class−D as the track length between the amplifier and the speaker is short, thus, there is usually no need for an EMI filter. However, to lower radiated emissions as much as possible when used in filterless mode, a ferrite filter can often be used. Select a ferrite bead with the high impedance around 100 MHz and a very low DCR value in the audio frequency range is the best choice. The MPZ1608S221A1 from TDK is a good choice. The package size is 0603. Input Capacitor Selection (Cin) The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with Rin, the cut−off frequency is given by Fc + 2 1 Ri Ci . When a 6 dB gain is chosen the internal impedance is set to 150 k. With a 12 dB gain, the internal resistance is 75 k and thus an input capacitor value between 10 nF and 1 F will give a cutoff frequency between 1 Hz and 212 Hz. The NCP2821 also includes a built in low pass filtering function. Its cutoff frequency is set to 20 kHz. http://onsemi.com 13 NCP2821 15 H 15 H OUTM RL = 8 2.2 F 1.0 F 2.2 F RL = 8 OUTM OUTP 15 H OUTP 15 H Figure 38. Advanced Optional Audio Output Filter Figure 39. Optional Audio Output Filter RL = 8 OUTM FERRITE CHIP BEADS OUTP Figure 40. Optional EMI Ferrite Bead Filter Cs VP INP Differential Audio Input from DAC OUTM INM OUTP SD Input from Microcontroller GND Figure 41. NCP2821 Application Schematic with Fully Differential Input Configuration Cs VP Differential Audio Input from DAC INP OUTM INM FERRITE CHIP BEADS Input from Microcontroller OUTP SD GND Figure 42. NCP2821 Application Schematic with Fully Differential Input Configuration and Ferrite Chip Beads as an Output EMI Filter http://onsemi.com 14 NCP2821 Cs Ci VP INP Differential Audio Input from DAC OUTM INM FERRITE CHIP BEADS Ci OUTP SD Input from Microcontroller GND Figure 43. NCP2821 Application Schematic with Differential Input Configuration and High Pass Filtering Function Cs Ci VP INP Single−Ended Audio Input from DAC OUTM INM Ci OUTP SD Input from Microcontroller GND Figure 44. NCP2821 Application Schematic with Single Ended Input Configuration http://onsemi.com 15 NCP2821 Vp J1 C4 4.7 F U1 J7 Rf INM Vp Ri 100 nF OUTP BYP GS J2 RAMP GENERATOR J3 RL = 8 C1 Data Processor Gain Control GS OUTM BYP C2 100 nF INP Ri Rf 300 k J8 Shutdown Control GND SD Vp J9 Vp CL = 6 dB J10* J5 CL = NCP2821 ON J5 CL = NCP2821 OFF J6* J4 J9 CL = 12 dB *J6, J10 Not Mounted Figure 45. Schematic of the Demonstration Board of the 9−pin Flip−Chip CSP Device Figure 46. Silkscreen Layer http://onsemi.com 16 NCP2821 A 1.0 F low ESR ceramic capacitor can also be used with slightly degraded performances on the THD+N from 0.06% up to 0.2%. In a two layers application, if both Vp pins are connected on the top layer, a single 4.7 F decoupling capacitor will optimize the THD+N level. The NCP2821 power audio amplifier can operate from 2.5 V until 5.5 V power supply. With less than 2% THD+N, it delivers 500 mW rms output power to a 8.0 load at Vp =3.0 V and 1.0 W rms output power at Vp = 4.0 V. PCB Layout Information NCP2821 is suitable for low cost solution. In a very small package it gives all the advantages of a Class−D audio amplifier. The required application board is focused on low cost solution too. Due to its fully differential capability, the audio signal can only be provided by an input resistor. If a low pass filtering function is required, then an input coupling capacitor is needed. The values of these components determine the voltage gain and the bandwidth frequency. The battery positive supply voltage requires a good decoupling capacitor versus the expected distortion. When the board is using Ground and Power planes with at least 4 layers, a single 4.7 F filtering ceramic capactior on the bottom face will give optimized performance. Note Figure 47. Top Layer Note: This track between Vp pins is only needed when a 2 layers board is used. In case of a typical 4 or more layers, the use of laser vias in pad will optimize the THD+N floor. The demonstration board delivered by ON Semiconductor is a 4 Layers with Top, Ground, Power Supply and Bottom. http://onsemi.com 17 NCP2821 Bill of Materials PCB Footprint Item Part Description Ref Manufacturer Part Number 1 NCP2821 Audio Amplifier U1 2 Ceramic Capacitor 100 nF, 50 V, X7R C1, C2 0603 TDK C1608X7R1H104KT 3 Ceramic Capacitor 4.7 F, 6.3 V, X5R C4 0603 TDK C1608X5R0J475MT 4 PCB Footprint J7, J8 5 I/O connector. It can be plugged by MC−1,5/3−ST−3,81 J2 Phoenix Contact MC−1,5/3−G 6 I/O connector. It can be plugged by BLZ5.08/2 (Weidmuller Reference) J1, J3 Weidmuller SL5.08/2/90B 7 Jumper Connector, 400 mils J4 Harwin D3082−B01 8 Jumper Header Vertical Mount 3*1, 2.54 mm. J5, J9 Tyco Electronics / AMP 5−826629−0 NCP2821 ORDERING INFORMATION Device NCP2821FCT1G Marking Package Shipping† MAU 9−Pin Flip−Chip CSP (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 18 NCP2821 PACKAGE DIMENSIONS 9−PIN FLIP−CHIP CSP FC SUFFIX CASE 499AL−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. −A− 4X D 0.10 C −B− E DIM A A1 A2 D E b e D1 E1 TOP VIEW A 0.10 C 0.05 C −C− MILLIMETERS MIN MAX 0.540 0.660 0.210 0.270 0.330 0.390 1.450 BSC 1.450 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC A2 A1 SIDE VIEW SEATING PLANE D1 e C B e E1 A 9X b 1 2 3 0.05 C A B 0.03 C BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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