MOTOROLA MC12040FN

Order this document by MC12040/D
The MC12040 is a phase–frequency detector intended for use in systems
requiring zero phase and frequency difference at lock. In combination with a
voltage controlled oscillator (such as the MC1648, MC12147, MC12148 or
MC12149), it is useful in a broad range of phase–locked loop applications.
• Operating Frequency = 80 MHz Typical
PHASE–FREQUENCY
DETECTOR
Pin Conversion Table
14 PIN DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20 PIN PLCC
2
3
4
6
8
9
10
12
13
14
16
18
19
20
SEMICONDUCTOR
TECHNICAL DATA
Outputs
Inputs
R
V
U
D
U
D
0
0
1
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
14
1
P SUFFIX
PLASTIC PACKAGE
CASE 646
8
19
3
4
FN SUFFIX
PLASTIC PACKAGE
CASE 775
(PLCC)
Not Recommended for New Designs
LOGIC DIAGRAM
4 U (fR>fV)
3 U (fR>fV)
R6
R Q
S
S
R Q
12 D (fV>fR)
11 D (fV>fR)
V9
PIN CONNECTIONS
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Vref
NC
VCC
VC
Output
Gnd
Power Ground
(Top View)
VCC1 = Pin 1
VCC2 = Pin 14
VEE = Pin 7
ORDERING INFORMATION
TRUTH TABLE
This is not strictly a functional truth table; i.e., it does not cover all possible
modes of operation. However, it gives a sufficient number of tests to
ensure that the device will function properly in all modes of operation.
Device
Operating
Temperature Range
Package
MC12040P
TA = 0° to +75°C
Plastic
 Motorola, Inc. 1997
Rev 3
MC12040
ELECTRICAL CHARACTERISTICS
The MC12040 has been designed to meet the dc
specifications shown in the test table after thermal
equilibrium has been established. Outputs are terminated
through a 50 ohm resistor to +3.0 V for +5.0 V tests and
through a 50 ohm resistor to –2.0 V for –5.2 V tests.
NOTE: For more information on using an ECL device in a
+5V system, refer to Motorola Application Note
AN1406/D, “Designing with PECL (ECL at +5.0V)”
6
R
9
V
U
U
4
3
D
11
D
12
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
Supply Voltage = –5.2V
VIHmax
VILmin
VIHAmin
VILAmax
VEE
0°C
–0.840
–1.870
–1.145
–1.490
–5.2
25°C
–0.810
–1.850
–1.105
–1.475
–5.2
75°C
–0.720
–1.830
–1.045
–1.450
–5.2
MC12040
Symbol
Characteristics
Pi
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS BELOW
0°C
Min
25°C
Max
75°C
Min
Max
Min
Max
–120
–60
mAdc
350
350
µAdc
IE
Power Supply Drain
7
IINH
Input Current
6
9
VOH1
Logic “1”
Output Voltage
3
4
11
12
–1.000
–0.840
–0.960
–0.810
–0.900
–0.720
Logic “0”
Output Voltage
3
4
11
12
–1.870
–1.635
–1.850
–1.620
–1.830
–1.595
Logic “1”
Input Voltage
3
4
11
12
–1.020
Logic “0”
Input Voltage
3
4
11
12
VOL1
VOHA2
VOLA2
Unit
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
7
1,14
7
7
1,14
1,14
7
1,14
7
1,14
7
1,14
7
1,14
6
9
Vdc
Vdc
Vdc
–0.980
–0.920
6.9
Vdc
–1.615
–1.600
9
6
9
6
–1.575
6
9
6
9
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
0°C
+4.160
+3.130
+3.855
+3.510
+5.0
25°C
+4.190
+3.150
+3.895
+3.525
+5.0
75°C
+4.280
+3.170
+3.955
+3.550
+5.0
Supply Voltage = +5.0V
MC12040
Symbol
Characteristics
Pin
Pi
Under
Test
TEST VOLTAGE APPLIED TO PINS BELOW
0°C
Min
25°C
Max
75°C
Min
Max
Min
Max
–115
–60
mAdc
350
350
µAdc
IE
Power Supply Drain
7
IINH
Input Current
6
9
VOH1
Logic “1”
Output Voltage
3
4
11
12
4.000
4.160
4.040
4.190
4.100
4.280
Logic “0”
Output Voltage
3
4
11
12
3.190
3.430
3.210
3.440
3.230
3.470
Logic “1”
Input Voltage
3
4
11
12
3.980
Logic “0”
Input Voltage
3
4
11
12
VOL1
VOHA2
VOLA2
2
Unit
VIHmax
VILmin
VIHAmin
VILAmax
6
9
VEE
(VCC)
Gnd
1,14
7
1,14
1,14
7
7
1,14
7
1,14
7
1,14
7
1,14
7
Vdc
Vdc
Vdc
4.020
4.080
6.9
Vdc
3.450
3.460
3.490
9
6
9
6
6
9
6
9
MOTOROLA RF/IF DEVICE DATA
MC12040
Figure 1. AC Tests
VCC = +2.0V
To Scope Channel A
5.0µF
0.1µF
1
14
4
Pulse
Gen 1
PRF = 5.0MHz
Duty Cycle = 50%
t+ = t– = 1.5ns ±0.2ns
6
U
R
3
U
Pulse
Gen 2
To Scope Channel B
11
D
9
V
12
D
7
t–
Pulse
Gen 1
50%
t+
90%
10%
50%
t+–
t++
Output
Waveform B
t+
50%
NOTES:
1 All input and output cables to the scope are equal lengths of 50Ω
coaxial cable.
2 Unused input and outputs are connected to a 50Ω resistor to
ground.
3 The device under test must be preconditioned before performing
the ac tests. Preconditioning may be accomplished by applying
pulse generator 1 for a minimum of two pulses prior to pulse generator 2. The device must be preconditioned again when inputs to
pins 6 and 9 are interchanged. The same technique applies.
+1.1V
90%
t++
Output
Waveform A
+0.3V
t–
50%
t+–
VEE = –3.2 or –3.0V
+1.1V
20ns
Pulse
Gen 2
0.1µF
10%
+0.3V
t–
80%
t+
20%
t+
80%
t–
20%
MC12040
0°C
Symbol
Characteristic
25°C
85°C
TEST VOLTAGES/WAVEFORMS
APPLIED TO PINS LISTED
Pulse
Gen 1
Pulse
Gen 2
Pi
Pin
Under
Test
Output
Waveform
Max
Max
Max
Unit
VEE
–3.0 or
–3.2V
VCC
+2.0V
t6+4+
t6+12+
t6+3–
t6+11–
t9+11+
t9+3+
t9+12–
t9+4–
Propagation Delay
6,4
6,12
6,3
6,11
9,11
9,3
9,12
9,4
B
A
A
B
B
A
A
B
4.6
6.0
4.5
6.4
4.6
6.0
4.5
6.4
4.6
6.0
4.5
6.4
4.6
6.0
4.5
6.4
5.0
6.6
4.9
7.0
5.0
6.6
4.9
7.0
ns
6
9
6
9
9
6
9
6
9
6
9
6
6
9
6
9
7
1,14
t3+
t4+
t11+
t14+
Output Rise Time
3
4
11
14
A
B
B
A
3.4
3.4
3.8
ns
6
6
9
9
9
9
6
6
7
1,14
t3–
t4–
t11–
t14–
Output Fall Time
3
4
11
14
A
B
B
A
3.4
3.4
3.8
ns
6
6
9
9
9
9
6
6
7
1,14
MOTOROLA RF/IF DEVICE DATA
3
MC12040
APPLICATIONS INFORMATION
The MC12040 is a logic network designed for use as a
phase comparator for MECL–compatible input signals. It
determines the “lead” or “lag” phase relationship and the time
difference between the leading edges of the waveforms.
Since these edges occur only once per cycle, the detector
has a range of ±2π radians.
Operation of the device may be illustrated by assuming
two waveforms, R and V (Figure 2), of the same frequency
but differing in phase. If the logic had established by past
history that R was leading V, the U output of the detector (pin
4) would produce a positive pulse width equal to the phase
difference and the D output (pin 11 ) would simply remain low.
On the other hand, it is also possible that V was leading R
(Figure 2), giving rise to a positive pulse on the D output and
a constant low level on the U output pin. Both outputs for the
sample condition are valid since the determination of lead or
lag is dependent on past edge crossing and initial conditions
at start–up. A stable phase–locked loop will result from either
condition.
Phase error information is contained in the output duty
cycle–that is, the ratio of the output pulse width to total
period. By integrating or low–pass filtering the outputs of the
detector and shifting the level to accommodate ECL swings,
usable analog information for the voltage controlled oscillator
can be developed. A circuit useful for this function is shown in
Figure 3.
Figure 2. Timing Diagram
Proper level shifting is accomplished by differentially
driving the operational amplifier from the normally high
outputs of the phase detector (U and D). Using this technique
the quiescent differential voltage to the operational amplifier
is zero (assuming matched “1” levels from the phase
detector). The U and D outputs are then used to pass along
phase information to the operational amplifier. Phase error
summing is accomplished through resistors R1 connected to
the inputs of the operational amplifier. Some R–C filtering
imbedded within the input network (NO TAG) may be very
beneficial since the very narrow correctional pulses of the
MC12040 would not normally be integrated by the amplifier.
Phase detector gain for this configuration is approximately
0.16 volts/radian.
System phase error stems from input offset voltage in the
operational amplifier, mismatching of nominally equal
resistors, and mismatching of phase detector “high” states
between the outputs used for threshold setting and phase
measuring. All these effects are reflected in the gain
constant. For example, a 16mV offset voltage in the amplifier
would cause an error of 0.016/ 0.16 = 0.1 radian or 5.7
degrees of error. Phase error can be trimmed to zero initially
by trimming either input offset or one of the threshold
resistors (R1 in Figure 3). Phase error over temperature
depends on how much the offending parameters drift.
Figure 3. Typical Filter and Summing Network
R2
R
3
R1
2
R1
2
R1
2
CC
R1
2
+10 to
+30V
U
–
V
510
MC12040
Lead
R Leads V
(D Output=“0”)
V Leads R
(D Output=“0”)
4
12
MC1741
To
VCO
+
D
R2
510
Lag
C
CC
C
MOTOROLA RF/IF DEVICE DATA
MC12040
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
L
N
C
–T–
SEATING
PLANE
J
K
H
G
D 14 PL
0.13 (0.005)
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
–––
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
–––
10_
0.38
1.01
M
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MOTOROLA RF/IF DEVICE DATA◊
MC12040/D
5