CY24115 MediaClock™ Mini Disc Clock Generator Features • • • • Benefits Integrated phase-locked loop (PLL) Low-jitter, high-accuracy outputs 3.3V operation 8-pin SOIC package • High-performance PLL tailored for mini disc applications • Meets critical timing requirements in complex system designs • Enables application compatibility • Industry standard package saves on board space Part Number Outputs Input Frequency Range CY24115-1 1 1 MHz–30 MHz 45.1584 MHz/90.3168 MHz (selectable) Output Frequencies CY24115-2 1 1 MHz–30 MHz 90.3168 MHz/180.6336 MHz (selectable) Logic Block Diagram XIN OSC XOUT Q Φ VCO OUTPUT DIVIDERS P CLKA PLL FS0 FREQUENCY TABLE FS1 CLKSEL VDD VSS Table 1. CLKSEL Function CY24115-1 Pin Configurations CLKSEL CLKA Unit PPM Error 0 45.1584 MHz 0 1 90.3168 MHz Table 2. CLKSEL Function, CY24115-2 CY24115 8-pin SOIC XIN 1 8 XOUT VDD CLKSEL 2 7 FS1 3 6 FS0 VSS 4 5 CLKA Cypress Semiconductor Corporation Document #: 38-07275 Rev. *C 0 CLKSEL CLKA Unit PPM Error 0 90.3168 MHz 0 1 180.6336 MHz 0 Table 3. Input Frequency Function, CY24115-1 and CY24115-2 • FS1 FS0 Xtal Input Unit 0 0 2.8224 MHz 0 1 5.6448 MHz 1 0 11.2896 MHz 1 1 22.5792 MHz 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 10, 2004 CY24115 Pin Summary Pin Name Pin Number Pin Description XIN 1 Reference input (crystal or external input) VDD 2 3.3V voltage supply CLKSEL 3 CLKA Select Line For 24115-1, see Table 1 for output values For 24115-2, see Table 2 for output values VSS 4 Ground CLKA 5 24115-1: 45.1584 MHz/90.3168 MHz (frequency selectable). See Table 1. 24115-2: 90.3168 MHz/180.6336 MHz (frequency selectable). See Table 2. FS0 6 Input Frequency FS0. See Table 3. FS1 7 Input Frequency FS1. See Table 3. XOUT[1] 8 Reference Output Absolute Maximum Conditions Parameter VDD Description Min. Max. Unit Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C TJ Junction Temperature 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs Referred to VDD VSS – 0.3 VDD + 0.3 Electrostatic Discharge V 2 kV Recommended Operating Conditions Parameter VDD TA CLOAD fREF Description Operating Voltage Ambient Temperature Min. Typ. Max. 3.14 3.3 3.47 V 0 70 °C 15 pF 2.8224 22.5792 MHz Max. Load Capacitance Reference Frequency t1 Driven Reference Edge Rate 0.8 DCIN Driven Reference Duty Cycle 40 CIN XIN, XOUT capacitance tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Unit V/ns 60 % 12 pF 0.05 500 ms DC Electrical Characteristics Parameter Name IOH Output High Current Min. Typ. VOH = VDD – 0.5, VDD = 3.3V (source) Description 12 24 12 24 IOL Output Low Current VOL = 0.5, VDD = 3.3V (sink) CIN Input Capacitance CLKSEL, FS0, FS1, excludes XIN, XOUT VIL Input Low Voltage VIH Input High Voltage IIZ Input Leakage Current IDD Supply Current Max. mA mA 7 30 70 pF % of VDD % of VDD µA 5 Sum of Core and Output Current Unit 35 mA Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07275 Rev. *C Page 2 of 5 CY24115 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] DC Name Description Min. Typ. Max. 55 Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 t3 Rising Edge Slew Rate Output Clock Rise Time, 20%–80% of VDD 0.8 1.4 t4 Falling Edge Slew Rate Output Clock Fall Time, 80%–20% of VDD 0.8 1.4 t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time Unit % V/ns V/ns 350 ps 3 ms Notes: 3. Not 100% tested. Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS GND t1 t2 CLK t3 t4 80 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 CLK 20 Figure 2. Rise and Fall Time Definitions Ordering Information Ordering Code Package Type CY24115SC-1 8-pin SOIC Operating Range Commercial Operating Voltage 3.3V CY24115SC-1T 8-pin SOIC - Tape and Reel Commercial 3.3V CY24115SC-2 8-pin SOIC Commercial 3.3V CY24115SC-2T 8-pin SOIC - Tape and Reel Commercial 3.3V CY24115SXC-1 8-pin SOIC Commercial 3.3V CY24115SXC-1T 8-pin SOIC - Tape and Reel Commercial 3.3V CY24115SXC-2 8-pin SOIC Commercial 3.3V CY24115SXC-2T 8-pin SOIC - Tape and Reel Commercial 3.3V Lead Free Document #: 38-07275 Rev. *C Page 3 of 5 CY24115 Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07275 Rev. *C Page 4 of 5 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24115 Document Title: CY24115 MediaClock™ Mini Disc Clock Generator Document Number: 38-07275 REV. ECN NO. Issue Date Orig. of Change ** 110767 02/06/02 CKN New Data Sheet *A 113515 04/30/02 CKN Changed from Preliminary to Final P. 2 in Electrical Characteristics table added (source) to row 1 and (sink) to row 2 Description of Change *B 121884 12/14/02 RBI Power up requirements added to Operating Conditions Information *C 252154 See ECN RGL Added Lead Devices Document #: 38-07275 Rev. *C Page 5 of 5