CY24210 100-MHz Clock Generator with Spread Spectrum Features Benefits • Integrated phase-locked loop (PLL) High-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • Spread Spectrum Spread Spectrum outputs for EMI reduction • 3.3V operation Enables application compatibility Part Number Outputs Input Frequency Range CY24210 3 14.31818 MHz Output Frequencies Two copies of 100 MHz, 14.31818 MHz Logic Block Diagram REF XIN OSC Q XOUT Φ SPREAD SPECTRUM VCO CLK2 OUTPUT DIVIDERS CLK1 P PLL SSON VDD VSS Spread Spectrum Profiles Pin Configuration CY24210 8-pin SOIC XIN 1 8 XOUT VDD SSON 2 7 3 6 CLK1 CLK2 VSS 4 5 REF Cypress Semiconductor Corporation Document #: 38-07361 Rev. *A • 3901 North First Street Part Numbers Center Spread Percentage CY24210SC-3 + 1.875% CY24210SC-4 + 1.375% CY24210SC-5 + 2.375% CY24210SC-6 + 2.875% CY24210SC-7 + 3.375% • San Jose, CA 95134 • 408-943-2600 Revised December 5, 2002 CY24210 Pin Description Pin Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply SSON 3 Spread Spectrum Control for CLK1, CLK2, 0 = SS off, 1 = SS on, Internal Pull-up Resistor VSS 4 Ground REF 5 Buffered Reference Clock Output CLK2 6 100-MHz Clock Output with Spread Spectrum CLK1 7 100-MHz Clock Output with Spread Spectrum 8 Reference Crystal Output XOUT [1] Absolute Maximum Conditions Parameter Description Min. Max. Unit V Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 Junction Temperature TJ Electrostatic Discharge V 2 kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency Min. Typ. Max. 3.14 3.3 3.47 V 70 °C 0 Unit 15 pF 14.31818 MHz DC Electrical Specifications Parameter Description Min. Typ. VOH = VDD – 0.5, VDD = 3.3 V 12 24 mA Output Low Current VOL = 0.5, VDD = 3.3 V 12 24 mA Input High Current VIH = VDD 5 µA IIL Input Low Current VIL = 0V VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD CIN Input Capacitance IOH Output High Current IOL IIH IDD Supply Current RUP Pull-up Resistor on Input Pin ZOUT Output Impedance Conditions 50 0.7 80 Unit µA VDD Sum of Core and Output Current CLK1, CLK2, REF outputs Max. 100 18.4 0.3 VDD 7 pF 35 mA 150 kΩ Ω Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07361 Rev. *A Page 2 of 5 CY24210 AC Electrical Specifications Parameter[3] Description Conditions Min. Typ. Max. Unit DC Output Duty Cycle Duty Cycle is Defined in Figure 1, 50% of VDD 45 50 55 % t3 Rising Edge Slew Rate Output Clock Rise Time, 20%–80% of VDD 0.8 1.4 2 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80%–20% of VDD 0.8 1.4 2 V/ns t5 Output to Output Skew CLK1 + CLK2 Equally Loaded 200 ps t9 Clock Jitter Peak to Peak Period Jitter with Spread Off 300 ps t10 PLL Lock Time 3 ms Note: 3. Not 100% tested. Test and Measurement Setup VDD CLK 0.1 µF CLOAD OUTPUTS GND Voltage and Timing Definitions t1 t2 50% 50% CLK Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions Document #: 38-07361 Rev. *A Page 3 of 5 CY24210 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24210SC-3 S8 8-pin SOIC Commercial 3.3V CY24210SC-3T S8 8-pin SOIC - Tape and Reel Commercial 3.3V CY24210SC-4 S8 8-pin SOIC Commercial 3.3V CY24210SC-4T S8 8-pin SOIC - Tape and Reel Commercial 3.3V CY24210SC-5 S8 8-pin SOIC Commercial 3.3V CY24210SC-5T S8 8-pin SOIC - Tape and Reel Commercial 3.3V CY24210SC-6 S8 8-pin SOIC Commercial 3.3V CY24210SC-6T S8 8-pin SOIC - Tape and Reel Commercial 3.3V CY24210SC-7 S8 8-pin SOIC Commercial 3.3V CY24210SC-7T S8 8-pin SOIC - Tape and Reel Commercial 3.3V Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 51-85066-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07361 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY24210 Document History Page Document Title: CY24210 100-MHz Clock Generator with Spread Spectrum Document Number: 38-07361 ECN NO. Issue Date Orig. of Change ** 112458 04/04/02 CKN New Data Sheet *A 120234 12/05/02 CKN Pg. 2 added ZOUT row to the DC Electrical Specif. table. Pg. 3 added “SC” and Tape and Reel to all the dash numbers in the Ordering Information table. REV. Document #: 38-07361 Rev. *A Description of Change Page 5 of 5