CY241V08A-01,04 CY241V8A-01 MPEG Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) • Digital VCXO control • Low-jitter, high-accuracy outputs • Second source for existing designs • VCXO with analog adjust • Highest-performance PLL tailored for multimedia applications • 3.3V operation • Compatible with MK3727 (–1, –4) • Application compatibility for a wide variety of designs • Enables design compatibility • Meets critical timing requirements in complex system designs • • Lower drive strength settings (CY241V08A–04) CY241V08A-01,-04 Logic Block Diagram 13.5 XIN OSC Q XOUT OUTPUT DIVIDERS Φ VCO 27 MHz P VCXO PLL VDD VSS Pin Configurations CY241V08A-01,-04 8-pin SOIC Part Number Outputs XIN 1 VDD VCXO VSS 2 3 4 8 7 6 5 XOUT NC or VSS NC or VDD 27 MHz Input Frequency Range Output Frequencies VCXO Control Curve Other Features CY241V08A-01 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz linear Cypress specification Compatible with MK3727 CY241V08A-04 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz linear Cypress specification Same as CY241V08A-01 except lower drive strength settings Cypress Semiconductor Corporation Document #: 38-07656 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 14, 2005 CY241V08A-01,04 CY241V8A-01 Pin Description Name Pin Number Description XIN 1 Reference crystal input VDD 2 Voltage supply VCXO 3 Input analog control for VCXO VSS 4 Ground 27 MHz 5 27-MHz clock output NC/VDD 6 No connect or voltage supply NC/VSS 7 No connect or ground XOUT 8 Reference crystal output Document #: 38-07656 Rev. *C Page 2 of 6 CY241V08A-01,04 CY241V8A-01 Absolute Maximum Conditions Storage Temperature (Non-condensing) .... –55°C to +125°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C................................> 10 years Supply Voltage (VDD) ........................................–0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage...................................... –0.5V to VDD + 0.5 ESD (Human Body Model) MIL-STD-883................. > 2000V Pullable Crystal Specifications[1] Parameter Description Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut – 13.5 – MHz FNOM Nominal crystal frequency CLNOM Nominal load capacitance – 14 – pF R1 Equivalent series resistance (ESR) Fundamental mode – – 25 Ω R3/R1 Ratio of third overtone mode ESR Ratio used because typical R1 values to fundamental mode ESR are much less than the maximum spec 3 – – – DL Crystal drive level No external series resistor assumed 150 – – µW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 – C1 Crystal motional capacitance 14.4 18 21.6 fF Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 – 70 °C Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) – – 15 pF 0.05 – 500 ms DC Electrical Specifications Min. Typ. Max. Unit IOH Parameter Output HIGH Current Name VOH = VDD – 0.5V, VDD = 3.3V Description 12 24 – mA IOL Output LOW Current VOL = 0.5V, VDD = 3.3V 12 24 – mA CIN Input Capacitance Except XIN, XOUT pins – – 7 pF VVCXO VCXO Input Range f∆XO[2] VCXO Pullability Range IVDD Supply Current 0 – VDD V Low Side – – –115 ppm High Side 115 – – ppm – 30 35 mA Notes: 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. 2. –115/+115 ppm assumes 2.5pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. Document #: 38-07656 Rev. *C Page 3 of 6 CY241V08A-01,04 CY241V8A-01 AC Electrical Specifications (VDD = 3.3V) [3] Parameter[3] Name Description Min. Typ. Max. Unit DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 55 % EROR Rising Edge Rate –01 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 – V/ns EROF Falling Edge Rate –01 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 – V/ns EROR Rising Edge Rate –04 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.7 1.1 – V/ns EROF Falling Edge Rate –04 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.7 1.1 – V/ns t9 Clock Jitter Peak-to-peak period jitter – – 100 ps t10 PLL Lock Time – – 3 ms Test and Measurement Set-up VDD 0.1 µF Outputs C LOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD)/t3, EF = (0.6 x VDD)/t4 Note: 3. Not 100% tested. Document #: 38-07656 Rev. *C Page 4 of 6 CY241V08A-01,04 CY241V8A-01 Ordering Information Ordering Code Operating Range Package Type Operating Voltage Features CY241V08ASC–01 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V08ASC–01T 8-pin SOIC – Tape and Reel Commercial 3.3V Linear VCXO control curve CY241V08ASC–04 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V08ASC–04T 8-pin SOIC – Tape and Reel Commercial 3.3V Linear VCXO control curve CY241V8ASXC-01 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V8ASXC-01T 8-pin SOIC - Tape and Reel Commercial 3.3V Linear VCXO control curve Lead-free Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07656 Rev. *C Page 5 of 6 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY241V08A-01,04 CY241V8A-01 Document History Page Document Title: CY241V08A-01,04/ CY241V8A-01MPEG Clock Generator with VCXO Document Number: 38-07656 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 214069 See ECN RGL New Data Sheet *A 220404 See ECN RGL Minor Change: To post on web *B 393122 See ECN RGL Added Lead-free device for -01 Added the CY241V8A-01 in the title *C 414184 See ECN RGL Minor Change: Deleted unneccesary text in the benefit section Document #: 38-07656 Rev. *C Page 6 of 6