STK14CA8 128Kx8 Autostore nvSRAM FEATURES DESCRIPTION • 25, 35, 45 ns Read Access & R/W Cycle Time The Simtek STK14CA8 is a 1Mb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. • Unlimited Read/Write Endurance • Automatic Non-volatile STORE on Power Loss • Non-Volatile STORE Under Hardware or Software Control • Automatic RECALL to SRAM on Power Up The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. • Unlimited RECALL Cycles • 200K STORE Cycles • 20-Year Non-volatile Data Retention • Single 3.0V + 20%, -10% Operation • Commercial and Industrial Temperatures • Small Footprint SOIC & SSOP Packages (RoHSCompliant) The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available. BLOCK DIAGRAM VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ROW DECODER POWER CONTROL STORE STATIC RAM ARRAY 1024 X 1024 RECALL STORE/ RECALL CONTROL HSB SOFTWARE DETECT INPUT BUFFERS A5 A6 A7 A8 A9 A12 A13 A14 A15 A16 VCAP Quantum Trap 1024 X 1024 A15 – A0 COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 A11 G E W This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. 1 Document Control #ML0022 Rev 2.1 Jan, 2008 STK14CA8 PACKAGES VCAP 1 48 VCC VCAP 1 32 VCC A16 A14 2 47 A15 A16 2 31 A15 3 46 HSB 30 4 A6 A5 43 A7 5 29 28 6 W A13 A8 4 5 45 44 A14 A12 3 A12 A7 7 42 27 41 7 26 9 40 A11 A6 A5 A4 6 8 A9 NC HSB W A13 A8 8 25 10 39 A3 A2 9 24 10 23 NC A4 NC NC A9 A11 G A10 NC 11 38 NC NC VSS 12 37 NC A1 11 22 13 36 VSS A0 12 21 NC NC 14 35 NC DQ0 13 20 15 34 19 16 33 15 18 DQ4 A3 A2 17 32 G DQ1 DQ2 VSS 14 DQ0 NC DQ6 DQ6 DQ5 16 17 DQ3 18 31 A10 A1 19 30 A0 DQ1 DQ2 20 29 E DQ7 21 28 DQ5 22 23 27 DQ4 NC 26 NC 24 25 DQ3 VCC E DQ7 SOIC SSOP 32-Pin SOIC 48-Pin SSOP Relative PCB area usage. See page 17 for detailed package size specifications. PIN DESCRIPTIONS Pin Name I/O Description A16-A0 Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. VCC Power Supply Power: 3.0V, +20%, -10% HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). VCAP Power Supply Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. VSS Power Supply Ground NC No Connect Unlabeled pins have no internal connections. Document Control #ML0022 Rev 2.1 Jan, 2008 2 STK14CA8 ABSOLUTE MAXIMUM RATINGS Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V Voltage on Input Relative to VSS . . . . . . . . . .–0.5V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .–55°C to 140°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS θjc 5.4 C/W; θja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm]. RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS θjc 6.2 C/W; θja 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm]. DC CHARACTERISTICS (VCC = 2.7V-3.6V) COMMERCIAL SYMBOL UNITS MIN ICC1 ICC2 ICC3 ICC4 ISB INDUSTRIAL PARAMETER MAX MIN NOTES MAX Average VCC Current tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns Dependent on output loading and cycle rate. Values obtained without output loads. 65 55 50 70 60 55 mA mA mA 3 3 mA All Inputs Don’t Care, VCC = max Average current for duration of STORE cycle (tSTORE) Average VCC Current during STORE 10 10 mA W ≥ (V CC – 0.2V) All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate. Values obtained without output loads. Average VCAP Current during AutoStore Cycle 3 3 mA All Inputs Don’t Care Average current for duration of STORE cycle (tSTORE) VCC Standby Current (Standby, Stable CMOS Levels) 3 3 mA Average VCC Current at tAVAV = 200ns 3V, 25°C, Typical E ≥ (VCC -0.2V) All Others VIN≤ 0.2V or ≥ (VCC-0.2V) Standby current level after nonvolatile cycle complete IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V All Inputs VIL Input Logic “0” Voltage VSS –0.5 0.8 VSS –0.5 0.8 V All Inputs VOH Output Logic “1” Voltage VOL Output Logic “0” Voltage TA Operating Temperature 0 70 VCC Operating Voltage 2.7 3.6 VCAP Storage Capacitance 17 120 NVC Nonvolatile STORE operations 200 200 K DATAR Data Retention 20 20 Years 2.4 2.4 V IOUT = – 2mA 0.4 V IOUT = 4mA –40 85 °C 2.7 3.6 V 3.3V + 0.3V 17 120 μF Between VCAP pin and VSS, 5V rated. 0.4 Note: The HSB pin has IOUT=-10 uA for VOH of 2.4 V, this parameter is characterized but not tested. Document Control #ML0022 Rev 2.1 Jan, 2008 3 @ 55 deg C STK14CA8 AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 and 2 CAPACITANCEb SYMBOL (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 7 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V Note b: These parameters are guaranteed but not tested. 3.0V 577 Ohms OUTPUT 789 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading 3.0V 577 Ohms OUTPUT 789 Ohms 5 pF INCLUDING SCOPE AND FIXTURE Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ) Document Control #ML0022 Rev 2.1 Jan, 2008 4 STK14CA8 SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK14CA8-25 STK14CA8-35 STK14CA8-45 MIN MIN MIN PARAMETER #1 #2 1 Alt. tELQV UNITS MAX MAX tACS Chip Enable Access Time 2 tAVAVc tELEH c tRC Read Cycle Time 3 tAVQVd tAVQVd tAA Address Access Time 25 35 45 ns tGLQV tOE Output Enable to Data Valid 12 15 20 ns 4 tAXQXd 5 tAXQX d 25 35 MAX 25 45 35 45 ns ns tOH Output Hold after Address Change 3 3 3 ns 6 tELQX tLZ Address Change or Chip Enable to Output Active 3 3 3 ns 7 tEHQZe tHZ Address Change or Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active e 9 tGHQZ tOHZ Output Disable to Output Inactive 10 tELICCHb tPA Chip Enable to Power Active 11 b tPS Chip Disable to Power Standby tEHICCL Note c: Note d: Note e: Note f: 10 13 0 15 0 0 10 13 0 0 25 35 SRAM READ CYCLE #1: Address Controlledc,d,f 2 tAVAV ADDRESS 3 tAVQV tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E and G Controlledc,f ADDR ESS 2 E t E LE H 1 tEL Q V 6 29 t EHAX 11 t EHI CC L t ELQ X 27 7 t EHQ Z 3 t AV QV G 8 tG L Q X 9 t GH Q Z 4 t G L QV DQ (D ATA OUT) DAT A VAL ID 10 t ELI CC H AC T IVE I CC ST AND BY Document Control #ML0022 Rev 2.1 Jan, 2008 5 ns ns 45 W must be high during SRAM READ cycles. Device is continuously selected with E and G both low Measured ± 200mV from steady state output voltage. HSB must remain high during READ and WRITE cycles. 5 ns 15 0 ns ns STK14CA8 SRAM WRITE CYCLES #1 & #2 SYMBOLS NO. STK14CA8-25 STK14CA8-35 STK14CA8-45 MIN MIN MIN PARAMETER UNITS #1 #2 Alt. MAX MAX MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns 20 t WLQZ e, g tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write 10 3 13 3 3 Note g: If W is low when E goes low, the outputs remain in the high-impedance state. Note h: E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledg,h 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN 16 tWHDX DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledg,h 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH 13 tWLEH W 15 tDVEH DATA IN DATA OUT Document Control #ML0022 Rev 2.1 Jan, 2008 16 tEHDX DATA VALID HIGH IMPEDANCE 6 15 ns ns STK14CA8 AutoStore/POWER-UP RECALL SYMBOLS STK14CA8 NO. PARAMETER Standard Alternate MIN UNITS NOTES 20 ms i j,k MAX 22 tHRECALL Power-up RECALL Duration 23 tSTORE STORE Cycle Duration 12.5 ms 24 VSWITCH Low Voltage Trigger Level 2.65 V 25 VCCRISE VCC Rise Time tHLHZ μs 150 Note i: tHRECALL starts from the time VCC rises above VSWITCH Note j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place Note k: Industrial Grade Devices require 15 ms MAX. AutoStore/POWER-UP RECALL STORE occurs only if a SRAM write has happened. No STORE occurs without at least one SRAM write. VCC 24 VSWITCH 25 tVCCRISE AutoStoreTM 23 tSTORE 23 tSTORE POWER-UP RECALL 22 tHRECALL 22 tHRECALL Read & Write Inhibited POWER-UP RECALL BROWN OUT TM AutoStore POWER-UP RECALL POWER DOWN TM AutoStore Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH Document Control #ML0022 Rev 2.1 Jan, 2008 7 STK14CA8 SOFTWARE-CONTROLLED STORE/RECALL CYCLEl,m Symbols STK14CA8-35 NO. STK14CA8-35 STK14CA8-45 PARAMETER UNITS NOTES E Cont G Cont Alternate MIN MAX MIN 26 tAVAV tAVAV tRC STORE/RECALL Initiation Cycle Time 25 35 45 ns 27 tAVEL tAVGL tAS Address Set-up Time 0 0 0 ns 28 tELEH tGLGH tCW Clock Pulse Width 20 25 30 ns 29 tEHAX tGHAX Address Hold Time 1 1 1 ns 30 tRECALL tRECALL RECALL Duration 50 MAX MIN MAX 50 50 m μs Note l: The software sequence is clocked on the falling edge of E controlled READs or G controlled READs Note m: The six consecutive addresses must be read in the order listed in the in the Software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDm ADDRESS E 26 tAVAV 26 tAVAV ADDRESS #1 ADDRESS #6 27 tAVEL 28 tELEH 29 tEHAX G 23 tSTORE /t 30 RECALL HIGH IMPEDENCE DQ (DATA) DATA VALID DATA VALID SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDm ADDRESS 26 tAVAV 26 tAVAV ADDRESS #1 ADDRESS #6 E 27 tAVGL 28 tGLGH G 23 tSTORE 29 / 30 tRECALL tGHAX DQ (DATA) DATA VALID Document Control #ML0022 Rev 2.1 Jan, 2008 DATA VALID 8 HIGH IMPEDENCE STK14CA8 HARDWARE STORE CYCLE SYMBOLS STK14CA8 PARAMETER Standard Alternate 31 1 tDELAY tHLQZ 32 2 tHLHX MIN MAX Hardware STORE to SRAM Disabled 1 70 Hardware STORE Pulse Width 15 UNITS NOTES μs n ns Note n: On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read/write cycles to complete HARDWARE STORE CYCLE 32 tHLHX HSB (IN) 23 tSTORE HSB (OUT) 31 tDELAY DQ (DATA OUT) SRAM Enabled SRAM Enabled Soft Sequence Commands NO. SYMBOLS STK14 CA8 PARAMETER Standard 341 tSS MIN NOTES μs o,p MAX 70 Soft Sequence Processing Time UNITS Notes: o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command. p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command. 34 tSS 34 tSS Soft Sequence Command ADDRESS ADDRESS #1 Soft Sequence Command ADDRESS #1 ADDRESS #6 Vcc Document Control #ML0022 Rev 2.1 Jan, 2008 9 ADDRESS #6 STK14CA8 MODE SELECTION E W G A16-A0 Mode I/O Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output Data Output Data Output Data Output Data Output Data Output Data Active L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output Data Output Data Output Data Output Data Output Data Output Data Active L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Output Data Output Data Output Data Active 0x08FC0 Nonvolatile Store Output High Z ICC2 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z Active L L L L H H H H L Notes q,r,s q,r,s q,r,s q,r,s Notes q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. r: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes s: I/O state depends on the state of G. The I/O table shown assumes G low Document Control #ML0022 Rev 2.1 Jan, 2008 10 STK14CA8 nvSRAM OPERATION nvSRAM AutoStore OPERATION The STK14CA8 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The STK14CA8 supports unlimited read and writes like a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations. The STK14CA8 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store (activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down). SRAM READ The STK14CA8 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins A0-16 determine which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W and HSB is brought low. AutoStore operation is a unique feature of Simtek Quantum Trap technology is enabled by default on the STK14CA8. During normal operation, the device will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the DC CHARACTERISTICS table for the size of the capacitor. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up. To reduce unneeded nonvolatile stores, AutoStore and Hardware Store operations will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation SRAM WRITE It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. Document Control #ML0022 Rev 2.1 Jan, 2008 11 VCC W Figure 3. AutoStore Mode 0.1µF VCAP VCAP A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. 10k Ohm VCC STK14CA8 has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress. HARDWARE STORE (HSB) OPERATION The STK14CA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14CA8 will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14CA8 will continue to allow SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low, it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. If HSB is not used, it should be left unconnected. To initiate the software STORE cycle, the following READ sequence must be performed: 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ Valid READ 5 Read Address 0x703F 6 Read Address 0x8FC0 Initiate STORE Cycle Valid READ Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence and that G is active. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE RECALL Data can be transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 HARDWARE RECALL (POWER-UP) 4 Read Address 0x7C1F Valid READ During power up or after any low-power condition (VCC<VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete. 5 Read Address 0x703F Valid READ 6 Read Address 0x4C63 Initiate RECALL Cycle SOFTWARE STORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initiated by executing sequential E controlled or G controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed. Document Control #ML0022 Rev 2.1 Jan, 2008 12 Valid READ Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM will once again be ready for READ or WRITE operations. The RECALL operation in no way alters the data in the nonvolatile storage elements. STK14CA8 DATA PROTECTION The STK14CA8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The lowvoltage condition is detected when VCC<VSWITCH. If the STK14CA8 is in a WRITE mode (both E and W low) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions. NOISE CONSIDERATIONS The STK14CA8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 µF connected between VCC and VSS, using leads and traces that are a short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise. • If autostore has been firmware disabled, it will not reset to “autostore enabled” on every power down event captured by the nvSRAM. The application firmware should re-enable or re-disable autostore on each reset sequence based on the behavior desired. • The Vcap value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Simtek to understand any impact on the Vcap voltage level at the end of a tRECALL period. LOW AVERAGE ACTIVE POWER BEST PRACTICES nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: • The non-volatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. • Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard Document Control #ML0022 Rev 2.1 Jan, 2008 against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). 13 CMOS technology provides the STK14CA8 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns. Figure 4 shows the relationship between ICC and READ/ WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, VCC=3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14CA8 depends on the following items: 1 The duty cycle of chip enable 2 The overall cycle rate for operations 3 The ratio of READs to WRITEs 4 The operating temperature 5 The VCC Level 6 I/O Loading STK14CA8 PREVENTING AUTOSTORE The AutoStore function can be disabled by initiating an AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed: 1 Read Address 0x4E38 2 Read Address 0xB1C7 Valid READ Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x8B45 AutoStore Disable Valid READ The AutoStore can be re-enabled by initiating an AutoStore Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed: Figure 4 - Current vs Cycle Time 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 4 Read Address 0x7C1F Valid READ Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Document Control #ML0022 Rev 2.1 Jan, 2008 14 STK14CA8 ORDERING INFORMATION STK14CA8-R F 45 I TR Packing Option Blank=Tube TR=Tape and Reel Temperature Range Blank=Commercial (0 to +70 C) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Finish F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mil SOIC (50 mil pitch) R=Plastic 48-pin 300 mil SSOP (25 mil pitch) Document Control #ML0022 Rev 2.1 Jan, 2008 15 STK14CA8 ORDERING CODES Part Number STK14CA8-NF25 STK14CA8-NF35 STK14CA8-NF45 STK14CA8-NF25TR STK14CA8-NF35TR STK14CA8-NF45TR STK14CA8-RF25 Description 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SSOP48-300 STK14CA8-RF35 STK14CA8-RF45 STK14CA8-RF25TR STK14CA8-RF35TR STK14CA8-RF45TR STK14CA8-NF25I STK14CA8-NF35I STK14CA8-NF45I STK14CA8-NF25ITR STK14CA8-NF35ITR STK14CA8-NF45ITR STK14CA8-RF25I STK14CA8-RF35I STK14CA8-RF45I STK14CA8-RF25ITR STK14CA8-RF35ITR STK14CA8-RF45ITR 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM 3V 128Kx8 AutoStore nvSRAM SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SOP32-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 SSOP48-300 Document Control #ML0022 Rev 2.1 Jan, 2008 16 Access Times 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time 25 ns access time 35 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial STK14CA8 PACKAGE DRAWINGS 32 Pin 300 mil SOIC 0.292 7.42 0.300 7.60 ( ) 0.405 10.29 0.419 10.64 ( ) Pin 1 Index 0.810 20.57 0.822 20.88 ( 0.026 0.66 0.032 0.81 ( .050 (1.27) BSC ) ) 0.090 2.29 0.100 2.54 ( ) 0.086 0.090 0.12 0.22 ( ) 0.004 0.10 0.010 0.25 ( ) 0.014 0.36 0.020 0.51 DIM = INCHES DIM = mm 0.006 0.013 0 0.15 ( 0.32 ) 8 0.021 0.041 Document Control #ML0022 Rev 2.1 Jan, 2008 2.18 ) ( 2.29 17 0.53 ( 1.04 ) o o MIN MAX MIN ( MAX ) STK14CA8 48 Pin 300 mil SSOP TOP VIEW ( 0.620 15.75 0.630 16.00 N 0.400 0.410 ) BOTTOM VIEW ) ( 10.16 10.41 .045 .055 0.292 0.299 7.42 ) ( 7.59 0.292 0.299 7.42 ) ( 7.59 (11.43 13.97) 1 2 3 Pin 1 indicator .045 DIA. .035 .045 (11.43) .020 (5.1) 8.89 ) (11.43 SIDE VIEW 0.008 0.0135 0.025 (0.635) ( 0.203 0.343) ( ) ( 2.41 2.79) DIM = INCHES DIM = mm ( 0.088 0.092 ( 2.24 2.34 ) SEATING PLANE 0.008 0.016 SEE DETAIL A ( 0.20 0.41) MIN END VIEW PARTING LINE MAX MIN MAX ( 0.25 0.41 ) 45° 0.095 0.110 0.620 15.75 0.630 16.00 0.010 0.016 END VIEW ) 0.010 (0.25) GAUGE PLANE SEATING PLANE DETAIL A 0.024 0.040 Document Control #ML0022 Rev 2.1 Jan, 2008 18 ( 0.61 1.02 ) STK14CA8 Document Revision History Rev Date Change 0.0 January 2003 Publish New Datasheet 0.1 May 2003 Add 48-pin SSOP, Modify AutoStore Diagram, Update Mode Selection Table and Absolute Maximum Ratings, Added G controlled software store. 0.2 September 2003 Added lead-free finish 1.0 December 2004 1.1 Parameter VCAP Min Old Value New Value Notes 10uF 17uF tVCCRISE NA 150 us New Spec ICC1 Max Com. 35 mA 50 mA @45 ns access ICC1 Max Com. 40 mA 55 mA @35 ns access ICC1 Max Com. 50 mA 65 mA @25 ns access ICC1 Max Ind. 35 mA 55 mA @45 ns access ICC1 Max Ind. 45 mA 60 mA @35 ns access ICC1 Max Ind. 55 mA 70 mA @25 ns access ICC2 Max 1.5 mA 3.0 mA Com. & Ind. ICC4 Max 0.5 mA 3.0 mA Com. & Ind. tHRECALL 5 ms 20 ms tSTORE 10 ms 12.5 ms tRECALL tGLQV 20 us 40 us 10 ns 12 ns 25 ns device August 2005 Parameter ICC3 Max Com. Old Value New Value 5 mA 10 mA ICC3 Max Ind. 5 mA 10 mA ISB Max Com. 2 mA 3 mA ISB Max Ind. 2 mA 3 mA tRECALL 40 us 50 us tSTORE 12.5 ms 15 ms NVc 1x10 Document Control #ML0022 Rev 2.1 Jan, 2008 19 6 5 5x10 Notes Soft Recall Industrial Grade Only Contact Simtek For Details STK14CA8 Rev Date Change 1.2 September 2005 Added an Extended Temperature Range device tested from -55 degree C to +85 degree C 1.3 December 2005 Parameter 1.4 March 2006 1.5 February 2007 Old Value New Value tRECALL tSS 60 us Undefined 50 us 70 us DATAR 100 Years at Unspecified Temperature 20 Years @ Max Temperature Notes Typographical Error In Datasheet New Data Retention Specification Removed Lead Plated Lead Finish Parameter Old Value 500K 20 Years @ 85 C 2.55 V NVC DATAR VSWITCH Min. New Value Notes New Nonvolatile 200K Store Cycle Spec 20 Years @ New Data Retention 55 C Spec No Min. Spec -10 uA IOUT (HSB) tELAX, tGLAX tEHAX, tGHAX tDELAY Max. tHLBL tSS 20 ns 300ns 70 uS Min. 57 uF VCAP Max Not Specified Before Removed 1 ns New Spec 70 us New Spec Spec Not Required 70 uS Max. Typo 120 uF Deleted -G Extended Temperature Option Added tape and reel ordering option Added product order code listing Added package drawings Reformatted Entire Document Document Control #ML0022 Rev 2.1 Jan, 2008 20 Supports Upgrades From 14C88-3 STK14CA8 Rev Date Change 2.0 January 2008 page 3: added thermal characteristics. page 5: in the SRAM Read Cycles #1 and #2 table, revised parameter description for tELQX and tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram and changed title to add G controlled. page 8: revised the notes below the Software-Controlled Store/Recall Cycle diagram. page 10: in the Mode Selection table, changed column to A16-A0. In the values in this column, added a zero after each instance of “0x.” On fifth row, changed AutoStore Enable value to 0x04B46. page 11: under AutoStore Operation, revised text to read: “Refer to the DC CHARACTERISTICS table for the size of the capacitor.” page 12: under Hardware Store (HSB) Operation, revised first paragraph to read “The HSB pin has a very resistive pullup...” page 13: added best practices section. page 16: added access times column to the Ordering Codes. 2.1 January 2008 Corrected pin assignments in package drawings on page 2. SIMTEK STK14CA8 Datasheet, January 2008 Copyright 2008, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right. Document Control #ML0022 Rev 2.1 Jan, 2008 21