STK12C68-IM STK12C68-IM CMOS nvSRAM 8K x 8 AutoStore™ Nonvolatile Static RAM Industrial Temperature/Military Screen FEATURES DESCRIPTION • Industrial Temperature with Military Screening • 25, 35 and 45ns Access Times The Simtek STK12C68-IM is a fast static RAM (25, 35 and 45ns), with a nonvolatile EEPROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 µF capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. Software sequences may also be used to initiate both STORE and RECALL operations. A STORE can also be initiated via a single pin. • 15 mA ICC at 200ns Access Speed • Automatic STORE to EEPROM on Power Down • Hardware or Software initiated STORE to EEPROM • Automatic STORE Timing • 100,000 STORE cycles to EEPROM • 10 year data retention in EEPROM • Automatic RECALL on Power Up • Software initiated RECALL from EEPROM • Unlimited RECALL cycles from EEPROM • Single 5V±10% Operation The STK12C68-IM is available in the following packages: a 28-pin 300 mil ceramic DIP and a 28-pad LCC. MIL-STD-883 and Standard Military Drawing (SMD 5962-94599) devices are also available. • Commercial and Industrial Temperatures • Available in multiple standard packages 3 A6 A5 A3 STORE A9 A 12 A12 A9 23 A11 A2 8 22 G A1 9 21 A 10 A0 10 20 E DQ 0 DQ 1 11 19 12 18 DQ 7 DQ 6 TOP VIEW HSB DQ 3 DQ 4 DQ 5 COLUMN DECODER A0 A1 A2 A10 3 26 W HSB A6 4 25 A8 A5 A4 A3 5 24 6 23 7 22 A9 A 11 G A2 A1 A0 8 21 A 10 9 20 10 19 E DQ 7 DQ 0 DQ 1 DQ 2 11 18 DQ 6 12 17 13 16 DQ 5 DQ 4 VSS 14 15 DQ 3 28 - 300 CDIP PIN NAMES COLUMN I/O INPUT BUFFERS DQ 2 VCCX 27 28 - LCC DQ 0 DQ 1 28 2 W 24 7 13 14 15 16 17 STORE/ RECALL CONTROL 1 A 12 A7 DQ5 A0 6 A3 DQ4 A8 ARRAY 256 x 256 VCAP HSB A8 A4 DQ3 A7 28 27 26 25 Vss A6 RECALL STATIC RAM 1 5 DQ2 A5 ROW DECODER A4 2 4 VCCX A7 A 12 EEPROM ARRAY 256 x 256 VCAP PIN CONFIGURATIONS LOGIC BLOCK DIAGRAM A 11 G DQ 6 DQ 7 E W 41 A0 - A12 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCCX Power (+5V) VSS Ground VCAP Capacitor HSB Hardware Store/Busy STK12C68-IM ABSOLUTE MAXIMUM RATINGSa Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (One output at a time, one second duration) (VCC = 5.0V ± 10%)d DC CHARACTERISTICS INDUSTRIAL SYMBOL PARAMETER ICC b Average VCC Current 1 ICC MIN 2 ICC b 3 MAX UNITS 95 mA tAVAV = 25ns 85 mA tAVAV = 35ns 80 mA tAVAV = 45ns Average VCC Current During STORE 7 mA All inputs ≤ 0.2V or ≥ (VCC - 0.2V) Average VCC Current 15 mA E ≤ 0.2V, W ≥ (VCC – 0.2V) Average VCC current during AutoStore™ Cycle 4 mA All inputs ≤ 0.2V or ≥ (VCC - 0.2V) Average VCC Current 39 mA tAVAV = 25ns (Standby, Cycling TTL Input Levels) 35 mA tAVAV = 35ns 32 mA tAVAV = 45ns 3 mA E ≥ (VCC – 0.2V) VCC = max others ≤ 0.2V or ≥ (VCC – 0.2V) at tAVAV = 200ns ICC 4 ISB c 1 NOTES E ≥ VIH; all others cycling ISB c Average VCC Current 2 all others VIN ≤ 0.2V or ≥ (VCC – 0.2V) (Standby, Stable CMOS Input Levels) IILK Input Leakage Current (Any Input) ±1 µA IOLK Off State Output Leakage Current ±5 µA 3 VIN = VSS to VCC VCC = max VOUT = VSS to VCC VIH Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs VIL Input Logic "0" Voltage VSS–.5 0.8 V All Inputs VOH Output Logic "1" Voltage VOL Output Logic "0" Voltage TA Operating Temperature 2.4 -40 V IOUT = –4mA except HSB 0.4 V IOUT = 8mA except HSB 85 °C Note b: ICC and ICC 3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground. AC TEST CONDITIONS 5.0V Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL 480 Ohms Output 255 Ohms (TA=25°C, f=1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 8 pF ∆V = 0 to 3V COUT Output Capacitance 7 pF ∆V = 0 to 3V 30pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading Note e: These parameters are guaranteed but not tested. 42 STK12C68-IM SRAM MEMORY OPERATION (VCC = 5.0V ± 10%)d READ CYCLES #1 & #2 SYMBOLS NO. STK12C68-25-IM PARAMETER MAX 1 tELQV tACS Chip Enable Access Time 2 tAVAV tRC Read Cycle Time 3 tAVQVg tAA Address Access Time 25 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 10 20 25 ns 5 tAXQX tOH Output Hold After Address Change 5 5 5 ns 6 tELQX tLZ Chip Enable to Output Active 5 5 5 ns tHZ Chip Disable to Output Inactive 25 25 tEHQZ 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive 10 tELICCHe tPA Chip Enable to Power Active 11 tEHICCLc,e tPS Chip Disable to Power Standby MAX 10 45 45 10 20 0 25 20 0 35 45 READ CYCLE #1 f,g 2 tAVAV ADDRESS 3 tAVQV DQ (Data Out) DATA VALID READ CYCLE #2 f 2 tAVAV ADDRESS 6 E 1 tELQV 7 tEHQZ 4 tGLQV G 8 tGLQX 9 tGHQZ DQ (Data Out) DATA VALID 10 tELICCH ICC 11 tEHICCL tELQX ACTIVE STANDBY 43 ns ns Note c: Bringing E ≥ VIH will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note e: Parameter guaranteed but not tested. Note f: For READ CYCLE #1 and #2, W is high for entire cycle. Note g: Device is continuously selected with E low and G low. Note h: Measured ± 200mV from steady state output voltage. 5 tAXQX ns ns 17 0 ns ns 17 0 0 MAX 35 35 0 MIN UNITS Alt. 7 MIN STK12C68-45-IM #1, #2 h MIN STK12C68-35-IM ns STK12C68-IM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)d SYMBOLS STK12C68-25-IM NO. STK12C68-35-IM STK12C68-45-IM PARAMETER UNITS #1 #2 Alt. MIN MAX MIN 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 30 35 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 30 35 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 18 20 ns 16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 30 35 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns 20 tWLQZh,j tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active After End of Write 10 5 MAX MIN 17 20 5 5 Note h: Measured ±200mV from steady state output voltage. Note i: E or W must be ≥VIH during address transitions. Note j: If W is low when E goes low, the outputs remain in the high impedance state. WRITE CYCLE #1: W CONTROLLED i 12 tAVAV ADDRESS 14 tELWH 19 tWHAX E 17 tAVWH 18 13 tWLWH tAVWL W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA WRITE CYCLE #2: E CONTROLLED i 12 tAVAV ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT 16 tEHDX DATA VALID HIGH IMPEDANCE 44 MAX ns ns STK12C68-IM NONVOLATILE MEMORY OPERATION MODE SELECTION E W HSB A12 - A0(hex) MODE I/O POWER H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active L H H Active L H X H X NOTES l 0000 Read SRAM Output Data 1555 Read SRAM Output Data k,l 0AAA Read SRAM Output Data k,l 1FFF Read SRAM Output Data k,l k,l k,l 10F0 Read SRAM Output Data 0F0F Nonvolatile STORE Output High Z 0000 Read SRAM Output Data k Active k,l 1555 Read SRAM Output Data 0AAA Read SRAM Output Data k,l k,l 1FFF Read SRAM Output Data k,l k,l 10F0 Read SRAM Output Data 0F0E Nonvolatile RECALL Output High Z X STORE/Inhibit Output High Z L k ICC2/Standby m Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. Note l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G. Note m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the part will go into standby mode inhibiting all operation until HSB rises. HARDWARE STORE /RECALL SYMBOLS NO. PARAMETER MIN MAX UNITS NOTES RECALL Cycle Duration 20 µs Note o 10 ms VCC ≥ 4.5V 22 tRECALL 23 tSTORE tHLHH STORE Cycle Duration 24 tDELAY tHLQZ HSB Low to Inhibit On 25 tRECOVER tHHQX HSB High to Inhibit Off 26 tASSERT tHLHX External STORE Pulse Width 250 VSWITCH Low Voltage Trigger Level 4.0 IHSB_OL HSB Output Low Current 3 IHSB_OH HSB Output High Current 5 µs 1 700 4.5 60 ns Note e ns Note e V mA HSB = VOL, Note e, n µA HSB = VIL, Note e, n Note e: These parameters guaranteed but not tested. Note n: HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-IMs to be ganged together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68 HSB pins. Note o: A RECALL cycle is initiated automatically at power up when VCC exceeds VSWITCH. tRESTORE is measured from the point at which VCC exceeds 4.5V. HARDWARE STORE /RECALL VSWITCH VCAP 26 tASSERT 24 tDELAY HSB W 22 tRECALL 24 tDELAY 25 tRECOVER RECALL STORE SRAM Inhibit Power Up RECALL Brown Out RECALL 23 tSTORE 23 tSTORE 23 tSTORE Power Down STORE HSB Initiated STORE Software STORE 45 STK12C68-IM SOFTWARE STORE/RECALL CYCLE (VCC = 5.0V ± 10%)d SYMBOLS NO. Std. STK12C68-25-IM Alt. tRC PARAMETER MIN Store/Recall Initiation Cycle Time MAX 25 STK12C68-35-IM MIN MAX STK12C68-45-IM MIN tAVAV 28 tELQZp 29 tAVELN tAE Address Set-up to Chip Enable 0 0 0 ns 30 tELEHNp,q tEP Chip Enable Pulse Width 20 25 35 ns 31 tEHAXN tEA Chip Disable to Address Change 0 0 0 ns 32 tRESTORE 650 Power-up Recall Duration 45 UNITS 27 Chip Enable to Output Inactive 35 MAX 650 550 ns 650 550 550 ns µs Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence. Note r: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-IM performs a STORE or RECALL. Note t: E must be used to clock in the address sequence for the Software STORE and RECALL cycles. SOFTWARE STORE/RECALL CYCLE q,r,t 28 tAVAV 28 tAVAV ADDRESS ADDRESS #2 ADDRESS #1 30 tAVELN 31 tELEHN ADDRESS #6 32 tEHAXN E 23 tSTORE 22 tRECALL 29 tELQZ DQ(Data Out) VALID VALID 46 HIGH IMPEDANCE STK12C68-IM DEVICE OPERATION The STK12C68-IM has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. STORE cycles may be initiated under user control via a software sequence or HSB assertion and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power-up and whenever the power supply voltage level rises above VSWITCH. RECALL cycles may also be initiated by a software sequence. address locations. By relying on READ cycles only, the STK12C68-IM implements nonvolatile operation while remaining compatible with standard 8Kx8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is critical that no other read or write accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed: SRAM READ The STK12C68-IM performs a READ cycle whenever E and G are LOW and HSB and W are HIGH. The address specified on pins A0-12 determines which of the 8192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV. If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later. The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or HSB is brought LOW. SRAM WRITE A write cycle is performed whenever E and W are LOW and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W go HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. 1. 2. 3. 4. 5. 6. The STK12C68-IM software STORE cycle is initiated by executing sequential READ cycles from six specific 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SOFTWARE RECALL A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. It is recommended that G be kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tWLQZ after W goes LOW. SOFTWARE STORE Read address Read address Read address Read address Read address Read address Read address Read address Read address Read address Read address Read address 0000(hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the 47 STK12C68-IM EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. AUTOMATIC RECALL During power-up, or after any low power condition (VCAP < VSWITCH), when VCAP exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated. If the STK12C68-IM is in a WRITE state at the end of power-up RECALL , the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected between W and system VCC. HARDWARE PROTECT The STK12C68-IM offers hardware protection against inadvertent STORE operation during low voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations will be inhibited. HSB OPERATION The Hardware Store Busy pin (HSB) is an open drain circuit acting as both input and output to perform two different functions. When driven low by the internal chip circuitry it indicates that a STORE operation (initiated via any means) is in progress within the chip. When driven low by external circuitry for longer than tASSERT, the chip will conditionally initiate a STORE operation after tDELAY. READ and WRITE operations that are in progress when HSB is driven low (either by internal or external circuitry) will be allowed to complete before the STORE operation is performed, in the following manner. After HSB goes low, the part will continue normal SRAM operations for tDELAY. During tDELAY, a transition on any address or control signal will terminate SRAM operation and cause the STORE to commence. Note that if an SRAM write is attempted after HSB has been forced low, the write will not occur and the STORE operation will begin immediately. HARDWARE-STORE-BUSY (HSB) is a high speed, low drive capability bi-directional control line. In order to allow a bank of STK12C68-IMs to perform synchronized STORE functions, the HSB pin from a number of chips may be connected together. Each chip contains a small internal current source to pull HSB HIGH when it is not being driven low. To decrease the sensitivity of this signal to noise generated on the PC board, it may optionally be pulled to VCCX via an external resistor with a value such that the combined load of the resistor and all parallel chip connections does not exceed IHSB_OL at VOL. Do not connect this or any other pull-up to the VCAP node. If HSB is to be connected to external circuits other than other STK12C68-IMs, an external pull-up resistor should be used. During any STORE operation, regardless of how it was initiated, the STK12C68-IM will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of a STORE operation, the part will be disabled until HSB actually goes HIGH. AUTOMATIC STORE OPERATION During normal operation, the STK12C68-IM will draw current from VCCX to charge up a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX and initiate a STORE operation. Figure 1 shows the proper connection of capacitors for automatic store operation. The charge storage capacitor should have a capacity of at least 100µF (± 20%) at 6V. Each STK12C68-IM must have its own 100µF capacitor. Each STK12C68-IM must have a high quality, high frequency bypass capacitor of 0.1µF connected between VCAP and VSS, using leads and traces that are as short as possible. If the AutoStore™ function is not required, then VCAP should be tied directly to the power supply and VCCX should be tied to ground. In this mode, STORE operations may be triggered through software control or the HSB pin. In either event, VCAP (Pin 1) must always have a proper bypass capacitor connected to it. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB LOW will be ignored unless at least one WRITE operation has taken place since the most recent STORE cycle. Note that if HSB is driven low via external circuitry and no WRITEs have taken place, the part will still be disabled until HSB is allowed to return HIGH. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place. 48 STK12C68-IM PREVENTING AUTOMATIC STORES The AutoStore™function can be disabled on the fly by holding HSB HIGH with a driver capable of sourcing 15mA at a VOH of at least 2.2V as it will have to overpower the internal pull-down device that drives HSB low for 20µs at the onset of an AutoStore™. When the STK12C68-IM is connected for AutoStore™operation (system VCC connected to VCCX and a 100uF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK12C68-IM will attempt to pull HSB low; if HSB doesn't actually get below VIL, the part will stop trying to pull HSB LOW and abort the AutoStore™attempt. LOW AVERAGE ACTIVE POWER The STK12C68-IM has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55ns. Figure 2 below shows the relationship between ICC and access times for READ cycles. All remaining inputs are assumed to cycle, and current consumption is given for all inputs at CMOS or TTL levels. Figure 3 shows the same relationship for WRITE cycles. When E is HIGH, the chip consumes only standby currents, and these plots do not apply. 28 VCCX 26 HSB 100uF ± 20% + 0.1uF Bypass nvSRAM VSS 14 100 Power Supply 10K Ohms (optional) The overall average current drawn by the part depends on the following items: 1) CMOS or TTL input levels; 2) the time during which the chip is disabled (E HIGH); 3) the cycle time for accesses (E LOW); 4) the ratio of reads to writes; 5) the operating temperature; 6) the VCC level; and 7) output load. 100 80 60 40 TTL 20 CMOS 0 Average Active Current (ma) 1 Average Active Current (ma) VCAP The cycle time used in Figure 2 corresponds to the length of time from the later of the last address transition or E going LOW to the earlier of E going HIGH or the next address transition. W is assumed to be HIGH, while the state of G does not matter. Additional current is consumed when the address lines change state while E is asserted. The cycle time used in Figure 3 corresponds to the length of time from the later of W or E going LOW to the earlier of W or E going HIGH. 80 60 40 TTL 20 CMOS 0 50 100 150 200 Cycle Time (ns) Figure 2 ICC (Max) Reads Figure 1 Schematic Diagram 100 150 200 Cycle Time (ns) Figure 3 ICC (Max) Writes Note: Typical at 25° C 49 50 STK12C68-IM ORDERING INFORMATION STK12C68 - C 35 IM Temperature Range IM = Industrial (-40 to +85°C) with Military Screening Access Time 25 = 25ns 35 = 35ns 45 = 45ns Package C = Ceramic 28 pin 300 mil DIP with Gold Lead Finish K = Ceramic 28 pin 300 mil DIP with Solder DIP L = Ceramic 28 pin LCC 50