P3C1024L ULTRA LOW POWER 128K x 8 CMOS STATIC RAM FEATURES VCC Current (Commercial/Industrial) — Operating: 10mA/12mA — CMOS Standby: 10µA/10µA Common Data I/O Access Times —55/70 (Commercial or Industrial) Fully TTL Compatible Inputs and Outputs Single 3.3 Volts ± 0.3V Power Supply Automatic Power Down Three-State Outputs Advanced CMOS Technology Easy Memory Expansion Using CE1, CE2 and OE Inputs Packages —32-Pin 445 mil SOP —32-Pin TSOP DESCRIPTION The P3C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V ± 0.3V tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P3C1024L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. The P3C1024L is packaged in a 32-pin TSOP and 445 mil SOP. PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM SOP (S12) TOP VIEW See end of datasheet for TSOP pin configuration. Document # SRAM132 REV OR Revised April 2006 1 P3C1024L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 3.0V ≤ VCC ≤ 3.6V Industrial (-40°C to 85°C) 3.0V ≤ VCC ≤ 3.6V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol Min Max Unit Supply Voltage with Respect to GND -0.3 3.9 V Terminal Voltage with Respect to GND -0.3 VCC + 0.3 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 20 mA ILAT Latch-up Current VCC VTERM Parameter >200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Test Conditions Symbol Parameter VOH Output High Voltage (I/O0 - I/O7) IOH = –1mA, VCC = 3.3V VOL Output Low Voltage (I/O0 - I/O7) IOL = 2.1mA VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current ILO Output Leakage Current GND ≤ VOUT ≤ VCC CE1 ≥ VIH or CE2 ≤ VIL ISB VCC Current TTL Standby Current (TTL Input Levels) ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) Document # SRAM132 REV OR Min Max 2.4 Unit V 0.4 V 2.2 VCC + 0.3 V -0.3 0.8 V -2 -1 +2 +1 µA -2 -1 +2 +1 µA VCC = 3.6V, IOUT = 0 mA CE1 = VIH or CE2 = VIL 3 mA VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V 10 µA GND ≤ VIN ≤ VCC Ind'l. Com'l. Ind'l. Com'l. Page 2 of 9 P3C1024L CAPACITANCES(4) (VCC = 3.3V, TA = 25°C, f = 1.0 MHz) Symbol Parameter Test Conditions Max Unit CIN Input Capacitance VIN = 0V 8 pF COUT Output Capacitance VOUT = 0V 9 pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter -55 -70 Unit Commercial 10 8 mA Industrial 12 10 mA Temperature Range Dynamic Operating Current Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter tRC Read Cycle Time tAA Address Access Time tAC tOH Chip Enable Access Time Output Hold from Address Change -70 -55 Min Max 55 Min Max Unit ns 70 55 70 ns 55 70 ns 10 10 ns 10 10 ns tLZ Chip Enable to Output in Low Z tHZ Chip Disable to Output in High Z 20 25 ns tOE Output Enable Low to Data Valid 25 35 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time Document # SRAM132 REV OR 5 5 20 0 ns 25 0 55 ns ns 70 ns Page 3 of 9 P3C1024L OE CONTROLLED)(1) READ CYCLE NO. 1 (OE READ CYCLE NO. 2 (ADDRESS CONTROLLED) CE CONTROLLED) READ CYCLE NO. 3 (CE Notes: 1. WE is HIGH for READ cycle. 2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. Document # SRAM132 REV OR 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. Page 4 of 9 P3C1024L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) -70 -55 Symbol Parameter tWC Write Cycle Time 55 70 ns tCW Chip Enable Time to End of Write 40 60 ns tAW Address Valid to End of Write 40 60 ns tAS Address Set-up Time 0 0 ns tWP Write Pulse Width 40 50 ns tAH Address Hold Time 0 0 ns tDW Data Valid to End of Write 25 30 ns tDH Data Hold Time 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write Min Max Min 20 10 Max 25 10 Unit ns ns WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM132 REV OR Page 5 of 9 P3C1024L CE CONTROLLED)(6) TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE TRUTH TABLE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load Mode CE1 CE2 OE WE I/O Power Standby 3ns Standby H X X X High Z 1.5V 1.5V Standby X L X X High Z Standby Output Disabled L H H H High Z Active Read L H H DOUT Write L H L X L DIN Active Active See Fig. 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the high speed of the P3C1024L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. Document # SRAM132 REV OR To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.75V (Thevenin Voltage) at the comparator input, and a 595Ω resistor must be used in series with DOUT to match 645Ω (Thevenin Resistance). Page 6 of 9 P3C1024L DATA RETENTION Symbol Parameter Test Conditions Min 2.0 VDR VCC for Data Retention CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V ICCDR (1) Data Retention Current VDR = 2.0V tCDR Chip Deselect to Data Retention Time See Retention Waveform tR Operating Recovery Time(2) Max Unit V 10 µA 0 ns 100 µs 1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V 2. VCC ramp from VDR to VCC (min) > 100 µs for full device operation. CE1 CONTROLLED) LOW VCC DATA RETENTION WAVEFORM 1 (CE LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED) Document # SRAM132 REV OR Page 7 of 9 P3C1024L ORDERING INFORMATION SELECTION GUIDE The P3C1024L is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Package Speed -55 -70 Plastic SOP (445 mil) -55SC -70SC TSOP -55TC -70TC Plastic SOP (445 mil) -55SI -70SI TSOP -55TI -70TI TSOP PIN CONFIGURATION Document # SRAM132 REV OR Page 8 of 9 P3C1024L Pkg # # Pins Symbol A A1 b2 C D e E H h L α Pkg # # Pins Symbol A A2 b D E e HD S12 SOIC/SOP SMALL OUTLINE IC PACKAGE 32 (445 Mil) Min Max 0.118 0.004 0.014 0.020 0.006 0.012 0.790 0.820 0.050 BSC 0.435 0.455 0.546 0.566 0.010 0.029 0.023 0.039 0° 8° T3 32 Min Max 0.048 0.037 0.042 0.006 0.011 0.720 0.729 0.307 0.323 0.50 mm BSC 0.779 0.796 Document # SRAM132 REV OR TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm) All dimensions in inches except as noted Page 9 of 9 P3C1024L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM132 P3C1024L LOW POWER 128K x 8 CMOS STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE OR Apr-06 JDB Document # SRAM132 REV OR DESCRIPTION OF CHANGE New Data Sheet Page 10 of 9