P4C1049/P4C1049L HIGH SPEED 512K x 8 STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) — 15/20/25 ns (Commercial) — 20/25/35 ns (Industrial) — 20/25/35/45/55/70 ns (Military) Low Power Single 5V±10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O DESCRIPTION The P4C1049 is a 4 Megabit high-speed CMOS static RAM organized as 512Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times as fast as 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1049 is a member of a family of PACE RAM™ products offering fast access times. Functional Block Diagram Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —36-Pin Ceramic DIP (600 mil) —36-Pin SOJ (400 mil) —36-Pin FLATPACK —36-Pin LCC (452 mil x 920 mil) The P4C1049 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A18. Reading is accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Pin ConfigurationS SOLDER-SEAL FLATPACK (FS-4), SOJ (J9, CJ2) LCC (L11) dip pin-out inside datasheet Document # SRAM128 REV C Revised August 2011 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM Maximum Ratings(1) Sym Parameter RECOMMENDED OPERATING CONDITIONS Value Unit V Grade(2) Ambient Temp GND VCC 0°C to 70°C 0V 5.0V ± 10% Industrial -40°C to +85°C 0V 5.0V ± 10% Military -55°C to +125°C 0V 5.0V ± 10% VCC Power Supply Pin with Respect to GND -0.5 to +7 VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter Commercial CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) PT Power Dissipation 1.0 W CIN Input Capacitance IOUT DC Output Current 50 mA COUT Output Capacitance Conditions Typ Unit VIN=0V 8 pF VOUT=0V 8 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter P4C1049 Test Conditions Max Min Max VCC + 0.3 2.2 VCC + 0.3 V 0.8 V VCC + 0.3 V 0.2 V 0.4 V Input High Voltage 2.2 VIL Input Low Voltage -0.3 VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min VOH Output High Voltage (TTL Load) IOH = -4 mA, VCC = Min Input Leakage Current VCC = Max, VIN = GND to VCC (3) VCC - 0.2 -0.3 VCC = Max, CE = VIH, VOUT = GND to VCC ILO Output Leakage Current ISB Standby Power Supply Current (TTL Input Levels) CE ≥ VIH, VCC = Max, f = Max, CE ≥ VHC, VCC = Max, f = 0, ISB1 Standby Power Supply Current (CMOS Input Levels) Outputs Open (3) 0.8 VCC + 0.3 0.2 -0.3 (3) VCC - 0.2 -0.3 (3) 0.4 2.4 2.4 V -10 +10 -5 +5 -5 +5 N/A N/A -10 +10 -5 +5 IND/COM -5 +5 N/A N/A MIL — 45 — 40 IND/COM — 40 — N/A MIL — 15 — 10 IND/COM — 10 — N/A MIL µA IND/COM MIL µA mA Outputs Open VIN ≤ VLC or VIN ≥ VHC Unit Min VIH ILI P4C1049L mA N/A = Not applicable Document # SRAM128 REV C Page 2 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM DATA RETENTION CHARACTERISTICS (P4C1049L Military Temperature Only) Sym Parameter Test Conditions Min Typ* VCC= Max VCC= 2.0V 2.0V Unit VDR VCC for Data Retention 3.0 V ICCDR Data Retention Current CE ≥ VCC -0.2V, tCDR Chip Deselect to Data Retention Time VIN ≥ VCC -0.2V 0 ns tR† Operation Recovery Time or VIN ≤ 0.2V tRC§ ns 2 3 mA * TA = +25°C § tRC = Read Cycle Time † This Parameter is guaranteed but not tested DATA RETENTION WAVEFORM POWER DISSIPATION CHARACTERISTICS VS. SPEED Sym ICC Parameter Dynamic Operating Current* Temperature Range -15 -20 -25 -35 -45 -55 -70 Unit Commercial 220 185 Industrial N/A 190 180 N/A N/A N/A N/A mA 185 175 N/A N/A N/A mA Military N/A 200 195 185 175 170 165 mA * VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. Document # SRAM128 REV C Page 3 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -15 Min -20 Max 15 Min -25 Max 20 Min -35 Max Max Max Max Max 15 20 25 35 45 55 70 ns tAC Chip Enable Access Time 15 20 25 35 45 55 70 ns tOH Output Hold from Address Change 3 3 3 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 3 3 3 3 3 3 3 ns tHZ Chip Disable to Output in High Z 8 9 11 15 20 25 30 ns tOE Output Enable Low to Data Valid 7 9 10 15 20 25 30 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 7 0 9 0 15 10 0 20 0 15 0 25 0 20 0 35 70 Unit Address Access Time 0 55 Min tAA 0 45 Min -70 Read Cycle Time 0 35 Min -55 tRC 0 25 Min -45 0 25 0 45 ns ns 30 0 55 ns ns 70 ns TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) Document # SRAM128 REV C Page 4 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED) (5, 7) AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -15 -20 -25 -35 -45 -55 -70 Sym Parameter Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 15 20 25 35 45 55 70 ns tCW Chip Enable Time to End of Write 12 14 18 22 30 35 40 ns tAW Address Valid to End of Write 12 14 16 20 25 35 40 ns tAS Address Setup Time 0 0 0 0 0 0 0 ns tWP Write Pulse Width 12 14 16 22 25 30 35 ns tAH Address Hold Time 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 9 11 13 15 20 25 30 ns tDH Data Hold Time 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 8 3 10 3 Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL and IIL not more negative than –2.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM128 REV C 11 3 15 5 18 5 25 5 30 5 ns ns 4.This parameter is sampled and not 100% tested. 5.WE is HIGH for READ cycle. 6.CE is LOW and OE is LOW for READ cycle. 7.ADDRESS must be valid prior to, or coincident with CE transition LOW. 8.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9.Read Cycle Time is measured from the last valid address to the first transitioning address. Page 5 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11) Timing Waveform of Write Cycle No. 2 (CE Controlled)(10) AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level Output Load Mode CE OE WE Standby H X X High Z Standby 1.5V DOUT Disabled L H H High Z Active See Figures 1 and 2 Read L L H DOUT Active Write L X L High Z Active Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state Document # SRAM128 REV C I/O Power 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 6 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM Figure 1. Output Load Figure 2. Thevenin Equivalent Note: Because of the ultra-high speed of the P4C1049/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). * including scope and test fixture. ORDERING INFORMATION Document # SRAM128 REV C Page 7 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM 32-PIN CERAMIC DIP PIN CONFIGURATION 32-Pin DIP (C10) Document # SRAM128 REV C Page 8 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM SIDEBRAZED DUAL IN-LINE PACKAGE C10 Pkg # # Pins 32 (600 mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.680 E 0.510 0.620 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - Pkg # FS-4 # Pins 36 Symbol Min Max A 0.089 0.125 b 0.015 0.019 c 0.003 0.007 D 0.910 0.930 E 0.505 0.515 E1 - 0.530 E2 0.385 0.395 E3 0.055 0.065 e 0.050 BSC L 0.300 0.350 Q 0.015 0.038 S - 0.045 M - 0.002 N SOLDER SEAL FLATPACK 36 Document # SRAM128 REV C Page 9 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM SOJ SMALL OUTLINE IC PACKAGE J9 Pkg # # Pins 36 Symbol Min Max A 0.130 0.145 A1 0.082 - b 0.015 0.020 C 0.007 0.013 D 0.920 0.930 e 0.050 BSC E 0.435 0.445 E1 0.395 0.405 E2 Q 0.370 BSC 0.045 0.055 Pkg # CJ2 # Pins 36 CERAMIC SOJ SMALL OUTLINE IC PACKAGE Symbol Min Max A 0.120 0.165 B1 0.030R TYP B2 0.020 REF B3 0.025 0.045 D 0.816 0.838 E 0.419 0.431 E2 0.360 0.380 e E1 0.050 BSC 0.430 0.454 Document # SRAM128 REV C Page 10 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM RECTANGULAR LEADLESS CHIP CARRIER L11 Pkg # # Pins 36 Symbol Min Max A 0.080 0.100 A1 0.054 0.066 B 0.022 0.028 D 0.910 0.930 D1 0.840 0.860 E 0.445 0.460 e .050 BSC L .100 TYP L2 0.115 0.135 P - 0.006 R .009 TYP Document # SRAM128 REV C Page 11 P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM REVISIONS DOCUMENT NUMBER SRAM 128 DOCUMENT TITLE P4C1049/P4C1049L - HIGH SPEED 512K X 8 STATIC CMOS RAM REV ISSUE DATE ORIGINATOR OR Oct-2005 JDB New Data Sheet A Jan-2008 JDB Added CJ2 Ceramic SOJ Package B Mar-2009 JDB Added C10 Ceramic DIP Package C Aug-2011 JDB Corrected typo in package list Document # SRAM128 REV C DESCRIPTION OF CHANGE Page 12