5 Advance Information CY26126 Dual Output 125-MHz Clock Generator Features Benefits • Integrated phase-locked loop Highest-performance PLL tailored for multimedia applications • Low skew, low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • 3.3V Operation Part Number Outputs Input Frequency Range Output Frequencies CY26126 2 25 MHz 2 copies of 125 MHz (3.3V) Logic Block Diagram 25 XIN P Comp OSC. OUTPUT MULTIPLEXER AND DIVIDERS Q XOUT VCO 125 MHz 125 MHz P PLL OE VDD VSS Pin Configurations CY26126 8-pin SOIC XIN 1 8 XOUT VDD 2 7 OE VSS 3 6 4 5 CLKB CLKA VSS Cypress Semiconductor Corporation Document #: 38-07351 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY26126 Advance Information Pin Summary Name Pin Number Description XIN 1 Reference Input VDD 2 3.3V Voltage Supply OE 3 Output Enable VSS 4 Ground VSS 5 Ground CLKA 6 125-MHz Clock Output A CLKB 7 125-MHz Clock Output B 8 Reference Output XOUT [1] Absolute Maximum Conditions Parameter Description Supply Voltage VDD Min. Max. Unit. –0.5 7.0 V –65 125 °C 125 °C Temperature[2] TS Storage TJ Junction Temperature Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Electro-Static Discharge 2 kV Recommended Operating Conditions Parameter Description VDD Operating Voltage Min. Typ. Max. Unit 3.14 3.3 3.47 V TA Ambient Temperature 70 °C CLOAD Max. Load Capacitance 0 15 pF Pmax Max. Output Power Dissipation 150 mW fREF Reference Frequency tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 25 MHz 0.05 500 ms DC Electrical Characteristics Parameter Min. Typ. IOH Output High Current Description VOH = VDD – 0.5, VDD = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 mA VIH Input High Voltage CMOS Levels 70% of VDD 0.7 CMOS Levels 30% of VDD VIL Input Low Voltage CIN Input Capacitance IIZ Input Leakage Current Conditions Supply Current Sum of Core and Output IDD Notes: 1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal). 2. Rated for 10 years. Document #: 38-07351 Rev. *A Max. VDD 0.3 VDD 7 pF µA 5 Current Unit 35 mA Page 2 of 5 CY26126 Advance Information AC Electrical Characteristics (VDD = 3.3V)[3] Parameter Description Conditions Min. Typ. Max. 55 Unit 45 50 t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD % 200 ps 3 ms Note: 3. Not 100% tested. Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS VDD 0.1 µF GND t1 t2 CLK 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26126SC S8 8-Pin SOIC Commercial 3.3V Document #: 38-07351 Rev. *A Page 3 of 5 CY26126 Advance Information Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07351 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Advance Information CY26126 Document Title: CY26126 Dual Output 125-MHz Clock Generator Document Number: 38-07351 REV. ECN NO. Issue Date Orig. of Change ** 112233 03/01/02 CKN *A 121891 12/14/02 RBI Document #: 38-07351 Rev. *A Description of Change New data sheet Power up requirements added to Operating Conditions Information Page 5 of 5