NSC DM74LS952

DM74LS952 (DM86LS52)
Dual Rank 8-Bit TRI-STATEÉ Shift Register
General Description
Features
These circuits are TRI-STATE, edge-triggered, 8-bit I/O registers in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes: parallel
load from I/O pins to register ‘‘A’’, parallel transfer down
from register ‘‘A’’ to serial shift register ‘‘B’’, parallel transfer
up from shift register ‘‘B’’ to register ‘‘A’’, serial shift of register ‘‘B’’, synchronously clear. Since the registers are edgetriggered by the positive transition of the clock, the control
lines which determine the mode or operation are completely
independent of the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their
TRI-STATE inputs and outputs on the same pins.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Registers are edge-triggered by the positive transition
of the clock
All inputs are PNP transistors
Input disable dominates over output disable
Output high impedance state does not impede any other mode of operation
8-bit I/O pins are TRI-STATE buffers
Typical shift frequency is 36 MHz
Typical power dissipation is 305 mW
All control inputs are active when in an ‘‘L’’ logic state
Devices can be cascaded into N-bit word
Connection Diagram
Dual-In-Line Package
Pin Description
DISOÐOutput disable
ISÐSerial input
DISIÐInput disable
DISTUÐTransfer up disable
DISTDÐTransfer down disable
DISSÐShift disable
OSÐSerial output
CLKÐClock
GNDÐGround
I/O 1 . . . I/O 8Ð8-bit I/O pins
VCCÐSupply Voltage
TL/F/6437 – 1
Top View
Order Number DM74LS952N or DM86LS52N
See NS Package Number N18A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/6437
RRD-B30M105/Printed in U. S. A.
DM74LS952 (DM86LS52) Dual Rank 8-Bit TRI-STATE Shift Register
August 1991
Absolute Maximum Ratings (Note)
Supply Voltage
7V
Input Voltage
7V
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM74LS/DM86LS
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
300§ C
Recommended Operating Conditions
Symbol
Parameter
VCC
Supply Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IOH
High-Level Output Current
IOL
Low-Level Output Current
fCLOCK
Clock Frequency (Note 5)
Clock Pulse
Min
Typ
Max
Units
4.75
5
5.25
V
0.8
V
b 5.2
mA
2
V
0
16
mA
25
MHz
High Pulse Width (Note 5)
25
17
ns
Low Pulse Width (Note 5)
15
7
ns
tSET-UP
Data Set-Up Time (Note 5)
10
tHOLD
Data Hold Time (Note 5)
0
TA
Free Air Operating Temperature
0
ns
ns
70
§C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions (1)
Min
Typ (2)
Max
Units
b 1.5
V
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High-Level Output Voltage
VCC e Min, VIH e 2V,
VIL e VIL Max
IOH e b5.2 mA
VOL
Low-Level Output Voltage
VCC e Min, VIH e 2V,
VIL e VIL Max
IOL e 8 mA
0.25
0.4
IOL e 16 mA
0.35
0.5
2.4
V
V
II
Input Current at Maximum
Input Voltage
VCC e Max, VI e 5.5V
0.1
mA
IIH
High-Level Input Current
VCC e Max, VI e 2.7V
20
mA
IIL
Low-Level Input Current
VCC e Max, VI e 0.4V
IOS
Short-Circuit Output Current
VCC e Max (3)
ICC
Supply Current
VCC e Max (4)
IOFF
TRI-STATE I/O Current
VCC e Max, VIH e 2V
b 20
61
99
mA
20
mA
VO e 0.4V
b 20
mA
Note 2: All typical values are at VCC e 5V, TA e 25§ C.
Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Note 4: ICC is measured with serial output open, the clock and shift disable input at 2.4V. All other control inputs and I/O pins grounded.
2
mA
mA
VO e 2.4V
Note 1: For conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
Note 5: TA e 25§ C and VCC e 5V.
b 50
b 100
Switching Characteristics at VCC e 5V and TA e 25§ C
Symbol
Parameter
Conditions
Min
Max
Units
fMAX
Maximum Clock Frequency
25
tPLH
Propagation Delay Time, Low-to-High-Level
from Clock to Any Outputs
7
33
ns
tPHL
Propagation Delay Time, High-to-Low Level
from Clock to Any Output
10
48
ns
CL e 15 pF, RL e 1 kX
MHz
tENABLE
Enable Time from Any Control Inputs
5
24
ns
tDISABLE
Disable Time from Any Control Inputs
6
27
ns
tPZH
Output Enable Time to High Level
5
23
ns
tPZL
Output Enable to Low Level
4
18
ns
tPHZ
Output Disable Time from High Level
5
23
ns
tPLZ
Output Disable Time from Low Level
6
27
ns
CL e 5 pF, RL e 1 kX
Logic Diagram
TL/F/6437 – 2
3
4
H
H
L
H
H
L
H
H
L
H
L
X
H
L
X
H
L
X
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
X
X
d
d
d
d
d
d
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Output
Input
Hi-Z
Output
Input
Hi-Z
Output
Input
Hi-Z
Output
Input
Hi-Z
Output
Input
Hi-Z
Output
Input
L
L
I2
L
L
I3
L
L
I4
L
L
I5
L
L
I6
L
L
I7
L
L
I8
b1 b2 b3 b4 b5 b6 b7 b8
b1 b2 b3 b4 b5 b6 b7 b8
www DOR xxx
a1 a2 a3 a4 a5 a6 a7 a8
a1 a2 a3 a4 a5 a6 a7 a8
I1 I2 I3 I4 I5 I6 I7 I8
L
L
I1
a1 a2 a3 a4 a5 a6 a7 a8
a1 a2 a3 a4 a5 a6 a7 a8
I1 I2 I3 I4 I5 I6 I7 I8
b1 b2 b3 b4 b5 b6 b7 b8
b1 b2 b3 b4 b5 b6 b7 b8
www DOR xxx
a1 a2 a3 a4 a5 a6 a7 a8
a1 a2 a3 a4 a5 a6 a7 a8
I1 I2 I3 I4 I5 I6 I7 I8
d
d
d
d
d
d
L
L
L
a1
a1
a1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
L
L
L
a2
a2
a2
b2
b2
b2
b2
b2
b2
B2
A
Data of the serial input
A
‘‘Data ORing function’’ ORing data from both I/O pins and register ‘‘B’’, i.e., I1 a b1, I2 a b2, I3 a b3 . . . I8 a b8
d
b3
b3
b3
b3
b3
b3
L
L
L
a4
a4
a4
b4
b4
b4
b4
b4
b4
B4
b4
b4
b4
b4
b4
b4
L
L
L
a5
a5
a5
b5
b5
b5
b5
b5
b5
B5
u transition of the clock
DOR
The level of steady state inputs of the I/O pins
b2
b2
b2
b2
b2
b2
L
L
L
a3
a3
a3
b3
b3
b3
b3
b3
b3
B3
b5
b5
b5
b5
b5
b5
L
L
L
a6
a6
a6
b6
b6
b6
b6
b6
b6
B6
b6
b6
b6
b6
b6
b6
L
L
L
a7
a7
a7
b7
b7
b7
b7
b7
b7
B7
Content of Lower Serial Shift Reg. ‘‘B’’
The content of the upper register ‘‘A’’/the lower serial shift register ‘‘B’’ before the most recent
High impedance state/output state/input state
L
L
L
L
L
L
X
X
X
X
X
X
H
H
H
H
H
H
B1
Table I
A
A
a1 . . . a8/b1 . . . b8
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
A1 A2 A3 A4 A5 A6 A7 A8
Content of Upper Reg. ‘‘A’’
I1 . . . I8
A
Hi-Z/Output/Input/
Don’t Care
H
H
L
H
L
X
A
H
H
L
H
L
X
X
H
H
L
H
L
X
8-Bit I/O
DISO DISI DISTU DISTD DISS CLK IS
Pins
Function Table
b7
b7
b7
b7
b7
b7
L
L
L
a8
a8
a8
b8
b8
b8
b8
b8
b8
B8
Comments
(1) Synchronously clear both registers to
(2) logic ‘‘L’’ level
(3) Enter data to reg. ‘‘A’’ clear reg. ‘‘B’’
b7
Transfer up and serial shifting
b7
b7 DOR function and serial shifting
b7
Serial shifting in the lower reg. ‘‘B’’
b7
b7 Entering data and serial shifting
L
L
L
a8
Transfer data down from reg. ‘‘A’’ to reg. ‘‘B’’
a8
a8 Entering data and transfer down
b8
Transfer data up from reg. ‘‘B’’ to reg. ‘‘A’’
b8
b8 Reg. ‘‘A’’ will OR data from I/O to reg. ‘‘B’’
b8
Stable state
b8
b8 Entering data from I/O to reg. ‘‘A’’
OS
Timing Diagram
TL/F/6437 – 3
5
AC Test Circuit and Switching Time Waveforms
All diodes are 1N916 or 1N3064.
CL includes probe and jig capacitance.
TL/F/6437 – 4
TL/F/6437 – 5
All input pulses are supplied by generators having tr s 15 ns, tf s 6 ns, PRR s 1 MHz, ZOUT & 50X.
Cascading Packages
Cascading Packages for N-Bit Word
TL/F/6437 – 6
6
7
DM74LS952 (DM86LS52) Dual Rank 8-Bit TRI-STATE Shift Register
Physical Dimensions inches (millimeters)
18-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS952N or DM86LS52N
NS Package Number N18A
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