INTEGRATED CIRCUITS DATA SHEET TDA4885 150 MHz video controller with I2C-bus Product specification Supersedes data of 1997 Mar 19 File under Integrated Circuits, IC02 1997 Nov 25 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.6 7.7 7.8 7.9 7.10 Signal input stage (input clamping, blanking and clipping) Electronic potentiometer stages Contrast control (driven by I2C-bus, 6-bit DAC) Brightness control (driven by I2C-bus, 6-bit DAC) Gain control (driven by I2C-bus, 6-bit DAC) and grey scale tracking Output stage Pedestal blanking Output clamping, feedback references and DAC outputs Clamping and blanking pulses On Screen Display (OSD) Limiting by contrast reduction Gain modulation I2C-bus control 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 I2C-BUS PROTOCOL 12 INTERNAL CIRCUITRY 13 TEST AND APPLICATION INFORMATION 13.1 13.2 Test application Recommendations for building the application board 14 PACKAGE OUTLINE 15 SOLDERING 15.1 15.2 15.3 Introduction Soldering by dipping or by wave Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I2C COMPONENTS 7.2 7.2.1 7.2.2 7.2.3 7.3 7.4 7.5 1997 Nov 25 2 TDA4885 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 1 FEATURES TDA4885 2 • 150 MHz pixel rate GENERAL DESCRIPTION • Positive feedback for AC-coupled cathodes The TDA4885 is a monolithic integrated RGB pre-amplifier for colour monitor systems (e.g. 15" and 17") with I2C-bus control and OSD. In addition to bus control beam current limiting and gain modulation are possible. The signals are amplified in order to drive commonly used video modules or discrete solutions. Individual black level control with negative feedback from the cathode (DC coupling) or fixed black level control with positive feedback and 3 DAC outputs for external cut-off control (AC coupling) is possible. • DAC outputs for black level restoration with AC-coupled cathodes With special advantages the circuit can be used in conjunction with the TDA485x monitor deflection IC family. • 2.7 ns rise time • Gain modulation capability for brightness uniformity • I2C-bus control • Grey scale tracking • On Screen Display (OSD) mixing • Negative feedback for DC-coupled cathodes • Integrated black level storage capacitors • Beam current limiting • Analog subcontrast setting • Pedestal blanking • OSD contrast • Sync clipping. 3 ORDERING INFORMATION TYPE NUMBER TDA4885 1997 Nov 25 PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) 3 VERSION SOT232-1 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 4 TDA4885 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage (pin 7) 7.6 8.0 8.8 V IP supply current (pin 7) − 20 25 mA VP1, 2, 3 channel supply voltage (pins 29, 24 and 19) 7.6 8.0 8.8 V IP1, 2, 3 channel supply current (pins 29, 24 and 19) − 40 − mA Vi(b-w) input voltage (black-to-white value; pins 6, 8 and 10) − 0.7 1.0 V Vo(b-w) nominal output voltage swing (black-to-white value; pins 30, 25 and 20) nominal contrast; maximum gain; pins 12, 13 and 14 grounded 2.5 2.8 − V Vo(b-w)(max) maximum output voltage swing (black-to-white value; pins 30, 25 and 20) maximum contrast; maximum gain; pins 12, 13 and 14 grounded − 4.5 − V Vo output voltage level (pins 30, 25 and 20) 0.1 − 6.0 V Vbl typical reference black level (pins 30, 25 and 20) 0.5 − 2.5 V Io(sink) peak output sink current during fast signal transients − − 20 mA Io(source) peak output source current during fast signal transients −40 − − mA B bandwidth −3 dB (small signal) − 150 − MHz tr(O) video rise time at signal outputs (pins 30, 25 and 20) − 2.7 − ns dVO over/undershoot at signal outputs (pins 30, 25 and 20) minimum rise/fall time − 5 − % αct crosstalk at signal outputs (pins 30, 25 and 20) f = 80 MHz − −30 − dB CC contrast control related to nominal contrast −28 − +4 dB GC gain control related to maximum gain −7 − 0 dB BC brightness control (typical black level voltage change related to output signal amplitude) −10 − +30 % − 125 − % −12 − 0 dB Vo(OSD)(max) maximum OSD output voltage swing related to nominal output voltage swing (pins 30, 25 and 20) COSD 1997 Nov 25 maximum OSD contrast; maximum gain; pins 12, 13 and 14 grounded OSD contrast control related to maximum OSD contrast 4 1997 Nov 25 VI3 VI2 VI1 INPUTCLAMPING BLANKING CLIPPING INPUTCLAMPING BLANKING CLIPPING INPUTCLAMPING BLANKING CLIPPING 6 8 10 5 fast blanking 1 FBL CONTRAST CONTRAST CONTRAST 3 4 OSD1 OSD2 OSD3 2 OSD-INPUT OSDCONTRAST OSDCONTRAST OSDCONTRAST DISO PEDST FPOL DISV REGISTER I2C-BUS 16 SCL GAIN GAIN 6-BIT DAC DISV 6-BIT DAC 13 14 8-BIT DAC HFB 11 BLANKING OUTPUT CLAMPING PEDST PEDESTAL BLANKING PEDST PEDESTAL BLANKING PEDST PEDESTAL BLANKING POLARITY SWITCH FPOL MODULATION 12 GM1 GM2 GM3 8-BIT DAC 8-BIT DAC 9 GND 7 VP SUPPLY 21 18 20 19 26 23 25 24 31 28 30 29 32 27 22 MHA343 CHANNEL 1 REFERENCE CHANNEL 2 REFERENCE CHANNEL 3 REFERENCE FB3 GND3 VO3 VP3 FB2 GND2 VO2 VP2 FB1 GND1 VO1 VP1 REF1 REF2 REF3 150 MHz video controller with I2C-bus Fig.1 Block diagram. CLI 5 INPUT CLAMPING VERTICAL BLANKING input clamping blanking BRIGHTNESS signal path 3 BRIGHTNESS signal path 2 GAIN 6-BIT DAC BRIGHTNESS signal path 1 BLANKING TDA4885 DISO 4-BIT DAC 6-BIT DAC data ok, full pagewidth LIMITING 6-BIT DAC 15 SDA 5 17 LIM Philips Semiconductors Product specification TDA4885 BLOCK DIAGRAM Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 6 TDA4885 PINNING SYMBOL PIN DESCRIPTION FBL 1 fast blanking input for OSD insertion OSD1 2 OSD input channel 1 OSD2 3 OSD input channel 2 OSD3 4 OSD input channel 3 CLI 5 vertical blanking input (input clamping) VI1 6 signal input channel 1 VP 7 supply voltage VI2 8 signal input channel 2 GND 9 VI3 handbook, halfpage FBL 1 32 REF1 OSD1 2 31 FB1 ground OSD2 3 30 VO1 10 signal input channel 3 OSD3 4 29 VP1 HFB 11 horizontal flyback input (output clamping, blanking) CLI 5 28 GND1 12 gain modulation input channel 1 VI1 6 GM1 27 REF2 GM2 13 gain modulation input channel 2 VP 7 26 FB2 GM3 14 gain modulation input channel 3 VI2 8 SDA 15 I2C-bus serial data input/output GND 9 SCL 16 I2C-bus clock input LIM 17 beam current limiting input, subcontrast setting GND3 18 ground channel 3 VP3 19 supply voltage channel 3 VO3 20 FB3 TDA4885 25 VO2 24 VP2 VI3 10 23 GND2 HFB 11 22 REF3 GM1 12 21 FB3 GM2 13 20 VO3 signal output channel 3 GM3 14 19 VP3 21 feedback input channel 3 SDA 15 18 GND3 REF3 22 reference voltage channel 3 SCL 16 17 LIM GND2 23 ground channel 2 VP2 24 supply voltage channel 2 VO2 25 signal output channel 2 FB2 26 feedback input channel 2 REF2 27 reference voltage channel 2 GND1 28 ground channel 1 VP1 29 supply voltage channel 1 VO1 30 signal output channel 1 FB1 31 feedback input channel 1 REF1 32 reference voltage channel 1 1997 Nov 25 MHA342 Fig.2 Pin configuration. 6 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 7 FUNCTIONAL DESCRIPTION 7.2.3 Gain control is used for white point adjustment (correction for different voltage to light amplification of the three colour channels) and therefore individual for the three channels. The video signals related to the reference black level can be gain controlled within a range of typical 7 dB. The nominal setting is maximum gain. The video signal is the addition of the contrast controlled input signal and the brightness shift. The gain setting is also valid for OSD signals, thus the complete ‘grey scale’ is effected by gain control. Signal input stage (input clamping, blanking and clipping) The RGB input signals with nominal signal amplitude of 0.7Vb-w are capacitively coupled into the TDA4885 from a low-ohmic source (75 Ω recommended) and actively clamped to an internal DC voltage during signal black level. Because of the high-ohmic input impedance of the TDA4885 the coupling capacitor (which also functions as storage capacitor during clamping pulses) can be relatively small (10 nF recommended). The internal leakage currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses. 7.3 A fast signal blanking stage belongs to the input stage which is driven by several blanking pulses (see Section “Clamping and blanking pulses”) and control bit DISV = 1. During the off condition the internal reference black level will be inserted instead of the input signals. 7.2.1 7.4 Electronic potentiometer stages CONTRAST CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC) 7.5 BRIGHTNESS CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC) Output clamping, feedback references and DAC outputs Aim of the output clamping (pins FB1, FB2 and FB3) is to set the reference black level of the signal outputs to a value which corresponds to the ‘extended cut-off voltage’ of the CRT cathodes. At lack of output clamping pulses the integrated storage capacitors will discharge resulting in output signals going to switch-off voltage. Feedback references are driven by the I2C-bus. With brightness control the video black level will be shifted in relation to the reference black level simultaneously for all three channels. With a negative setting (maximum 10% of nominal signal amplitude) dark signal parts will be lost in ultra black while for positive settings (maximum 30% of nominal signal amplitude) the background will alter from black to grey. The nominal brightness setting (10H) is no shift. The brightness setting is also valid for OSD signals. During blanking and output clamping the video black level will be blanked to reference black level (brightness blanking). 1997 Nov 25 Pedestal blanking For the video portion the reference black level should correspond to the ‘extended cut-off voltage’ at the cathode. During vertical flyback nevertheless retrace lines may be visible, though blanking to spot cut-off is useful. With control bit PEDST = 1 the pedestal black level will be adjusted by output clamping instead of the reference black level (see Fig.5). The pedestal black level is more negative than the video black level at minimum brightness setting and the voltage difference to reference black level is independent of any user control. The input signals related to the internal reference black level can be simultaneously adjusted by contrast control with a control range of typically 32 dB. The nominal contrast setting is defined for 26H (4 dB below maximum). 7.2.2 Output stage In the output stage the nominal input signal will be amplified to 2.8Vb-w output colour signal at nominal contrast and maximum gain. The maximum input-output amplification at maximum contrast and gain settings is 16 dB. By output clamping the reference black level can be adjusted. In order to achieve very fast rise and fall times of the output signals with minimum crosstalk between the channels, each output stage has its own supply voltage and ground pin. Composite signals will not disturb normal operations because a clipping circuit cuts all signal parts below black level. 7.2 GAIN CONTROL (DRIVEN BY I2C-BUS, 6-BIT DAC) AND GREY SCALE TRACKING See block diagram (Fig.1) and definition of levels and output signals (Chapter “Characteristics” notes 1 to 3; Figs 3 to 6). 7.1 TDA4885 7 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus During the vertical blanking pulse at pin CLI signal blanking, brightness blanking and with control bit PEDST = 1 pedestal blanking will be activated. Input clamping pulses during vertical blanking will not switch off blanking. 1. Control bit FPOL = 0 The cathode voltage (DC-coupled) is divided by a voltage divider and fed back to the IC. During the output clamping pulse it is compared with an adjustable feedback reference voltage with a range of 5.8 to 4.0 V. Any difference will lead to a reference black level correction (control bit PEDST = 0) or pedestal black level correction (control bit PEDST = 1) by charging or discharging the integrated capacitor which stores the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.5 V. The reference voltages are also fed to the DAC output pins (REF1, REF2 and REF3). For proper input clamping the input signals have to be at black level during the input clamping pulse. An input pulse at pin HFB (e.g. horizontal flyback pulse) will be scanned with two thresholds. If the input pulse exceeds the first one (typical 1.4 V) signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking will be activated. If the input pulse exceeds the second one (typical 3 V) additionally output clamping will be activated. The vertical blanking pulse can also be mixed with the horizontal flyback pulse at pin HFB. For correct operation it is necessary that there is enough room for ultra black signals (negative brightness setting, pedestal black level if control bit PEDST = 1). Any clipping with the video supply voltage can disturb signal rise/fall times or the black level stabilization. 7.7 For applications with AC-coupled cathodes positive feedback can be taken directly or divided by a voltage divider from the signal outputs or the emitter of an external emitter follower. During the output clamping pulse it is compared with a fixed reference voltage of 0.7 V. For black level restoration the DAC outputs (REF1, REF2 and REF3) with a range of 5.8 to 4.0 V can be used. With control bit DISO = 1 OSD, signal insertion and fast blanking (pin FBL) are disabled. The use of pedestal blanking allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit because the pedestal black level is the most negative output signal. 7.8 Limiting by contrast reduction Beam current limiting is possible with an external voltage at pin LIM. The maximum overall voltage gain of contrast (and OSD contrast) control can be reduced by a voltage between 4.5 V (start of reduction) and 2.0 V (−26 dB) without effecting the contrast bit resolution. By setting the maximum voltage at pin LIM to less than 4.5 V the maximum gain is reduced for all channels (subcontrast setting). The open-circuit pin will have a voltage of approximately 5.0 V but is very high-ohmic and should be tied to a voltage source of 5.0 V or higher or should be connected to a capacitance of some nF if not used. Clamping and blanking pulses The pin CLI of TDA4885 can be directly connected to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses. The threshold for the input clamping pulse (typical 3 V) is higher than the threshold for the vertical blanking pulse (typical 1.4 V) but there must be no blanking during input clamping. Thus vertical blanking only is enabled if no input clamping is detected. For this reason the input clamping pulse must have rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and opposite. The internal vertical blanking pulse will be delayed by typical 290 ns. 1997 Nov 25 On Screen Display (OSD) If the fast blanking input signal at pin FBL exceeds the threshold (typical 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 125% of the nominal colour signal (approximately 80% of the maximum colour signal). The amplitude can be controlled by OSD contrast (driven by I2C-bus) with a range of 12 dB. The OSD signals are inserted at the same point as the contrast controlled input signals and will be treated with brightness and gain control like normal input signals. 2. Control bit FPOL = 1 7.6 TDA4885 8 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 7.9 Gain modulation To achieve brightness uniformity over the screen scan dependent gain modulation is possible. With open-circuit pins the gain will be reduced by 20% giving the possibility of symmetrical gain modulations (±18%) with ±1 V related to the open-circuit voltage of about 2.0 V at any gain setting. If the gain modulation feature will not be used pins GM1, GM2 and GM3 should be grounded to profit by maximum voltage gain. 7.10 I2C-bus control The TDA4885 contains an I2C-bus receiver for several control functions: 1. Contrast control with 6-bit DAC 2. Brightness control with 6-bit DAC 3. OSD contrast control with 4-bit DAC 4. Gain control for each channel with 6-bit DAC 5. Internal feedback reference and external reference voltage control for each channel with 8-bit DAC 6. Control register with control bits FPOL, DISV, DISO and PEDST 7. Test register for production tests only. All registers are set to logic 0 (minimum value for control registers) after power-up and after internal power-on reset of the I2C-bus. 1997 Nov 25 9 TDA4885 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VP supply voltage (pin 7) 0 8.8 V VP1, 2, 3 supply voltage channel 1, 2 and 3 (pins 29, 24 and 19) 0 8.8 V Vi input voltage (pins 6, 8 and 10) −0.1 VP V Vext external DC voltage applied to the following pins: pins 1 to 4 −0.1 VP V pins 12, 13, 14 and 17 −0.1 VP V pins 11 and 5 −0.1 VP + 0.7 V pins 15 and 16 −0.1 VP V pins 31, 26 and 21 −0.1 VP + 0.7 V pins 30, 25 and 20 note 1 note 1 −0.1 VP V Io(av) average output current (pins 30, 25 and 20) − 20 mA IOM peak output current (pins 30, 25 and 20) − 50 mA Ptot total power dissipation − 1300 mW Tstg storage temperature −25 +150 °C Tamb operating ambient temperature −20 +70 °C Tj junction temperature −25 +150 °C VESD electrostatic handling for all pins machine model 0.75 µH (note 2) −250 +250 V human body model (note 3) −3000 +3000 V pins 32, 27 and 22 Notes 1. No external voltages. 2. Equivalent to discharging a 200 pF capacitor via a 10 Ω series resistor (“UZW-B0/FQ-B302” ). 3. Equivalent to discharging a 100 pF capacitor via a 1500 Ω series resistor (“UZW-B0/FQ-A302” ). 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1997 Nov 25 PARAMETER CONDITIONS thermal resistance from junction to ambient 10 in free air VALUE UNIT 60 K/W Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 10 CHARACTERISTICS All voltages and currents are measured in test circuit of Fig.19; all voltages are measured with respect to GND (pins 9, 28, 23 and 18); VP = VP1, 2, 3 = 8 V (pins 7, 29, 24 and 19); Tamb = 25 °C; nominal input signals [0.7 V (peak-to-peak value) at pins 6, 8 and 10]; nominal colour signals at signal outputs (pins 30, 25 and 20); reference black level (Vrbl) approximately 0.7 V; nominal settings for brightness and contrast; maximum settings for OSD contrast and gain; no limiting of contrast (V17 = 5 V); no OSD fast blanking (pin 1 connected to ground); no gain modulation (pins 12, 13 and 14 connected to ground); notes 1 to 3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage (pin 7) IP supply current (pin 7) VP1, 2, 3 channel supply voltage (pins 29, 24 and 19) IP1, 2, 3 channel supply current (pins 29, 24 and 19) VPSO 7.6 8.0 8.8 V − 20 25 mA 7.6 8.0 8.8 V signal outputs (pins 30, 25 and 20) open-circuit; Vrbl = 0.7 V; note 5 − 40 45 mA supply voltage for signal switch signal outputs switched to off (threshold at pin 7) switch-off voltage; note 1 − − 7.2 V no blanking, no input clamping −0.1 − +1.2 V blanking, no input clamping 1.6 − 2.6 V note 4 Clamping and blanking pulses (pins 5 and 11) V5 input clamping and vertical blanking input signal note 6 3.5 − VP V V5 = 1 V; note 7 −1.5 −0.2 −0.05 µA pin 5 grounded; note 7 −80 −60 −30 µA V5 = −0.1 V; note 7 −250 −200 −100 µA note 6; see Fig.7 − − 75 ns/V 0.6 − − µs input clamping, no blanking I5 input current tr/f5 rise/fall time for input clamping pulse, disable for blanking tW5 width of input clamping pulse tdl5 delay between leading edges of vertical blanking input pulse and internal blanking pulse V11 < 0.8 V; input pulse with 50 ns/V; threshold for rising input pulse V5 = 1.4 V; threshold after input clamping pulse V5 = 3 V; see Fig.7 − 270 − ns tdt5 delay between trailing edges of V11 < 0.8 V; input pulse with vertical blanking input pulse 50 ns/V; threshold V5 = 1.4 V; and internal blanking pulse see Fig.7 − 115 − ns V11 output clamping and blanking input signal no blanking, no output clamping −0.1 − +0.8 V blanking, no output clamping 2.0 − 2.6 V blanking, output clamping 3.5 − VP V 1997 Nov 25 note 8 11 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus SYMBOL I11 PARAMETER input current TDA4885 CONDITIONS V11 = 0.8 V; note 7 MIN. −3 TYP. MAX. −0.4 −0.1 −30 UNIT µA pin 5 grounded; note 7 −80 −60 V5 = −0.1 V; note 7 −250 −200 −100 µA µA − 0.7 1.0 V Video signal inputs (channel 1: pin 6; channel 2: pin 8; channel 3: pin 10) Vi(b-w)6, 8, 10 positive input signal referred to black VI(clamp)6, 8, 10 DC voltage during input clamping note 9 − 4 − V II6, 8, 10 DC input current no input clamping; VI6, 8, 10 = VI(clamp)6, 8, 10; Tamb = −20 to +70 °C 0.02 0.20 0.35 µA during input clamping; VI6, 8, 10 = VI(clamp)6, 8, 10 ±0.7 V ±110 ±150 ±190 µA f = 100 MHz; VI(DC)6, 8, 10 = VI(clamp)6, 8, 10 500 − − Ω − − 3 pF Zi6, 8, 10 magnitude of signal input impedance Ci6, 8, 10 input capacitance against ground Signal blanking αct(bl) crosstalk suppression from input to output during blanking control bit DISV = 1; f = 80 MHz 20 30 − dB control bit DISV = 1; f = 135 MHz 10 15 − dB td11(sig)l delay between blanking input (leading edge) and output signal blanking see Fig.8 − 55 − ns td11(sig)t delay between blanking input (trailing edge) and output signal blanking see Fig.8 − 25 − ns − 1 2 % − 4 − dB − 0 − dB 00H (minimum) − −28 − dB 3FH to 00H; note 12 − 0.0 0.5 dB Clipping (measured at signal outputs) ∆Vclipp offset during sync clipping VI6, 8, 10 = VI(clamp)6, 8, 10; related to nominal colour signal note 10; see Fig.3 Contrast control; see Fig.9 and note 11 dC ∆Gtrack 1997 Nov 25 colour signal related to nominal 3FH (maximum) colour signal 26H (nominal) tracking of output colour signals of channels 1, 2 and 3 12 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus SYMBOL PARAMETER TDA4885 CONDITIONS MIN. TYP. MAX. UNIT Fast blanking (pin 1) and OSD signal insertion (channel 1: pin 2; channel 2: pin 3; channel 3: pin 4); note 13 V1 V2, 3, 4 fast blanking input signal OSD input signal no video signal blanking, OSD signal insertion disabled 0 − 1.1 V video signal blanking, OSD signal insertion enabled 1.7 − VP − 1 V no internal OSD signal insertion 0 − 1.1 V internal OSD signal insertion 1.7 − VP − 1 V V1 > 1.7 V tf(FBL) fall time of colour signals (pins 30, 25 and 20) 90 to 10% amplitude; start of − fast blanking pulse at pin 1 with 1.2 ns/V; note 14; see Fig.10 − 10 ns tr(FBL) rise time of colour signals (pins 30, 25 and 20) 10 to 90% amplitude; end of − fast blanking pulse at pin 1 with 1.2 ns/V; note 14; see Fig.10 − 10 ns tr(OSD) rise time of OSD colour signals 10 to 90% amplitude; input pulse with 1.2 ns/V; see Fig.10 − − 4 ns tf(OSD) fall time of OSD colour signals 90 to 10% amplitude; input pulse with 1.2 ns/V; see Fig.10 − − 7 ns tg(CO) width of (negative going) OSD signal insertion glitch, leading edge identical pulses with 1.2 ns/V at − fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4); note 15; see Fig.10 − 6 ns tg(OC) width of (negative going) OSD signal insertion glitch, trailing edge identical pulses with 1.2 ns/V at − fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4); note 15; see Fig.10 − 6 ns dVOSD overshoot/undershoot of OSD colour signal related to actual OSD output pulse amplitude OSD input pulse (pins 2, 3 − and 4) with 1.2 ns/V; V1 > 1.7 V 13 20 % tover time of OSD signal overshoot exceeding 10% OSD input pulse (pins 2, 3 − and 4) with 1.2 ns/V; V1 > 1.7 V − 2 ns VOSD(max) maximum OSD colour signal maximum OSD contrast; 100 related to nominal colour signal maximum gain; pins 12, 13 and 14 connected to ground 125 150 % OSD contrast control; see Fig.11 and note 16 dOC 1997 Nov 25 OSD colour signal related to maximum OSD colour signal 00H (minimum) −14 −12 −10 dB 0FH (maximum) − 0 − dB 13 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus SYMBOL PARAMETER TDA4885 CONDITIONS MIN. TYP. MAX. UNIT Limiting (pin 17); see Fig.9 and note 17 V17(nom) input voltage V17(start) starting voltage for contrast and OSD contrast reduction V17(stop) stop voltage for contrast and OSD contrast reduction I17 maximum input current pin 17 open-circuit 4.7 5.0 5.3 V 4.2 4.5 4.8 V −32 dB below maximum colour signal (contrast setting 3FH) 1.5 2.0 2.5 V V17 = 0 V −1.0 −0.5 −0.1 µA 3FH (maximum) +25 +30 +35 % 10H (nominal) −2 0 +2 % 00H (minimum) −12 −10 −8 % −1.2 0 +1.2 % Brightness control; see Fig.12 and notes 18 and 19 ∆Vbl ∆VBT difference between black level and reference black level at signal outputs related to nominal colour signal difference of ∆Vbl between any two channels related to nominal colour signal Brightness blanking td11(br)l delay between blanking input at pin 11 (leading edge) and brightness blanking at signal outputs see Fig.8 − − 60 ns td11(br)t delay between blanking input at pin 11 (trailing edge) and brightness blanking at signal outputs see Fig.8 − − 60 ns 00H (minimum) −8 −7 −6 dB 3FH (maximum) − 0 − dB symmetrical modulation 1.0 − 3.0 V modulation feature not in use − − 0 V nominal: pins 12, 13 and 14 open-circuit 1.8 2.0 2.2 V 112 120 130 % Gain control; see Fig.13 and note 20 dG video signal related to video signal at maximum gain Gain modulation (channel 1: pin 12; channel 2: pin 13; channel 3: pin 14) V12, 13, 14 Gmod1, 2, 3 1997 Nov 25 input voltage gain modulation channels 1, 2 and 3 note 21; see Fig.14 pins 12, 13 and 14 grounded (modulation feature not in use) V12, 13, 14 = 1 V (maximum) 112 118 124 % V12, 13, 14 = 2 V − 100 − % V12, 13, 14 = 3 V (minimum) 76 82 88 % 14 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus SYMBOL PARAMETER TDA4885 CONDITIONS MIN. TYP. MAX. UNIT Pedestal blanking ∆V30, 25, 20PED difference of pedestal black level to video black level at nominal brightness at signal output pins related to nominal colour signal ∆V30, 25, 20PED(T) variation of ∆V30, 25, 20PED with temperature related to nominal colour signal note 22; see Fig.5 −18 −16 −14 % Tamb = −20 to +70 °C −0.8 0 +0.8 % Signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20) V30, 25, 20(b-w) nominal colour signal nominal contrast; maximum gain; pins 12, 13 and 14 grounded; VI(b-w) = 0.7 V; without load 2.5 2.8 3.1 V V30, 25, 20(max) maximum colour signal maximum contrast; maximum gain; pins 12, 13 and 14 grounded; VI(b-w) = 0.7 V; without load 4.0 4.5 5 V V30, 25, 20(min) switch-off voltage (minimum output voltage level) − 0.05 0.1 V V30, 25, 20(max) maximum output voltage level VP − 2 − VP − 1 V R30, 25, 20 output resistance − 80 − Ω I30, 25, 20 maximum source current −15 − − mA at arbitrary input signals, contrast, brightness and gain adjustments; without load I30, 25, 20M(source) peak source current during fast positive signal transients −40 − − mA I30, 25, 20M(sink) peak sink current during fast negative signal transients − − 20 mA S/N signal-to-noise ratio note 23 44 50 − dB D30, 25, 20(th) output thermal distortion note 24 − − 0.6 % Frequency response at signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20) ∆G30, 25, 20(f) amplification decrease by frequency response f = 135 MHz (small signal) − 1.2 3.0 dB tr(30, 25, 20) rise time of fast transients 10 to 90% amplitude; nominal colour signal; note 25 − 2.7 3 ns tf(30, 25, 20) fall time of fast transients 90 to 10% amplitude; nominal colour signal; note 25 − 3.9 4.3 ns dV30, 25, 20 over/undershoot of output signal pulse related to actual output pulse amplitude input rise/fall time = 1 ns; nominal colour signal − 5 10 % 1997 Nov 25 15 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus SYMBOL PARAMETER TDA4885 CONDITIONS MIN. TYP. MAX. UNIT Crosstalk at signal outputs (channel 1: pin 30; channel 2: pin 25; channel 3: pin 20) αct(tr) transient crosstalk suppression input rise/fall time = 1 ns; note 26 10 25 − dB αct(f) crosstalk suppression by frequency f = 50 MHz 25 30 − dB f = 100 MHz 10 20 − dB Internal feedback reference voltage; see Fig.15 and note 27 Vref(n) internal reference voltage for negative feedback polarity FFH; FPOL = 0 3.8 4.0 4.2 V 00H; FPOL = 0 5.6 5.8 6.1 V Vref(p) fixed internal reference voltage for positive feedback polarity FPOL = 1 0.6 0.7 0.8 V ∆Vref/∆T variation of Vref(n) and Vref(p) in the temperature range Tamb = −20 to +70 °C 0 − ±1.0 % ∆Vref/∆VP variation of Vref(n) and Vref(p) with supply voltage VP 7.6 V ≤ VP ≤ 8.8 V 0 − ±1.0 % External reference voltages (REF1: pin 32; REF2: pin 27; REF3: pin 22); see Fig.16 and note 28 V32, 27, 22 external reference voltage (equal to internal reference voltage with control bit FPOL = 0 ) FFH 3.8 4.0 4.2 V 00H 5.6 5.8 6.1 V ∆V32, 27, 22/∆T variation of V32, 27, 22 in the temperature range Tamb = −20 to +70 °C 0 − ±1.0 % ∆V32, 27, 22/∆VP variation of V32, 27, 22 with supply voltage VP 7.6 V ≤ VP ≤ 8.8 V 0 − ±1.0 % R32, 27, 22 output resistance − 90 − Ω I32, 27, 22 maximum sink current − − 400 µA I32, 27, 22 maximum source current − −330 −280 µA Output clamping, feedback inputs (channel 1: pin 31; channel 2: pin 26; channel 3: pin 21) I31, 26, 21(max) V30, 25, 20rbl(min) V30, 25, 20rbl(max) during output clamping; V11 > 3.5 V; V31, 26, 21 = 0.5 V −500 −100 −60 nA minimum reference black level PEDST = 0; V11 > 3.5 V 0.01 0.1 0.5 V minimum pedestal black level PEDST = 1; V11 > 3.5 V 0.01 0.1 0.5 V maximum reference black level PEDST = 0; V11 > 3.5 V 2.4 2.8 4 V maximum input current maximum pedestal black level PEDST = 1; V11 > 3.5 V 2.4 2.8 4 V ∆Vbl(CRT) black level variation at CRT note 29 0 40 200 mV ∆Vbl(lf) black level variation between clamping pulses related to nominal colour signal line frequency 60 kHz; 10% duty cycle − 0.1 0.5 % tW11 width of clamping pulse measured at V11 = 3 V; see Fig.8 1 − − µs td11(clamp)l delay between clamping input see Fig.8 at pin 11 (leading edge) and start of internal output clamping pulse − − 300 ns 1997 Nov 25 16 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus SYMBOL td11(clamp)t PARAMETER delay between clamping input at pin 11 (trailing edge) and end of internal output clamping pulse TDA4885 CONDITIONS see Fig.8 MIN. TYP. MAX. UNIT − − 60 ns I2C-bus inputs (pins 15 and 16) fSCL SCL clock frequency − − 100 kHz VIL LOW-level input voltage 0.0 − 1.5 V VIH HIGH-level input voltage 3.0 − 5.0 V IIL LOW-level input current VIL = 0 V − − −10 µA IIH HIGH-level input current VIH = 5 V − − −10 µA VOL LOW-level output voltage during acknowledge 0.0 − 0.4 V Iack output current at pin 15 during acknowledge VOL = 0.4 V 3.0 − 5.0 mA Vth(POR)(r) threshold for power-on reset on rising supply voltage − 1.5 2.0 V falling supply voltage − 3.5 − V threshold for power-on reset off rising supply voltage − − 7.0 V falling supply voltage − 1.5 − V Vth(POR)(f) Notes to the characteristics 1. Definition of levels (see Figs 3 to 5): Reference black level: this is the level to which the input level is clamped during the input clamping pulse (V5 > 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs: a) when the input is at black and the brightness setting is nominal (subaddress 01H = 10H) b) during output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 0. Video black level: this is the black level of the actual video. On the input it is still equal to the reference black level. On the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level unaltered . Pedestal black level: this is an ultra black level which deviates from reference black level by a fixed amount. It can be observed on the output during output blanking/clamping (V11 > 3.5 V) if control bit PEDST = 1. Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the internal black level storage capacitors if the supply voltage is less than VPSO. Blanking level: this level equals reference black (control bit PEDST = 0) or pedestal black (control bit PEDST = 1). 2. Explanation to black level adjustment: The actual blanking level on the output depends on the external feedback application. The loop will only function correctly if it is within the control range of V30, 25, 20rbl(min) to V30, 25, 20rbl(max). Note: changing control bit PEDST in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels). The three reference black levels are aligned correctly when they are made equal to the ‘extended cut-off levels’ of the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying a negative pulse to grid 1. 1997 Nov 25 17 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 3. Definition of output signals (see Fig.6): Colour signal: all positive voltages referred to black level at signal outputs. Nominal colour signal: colour signal with nominal input signal (0.7Vb-w), nominal contrast setting and maximum gain setting. Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the superposing of the brightness information (∆Vbl) and the colour signal. 4. The total supply current IP = I7 + I29 + I24 + I19 depends on the supply voltage with a factor of approximately 10 mA/V and varies in the temperature range of −20 to +70 °C by approximately ±10% (V30, 25, 20 = 0.7 V). 5. The channel supply current depends on the signal output current, the channel supply voltage and the signal output voltage. With Ipx = I29, 24, 19 at VP1, 2, 3 = 8 V and V30, 25, 20 = 0.7 V: mA mA I 29, 24, 19 ≈ I px + I 30, 25, 20 + 3.1 --------- × ( V P1, 2, 3 – 8 V ) – 2.5 --------- × ( V 30, 25, 20 – 0.7 V ) V V 6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and if control bit PEDST = 1 pedestal blanking). With a fast clamping pulse (transition between V5 = 1.2 to 3.5 V and vice versa in less than 75 ns/V) no blanking will occur during input clamping. For 75 ns/V < tr/f5 ≤ 280 ns/V the generation of the internal vertical blanking pulse is uncertain, for tr/f5 > 280 ns/V the internal blanking pulse will be generated. Pin 5 open-circuited will activate permanent input clamping and undefined blanking. 7. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or less. Feeding clamping/blanking pulses via a resistor of some kΩ protects the pin from negative voltages. 8. Pin 11 should be used for output clamping and/or blanking. Pin 11 open-circuited will activate permanent blanking and output clamping. 9. The DC voltage during input clamping is temperature dependent with a factor of approximately 0.5 V/100 °C (3VBE). 10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below input reference black level (see Fig.3). 11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 1.6% of contrast range). A 1 A 20 A 1 A 30 A 2 A 30 12. ∆G track = 20 × maximum of log --------- × --------- ; log --------- × --------- ; log --------- × --------- dB A A A A 10 10 A 20 A 3 2 3 Ax: colour signal output amplitude in channel x at any contrast setting. Ax0: colour signal output amplitude in channel x at nominal contrast and same gain setting. 13. When OSD fast blanking is active and V2, 3, 4 are HIGH (V1 > 1.7 V, V2, 3, 4 > 1.7 V) the OSD colour signals will be inserted in front of the gain potentiometers. This assures a correct grey scale of all video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via I2C-bus. 14. Typical pulse at fast blanking input (pin 1) and response at signal outputs (pins 30, 25 and 20) with nominal input signals at pins 6, 8 and 10. 15. Typical pulse at fast blanking input (pin 1) as well as OSD inputs (pins 2, 3 and 4) and response at signal outputs (pins 30, 25 and 20) during OSD fast blanking for maximum OSD contrast, maximum gain adjustment and pins 12, 13 and 14 grounded. Small internal threshold and delay differences between fast blanking and signal insertion might cause short signal distortion at begin and end of signal insertion (see Fig.10). 16. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution 6.7% of OSD contrast range). 1997 Nov 25 18 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 17. This pin can be used for beam current limiting or subcontrast setting. Both the video and OSD contrast are reduced simultaneously (see Figs 9 and 11). Because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 V or applied with a capacitor of some nF if not used. 18. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution 1.6% of brightness range). 19. The voltage difference between video black level and reference black level is related to the colour signal with nominal 0.7 V (peak-to-peak value) input signal, at nominal contrast (subaddress 02H = 26H) and for any gain setting. The voltage difference is proportional to the gain setting (grey scale tracking). The given values of ∆Vbl are valid only for video black levels higher than the signal output switch-off voltage V30, 25, 20(min). 20. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H (channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 1.6% of gain range). 21. The usage of the gain modulation capability results in a reduction of the overall voltage gain of the TDA4885 but gives enough room for positive and negative modulation. Only pins 12, 13 and 14 connected to ground makes it possible to reach the specified maximum video signals at pins 30, 25 and 20 (see Fig.14). By short-circuiting pins 12, 13 and 14 it is possible to assure that the relations between the video signals remain constant for any modulation (common gain modulation). 22. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative signal at the signal output pins. The reference black level which should correspond to the ‘extended cut-off voltage’ at the cathodes is about ∆V30, 25, 20PED higher (see Fig.5). The use of pedestal blanking with AC-coupled cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit. 23. The signal-to-noise ratio is calculated by the formula (range 1 to 135 MHz): peak-to-peak value of the nominal signal output voltage S ---- = 20 × log --------------------------------------------------------------------------------------------------------------------------------------------------- dB RMS value of the noise output voltage N 24. There might be short time smearing effects which have no thermal causes. The final amplitude will be reached some 10 ns after pulse step (amplitude differences of about 5%). For compensation methods see Section “Recommendations for building the application board” in Chapter “Test and application information”. 2 2 2 25. Ideal input rise/fall time of 0 ns; t r, out = t r, ideal + t r, in 26. Crosstalk between any two output pins: a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other two channels are capacitively coupled to ground (channel B). Gain setting to maximum (3FH). Contrast setting to nominal (26H) b) Output conditions: black level set to 1 V for each channel at signal outputs. Output signals are VA and VB respectively VA c) Transient crosstalk suppression: α ct(tr) = 20 × log ------- dB VB 27. Internal feedback reference voltage acts under I2C-bus control for control bit FPOL = 0; subaddress 07H (channel 1), 08H (channel 2) and 09H (channel 3; bit resolution 0.4% of voltage range). The internal feedback reference voltages can be measured at feedback inputs (pins 31, 26 and 21) during output clamping (V11 > 3.5 V) in closed feedback loop. The feedback loop remains operative at output levels between typically 0.1 to 2.8 V. The reference voltages are not influenced by the value of control bit PEDST. The levels of the internal feedback reference voltages depend on the individual adjustments via I2C-bus (values from 00H to FFH) and the selected feedback polarity (control bit FPOL = 0 or 1): a) Control bit FPOL = 0: rising values of the data bytes (subaddresses 07H, 08H and 09H), e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs (pins 30, 25 and 20) b) Control bit FPOL = 1: the internal feedback reference voltage remains constant. 1997 Nov 25 19 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 28. The external reference voltages act under I2C-bus control independent from control bit FPOL; subaddress 07H (REF1), 08H (REF2) and 09H (REF3; bit resolution 0.4% of voltage range). 29. Slow variations of video supply voltage VCRT will be suppressed at CRT cathode by the clamping feedback loop. A change of VCRT with 5 V leads to a specified change of the cathode voltage. handbook, full pagewidth input signals input video signal with syncs at pins 6, 8 and 10 input reference black level the syncs will be clipped to reference black level internally input clamping pulses at pin 5 blanking/output clamping pulses at pin 11 MHA344 The input video signals have to be on black level during input clamping. Fig.3 Input signals. 1997 Nov 25 20 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth blanking pulse, output clamping pulse at pin 11 blanking signal output signals pins 30, 25 and 20 (1) maximum gain setting, nominal contrast setting, maximum/nominal/minimum brightness setting (2) (3) video black levels at maximum brightness nominal brightness minimum brightness reference black level switch-off voltage ground (1) (2) maximum gain setting, maximum brightness setting, maximum/nominal/minimum contrast setting (3) video black level (maximum brightness) reference black level switch-off voltage ground maximum brightness setting, nominal contrast setting, maximum/minimum gain setting (1) (3) video black level (maximum brightness) reference black level switch-off voltage ground MHA345 (1) Maximum. (2) Nominal. (3) Minimum. Fig.4 Definition of levels, function of brightness setting, contrast setting, gain setting, no pedestal blanking (PEDST = 0). 1997 Nov 25 21 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 blanking pulse, handbook, full pagewidth output clamping pulse at pin 11 blanking signal output signals pins 30, 25 and 20 PEDST = 0 no pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting (1) (2) video black levels at maximum brightness minimum brightness reference black level switch-off voltage ground PEDST = 1 pedestal blanking maximum gain setting, nominal contrast setting, maximum/minimum brightness setting (1) (2) video black levels at maximum brightness minimum brightness reference black level pedestal black level switch-off voltage MHA346 ground (1) Maximum. (2) Minimum. Fig.5 Output signals without (PEDST = 0) and with pedestal blanking (PEDST = 1). 1997 Nov 25 22 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 signals handbook, output full pagewidth pins 30, 25 and 20 PEDST = 0 no pedestal blanking colour signals video signals maximum gain setting, nominal contrast setting, maximum/minimum brightness setting reference black level video black levels at maximum brightness minimum brightness MHA613 Fig.6 Definition of output signals. handbook, full pagewidth 3V trf5 ≤ 75 ns/V 1.4 V input pulses at pin 5 internal pulse for input clamping tdl5 tdt5 internal pulse for blanking MHA347 Fig.7 Timing of pulses at pin 5 and derived internal pulses. 1997 Nov 25 tdl5 23 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 3V blanking signal at pin 11 tW11 1.4 V td11(cl)l td11(cl)t internal output clamping pulse 50% td11(sig)l blanking of output signal at pins 30, 25 and 20 at nominal brightness setting td11(sig)t colour signal 50% reference black level td11(br)t td11(br)l blanking of maximum brightness at pins 30, 25 and 20 brightness offset 50% reference black level MHA348 Fig.8 Delay between blanking input and output signal blanking, brightness blanking and output clamping. 1997 Nov 25 24 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 MHA349 handbook, full pagewidth 4 colour signal amplitude related to nominal colour signal amplitude (dB) (1) 0 (2) (3) −28 00H 10H 20H 26H (1) No contrast reduction by limiting. (2) Partial contrast reduction by limiting. (3) Full contrast reduction by limiting. Fig.9 Contrast control characteristic with limiting. 1997 Nov 25 25 3FH 30H contrast control data byte Philips Semiconductors Product specification 150 MHz video controller with I2C-bus handbook, full pagewidth tf(FBL) TDA4885 tr(FBL) 90% 90% 10% 10% reference black level MHA932 a. Video signal with fast blanking at signal outputs (pins 30, 25 and 20). handbook, full pagewidth tf(OSD) tr(OSD) 90% 90% 10% 10% reference black level MHA933 b. OSD signal without video signal at signal outputs (pins 30, 25 and 20). handbook, full pagewidth dVOSD tg(CO) tg(OC) reference black level MHA934 c. Video signal with OSD signal insertion at signal outputs (pins 30, 25 and 20). Identical input pulse at pin 1 (fast blanking) and pins 2, 3 and 4 (OSD signal). Fig.10 OSD insertion. 1997 Nov 25 26 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus handbook, full pagewidth MHA351 maximum colour signal amplitude 160 OSD signal amplitude related to nominal colour signal amplitude (%) TDA4885 maximum OSD signal amplitude 125 nominal colour signal amplitude 100 (1) (2) 30 (3) 00H 0FH OSD contrast control data byte (1) No OSD contrast reduction by limiting. (2) Partial OSD contrast reduction by limiting. (3) Full OSD contrast reduction by limiting. Fig.11 OSD contrast control characteristic with limiting. MHA352 handbook, full pagewidth 30 difference of video black level and reference black level related to nominal colour signal amplitude (1) (%) 0 (2) −10 00H 10H 20H 30H brightness control data byte (1) Nominal adjustment. (2) Nominal brightness reference black level. Fig.12 Brightness control characteristic. 1997 Nov 25 27 3FH Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 MHA353 handbook, full pagewidth 1 video signal gain related to maximum video signal gain 0.45 0 00H 10H 20H 3FH 30H gain control data byte Fig.13 Gain control characteristic. handbook, full pagewidth MHA354 1 (1) video signal gain related to 0.83 maximum video signal gain (2) (3) 0.68 (4) 0.45 0.31 0 00H 10H 20H 3FH 30H gain control data byte (1) (2) (3) (4) Pin 12, 13 or 14 grounded. 1 V at pin 12, 13 or 14. Open-circuit pin 12, 13 or 14. 3 V at pin 12, 13 or 14. Fig.14 Gain modulation. 1997 Nov 25 28 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus handbook, full pagewidth TDA4885 MHA355 5.8 (1) internal feedback reference voltage (V) 4 (2) 0.7 0 00H 20H 40H 60H 80H A0H C0H E0H FFH feedback reference data byte (1) Control bit FPOL = 0. (2) Control bit FPOL = 1. Fig.15 Internal feedback reference voltages. handbook, full pagewidth MHA356 5.8 (1) external reference voltage (V) 4 0 00H 20H 40H 60H 80H A0H (1) Control bit FPOL = 0 or 1. Fig.16 External feedback reference voltages. 1997 Nov 25 29 C0H E0H FFH feedback reference data byte Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 11 I2C-BUS PROTOCOL Table 1 Slave address A6(1) A5(1) A4(1) A3(1) A2(1) A1(1) A0(1) W(2) 1 0 0 0 1 0 0 0 Notes 1. Address bit. 2. Write bit. Table 2 Slave receiver format S(1) SLAVE ADDRESS A(2) SUBADDRESS A(3) DATA BYTE A(4) P(5) Notes 1. START condition. 2. A = acknowledge. 3. All subaddresses within the range 00H to 09H are automatically incremented. The subaddress counter wraps around from 09H to 00H. The subaddress 0FH is reserved for test purposes under production. Do not use it. Subaddresses outside the range 00H to 0FH are acknowledged by the device but neither auto-increment nor any other internal operation takes place. 4. N data bytes with auto-increment of subaddresses. 5. STOP condition. 1997 Nov 25 30 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus Table 3 TDA4885 Subaddress byte and data byte format FUNCTION SUBADDRESS DATA BYTE(1) D6(2) D5(2) D4(2) D3(2) 00H X(4) X(4) X(4) X(4) FPOL DISV DISO PEDST Brightness control 01H X(4) X(4) A15 A14 A13 A12 A11 A10 10H Contrast control 02H X(4) X(4) A25 A24 A23 A22 A21 A20 26H 03H X(4) X(4) X(4) X(4) A33 A32 A31 A30 0FH Gain control channel 1 04H X(4) X(4) A45 A44 A43 A42 A41 A40 3FH Gain control channel 2 05H X(4) X(4) A55 A54 A53 A52 A51 A50 3FH Gain control channel 3 06H X(4) X(4) A65 A64 A63 A62 A61 A60 3FH Black level reference channel 1 07H A77 A76 A75 A74 A73 A72 A71 A70 − Black level reference channel 2 08H A87 A86 A85 A84 A83 A82 A81 A80 − Black level reference channel 3 09H A97 A96 A95 A94 A93 A92 A91 A90 − X(4) X(4) X(4) 0 0 0 Control register OSD contrast control D2(2) D1(2) D0(2) NOMINAL VALUE(3) D7(2) − − 0AH to 0EH not used Reserved (note 5) 0FH X(4) X(4) − Notes 1. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0). 2. Data bit. 3. After power-on reset control and test register are reset to logic 0 and all alignment registers are set to logic 0 (minimum). 4. X means don’t care but for software compatibility with other video ICs with the same slave address, they are preferably set to logic 0. 5. For production tests only. Table 4 Control register BIT FUNCTION PEDST = 0 no pedestal blanking PEDST = 1 pedestal blanking enabled DISO = 0 OSD signals enabled DISO = 1 OSD signals disabled DISV = 0 video signals enabled DISV = 1 video signals disabled FPOL = 0 negative feedback polarity FPOL = 1 positive feedback polarity 1997 Nov 25 31 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus handbook, full pagewidth TDA4885 START LOAD PRESET CONTROL BITS load from program ROM code or EEPROM FPOL PEDST DISV = 1 DISO = 1 LOAD FACTORY SETTINGS GAIN (CHANNEL 1, 2, 3) FEEDBACK REFERENCES (CHANNEL 1, 2, 3) load from EEPROM LOAD USER PRESET VALUES CONTRAST BRIGHTNESS OSD CONTRAST load from EEPROM no DEFLECTION CONTROL IC LOCKED yes DISV = 0 DISO = 0 DISPLAY NEW MODE (1) DISO = 1 USER INPUT no yes DISO = 0 RESPONSE TO USER INPUTS (CONTRAST, BRIGHTNESS, OSD CONTRAST) DISO = 1 (1) Only synchronized video should be displayed. Each new mode can be displayed by OSD. It is recommended to synchronize data transmission (brightness, contrast and OSD contrast) with vertical blanking pulse. DEFLECTION CONTROL IC LOCKED no MHA614 yes Fig.17 I2C-bus control flow. 1997 Nov 25 DISV = 1 32 1 SYMBOL AND DESCRIPTION FBL; fast blanking input for OSD insertion CHARACTERISTIC WAVEFORM open-circuit base EQUIVALENT CIRCUIT 50 µA 5V 50 µA 50 µA 50 µA VP signal blanking 0V MHA653 OSD1 blanking OSD2 blanking OSD3 blanking 1 1 kΩ MHA928 2 OSD1; OSD input channel 1 V2 < VP − 1 V: open-circuit base 5V VP 50 µA 0V MHA653 33 V2 = VP: I2 = 85 to 210 µA test current signal blanking VP 2 1 kΩ Philips Semiconductors PIN 150 MHz video controller with I2C-bus 1997 Nov 25 12 INTERNAL CIRCUITRY disable OSD 1 kΩ FBL MHA929 Product specification TDA4885 OSD2; OSD input channel 2 CHARACTERISTIC WAVEFORM V3 < VP − 1 V: open-circuit base EQUIVALENT CIRCUIT 5V VP 50 µA 0V MHA653 test current V3 = VP: I3 = 80 to 280 µA signal blanking VP 3 1 kΩ disable OSD 1 kΩ FBL 4 OSD3; OSD input channel 3 V4 < VP − 1 V: open-circuit base 5V MHA930 VP 34 50 µA 0V Philips Semiconductors 3 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN MHA653 V4 = VP: I4 = 80 to 280 µA test current signal blanking VP 4 1 kΩ disable OSD 1 kΩ FBL MHA931 Product specification TDA4885 CLI; vertical blanking input (input clamping) CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT V5 > 0.2 V: open-circuit base 5V 2.5 V 0V 2VBE VP 6 kΩ 26 µA 10 kΩ MHA651 3 V + VBE V5 ≤ 0.2 V: source current rising with decreasing voltage VP 1 kΩ 5 10 kΩ power on/down MHA619 6 35 VI1; signal input channel 1 outside clamping pulse: open-circuit base with base current compensation 4.7 V black shoulder VP VP video signal sync during clamping: I6 = −150 to +150 µA MIRROR 1:1 Philips Semiconductors 5 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN 4V 3.7 V 6 input clamping (pin 5) MHA652 700 Ω 1.8 V + VBE signal 150 µA 240 µA 220 µA 0 µA MHA620 20 mA 7 MHA621 TDA4885 VP; supply voltage Product specification 7 VI2; signal input channel 2 CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation WAVEFORM EQUIVALENT CIRCUIT 4.7 V MIRROR 1:1 black shoulder VP VP video signal sync during clamping: I6 = −150 to +150 µA 4V 3.7 V 8 input clamping (pin 5) MHA652 700 Ω 1.8 V + VBE signal 150 µA 240 µA 220 µA 0 µA MHA622 9 36 GND; ground 9 Philips Semiconductors 8 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN MHA623 10 VI3; signal input channel 3 outside clamping pulse: open-circuit base with base current compensation 4.7 V VP VP video signal sync during clamping: I6 = −150 to +150 µA MIRROR 1:1 black shoulder 4V 3.7 V 10 input clamping (pin 5) MHA652 700 Ω 1.8 V + VBE 240 µA 220 µA 0 µA MHA624 TDA4885 150 µA Product specification signal HFB; horizontal flyback input (output clamping, blanking) CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT V11 > 0.2 V: open-circuit base 5V 2VBE VP 10 kΩ 6 kΩ 0V MHA649 V11 ≤ 0.2 V: source current rising with decreasing voltage VP 3 V + VBE 27 µA 27 µA clamping blanking 12 kΩ 1.7 V 10 kΩ 1 kΩ 11 power on/down 12 GM1; gain modulation input channel 1 R12 = 20 kΩ; open-circuit voltage V12 = 2.0 V 3V 2V 1V 37 MHA650 MHA625 5.5 V 27.5 kΩ 2.2 V Philips Semiconductors 11 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN VP 10 kΩ 12 15.7 kΩ MHA626 13 GM2; gain modulation input channel 2 R13 = 20 kΩ; open-circuit voltage V13 = 2.0 V 3V 2V 1V MHA650 5.5 V 27.5 kΩ 2.2 V 10 kΩ 15.7 kΩ MHA627 TDA4885 13 Product specification VP CHARACTERISTIC GM3; gain modulation input channel 3 R14 = 20 kΩ; open-circuit voltage V14 = 2.0 V WAVEFORM EQUIVALENT CIRCUIT 3V 2V 1V MHA650 5.5 V 27.5 kΩ 2.2 V VP 10 kΩ 14 15.7 kΩ MHA628 15 SDA; I2C-bus serial data input/output no acknowledge; open-circuit base during acknowledge: I15 = 4 mA 5V 3 µA 70 µA 19 µA 0V MHA647 38 10 kΩ 2.46 V + VBE 15 Philips Semiconductors 14 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN MHA629 acknowledge 16 SCL; I2C-bus clock input open-circuit base 5V 19 µA 0V 10 kΩ MHA648 16 MHA630 TDA4885 Product specification 2.46 V + VBE LIM; beam current limiting input CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT open-circuit voltage V17 = 5.0 V VP 17 21 µA 1 kΩ 5.0 V V17 < 4.5 V: open-circuit base 10 kΩ MHA631 18 19 GND3; ground channel 3 39 VP3; supply voltage channel 3 18 MHA632 I19 = 40 mA 19 Philips Semiconductors 17 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN MHA633 Product specification TDA4885 VO3; signal output channel 3 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT reference black level 0.1 to 2.8 V MHA655 VP 500 Ω VP brightness 20 8 kΩ 80 Ω 1.5 kΩ reference black level during output clamping 3.5 pF control bit PEDST = 0 MHA634 pedestal black level 0.1 to 2.8 V MHA656 brightness pedestal black level during output clamping Philips Semiconductors 20 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN 40 control bit PEDST = 1 21 FB3; feedback input channel 3 open-circuit base feedback reference 5.8 to 4 V VP 10 µA PEDST = 0 21 10 µA 1 kΩ 15 kΩ Vs1 PEDST = 1 15 kΩ Vs2 MHA654 1 kΩ 1 kΩ control bit FPOL = 0 MHA635 0.7 V 5.8 to 4 V PEDST = 0 feedback reference 0.7 V MHA660 control bit FPOL = 1 TDA4885 DC coupling; Vs1 = 0 V; Vs2 = 1 V (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V (control bit FPOL = 1) Product specification PEDST = 1 REF3; reference voltage channel 3 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT −300 to +300 µA VP 22 300 µA 15 µA 170 Ω 5.8 to 4 V 30 µA 7.5 µA MHA636 23 41 24 GND2; ground channel 2 VP2; supply voltage channel 2 23 MHA637 I24 = 40 mA 24 Philips Semiconductors 22 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN MHA638 Product specification TDA4885 VO2; signal output channel 2 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT reference black level 0.1 to 2.8 V MHA655 VP 500 Ω VP brightness 25 8 kΩ 80 Ω 1.5 kΩ reference black level during output clamping 3.5 pF control bit PEDST = 0 MHA639 pedestal black level 0.1 to 2.8 V MHA656 brightness pedestal black level during output clamping Philips Semiconductors 25 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN 42 control bit PEDST = 1 26 FB2; feedback input channel 2 open-circuit base feedback reference 5.8 to 4 V VP 10 µA PEDST = 0 26 10 µA 1 kΩ 15 kΩ Vs1 PEDST = 1 15 kΩ Vs2 MHA654 1 kΩ 1 kΩ control bit FPOL = 0 MHA640 0.7 V 5.8 to 4 V PEDST = 0 feedback reference 0.7 V MHA660 control bit FPOL = 1 TDA4885 DC coupling; Vs1 = 0 V; Vs2 = 1 V (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V (control bit FPOL = 1) Product specification PEDST = 1 REF2; reference voltage channel 2 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT −300 to +300 µA VP 27 300 µA 15 µA 170 Ω 5.8 to 4 V 30 µA 7.5 µA MHA641 28 43 29 GND1; ground channel 1 VP1; supply voltage channel 1 28 MHA642 I29 = 40 mA 29 Philips Semiconductors 27 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN MHA643 Product specification TDA4885 VO1; signal output channel 1 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT reference black level 0.1 to 2.8 V MHA655 VP 500 Ω VP brightness 30 8 kΩ 80 Ω 1.5 kΩ reference black level during output clamping 3.5 pF control bit PEDST = 0 MHA644 pedestal black level 0.1 to 2.8 V MHA656 brightness pedestal black level during output clamping Philips Semiconductors 30 SYMBOL AND DESCRIPTION 150 MHz video controller with I2C-bus 1997 Nov 25 PIN 44 control bit PEDST = 1 31 FB1; feedback input channel 1 open-circuit base feedback reference 5.8 to 4 V VP 10 µA PEDST = 0 31 10 µA 1 kΩ 15 kΩ Vs1 PEDST = 1 15 kΩ Vs2 MHA654 1 kΩ 1 kΩ control bit FPOL = 0 MHA645 0.7 V 5.8 to 4 V PEDST = 0 feedback reference 0.7 V MHA660 control bit FPOL = 1 TDA4885 DC coupling; Vs1 = 0 V; Vs2 = 1 V (control bit FPOL = 0) AC coupling; Vs1 = 1 V; Vs2 = 0 V (control bit FPOL = 1) Product specification PEDST = 1 REF1; reference voltage channel 1 CHARACTERISTIC WAVEFORM EQUIVALENT CIRCUIT −300 to +300 µA VP 32 300 µA 15 µA 170 Ω 5.8 to 4 V 30 µA 7.5 µA MHA646 Philips Semiconductors 32 SYMBOL AND DESCRIPTION 45 150 MHz video controller with I2C-bus 1997 Nov 25 PIN Product specification TDA4885 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 13 TEST AND APPLICATION INFORMATION handbook, full pagewidth fast blanking OSD inputs input clamping vertical blanking signal inputs 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 n.c. VCRT = 90 V to cathode VCRT = 70 V BLACK LEVEL RESTORATION to cathode TDA4885 output clamping blanking 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCRT = 90 V n.c. to cathode GND beam current limiting; subcontrast setting I2C-BUS VP = 8 V MHA927 Fig.18 Basic application for different output stages with DC coupling (FPOL = 0) or AC coupling (FPOL = 1). 1997 Nov 25 46 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 13.1 The beam current limiting pin is fed to the 10-pin main connector without any special application and should be connected to the 5 V supply if not used. Test application For high frequency measurements a special test application and printed-circuit board with only a few external components is built. Figure 19 shows the test application circuit and Figs 20 and 21 the layout of the double sided printed board. Most components are of SMD type. Short HF loops and minimum crosstalk between the channels and between signal inputs and outputs are achieved by properly shaped ground areas. DC supply voltage VP with a series resistor of 5.6 Ω can be measured directly at pin 7 via a resistor of 1 kΩ (VP sense). The supply voltage for the signal channels is fed to VPX separately and connected to pins 19, 24 and 29 with decoupling resistors of 5.6 Ω. The supply voltage VP1 (pin 29) can be measured via 1 kΩ at pin VP1 sense. The HF input signal can be fed to the subclick connectors VI1, VI2 and VI3 by a 50 Ω line. The line is then terminated by a 50 Ω resistor on the board. In channel 3 (pin 10) the HF input signal can be measured (probe socket). All supply voltages are filtered near to their pins with 150 pF and 100 nF SMD capacitors and low impedance 0.47 µF/63 V electrolytic capacitors. For operation without input clamping the DC bias can be provided by VINDC if a short-circuit at J1, J2 and J3 is made. The signal outputs are loaded with 10 kΩ and 3 pF to ground and are connected to a probe socket. With a probe capacitance of 2 pF the total capacitive load is 5 pF. OSD input signals (subclick: OSD1, OSD2, OSD3, FBL) and blanking/clamping inputs (subclick: CLI, HFB) are terminated with 50 Ω on the board. The feedback inputs are connected to the voltage outputs with a 0 Ω resistor (short circuit; RFB1) and via 10 kΩ (RFB2) connected to the pin VFBDC. The blanking level can be adjusted with a variation of RFB1, RFB2 and VFBDC but the resistive output load will be changed. The blanking level is: RFB1 RFB1 U outbl = 1 + ---------------- × 0.7 V – ---------------- × VFBDC RFB2 RFB2 The gain modulation input GM (subclick) can be connected to the three inputs by the jumpers J8 and J4, J5 and J6. With jumper J7 pins 12, 13 and 14 can be connected to ground (no gain reduction). There is a separate 4-pin connector for the I2C-bus controller, SDA and SCL have 10 kΩ pull up resistors to 5 V digital supply. 1997 Nov 25 TDA4885 The reference outputs are connected to solder pins. 47 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 1 kΩ handbook, full pagewidth 5.6 Ω FBL 50 Ω OSD1 50 Ω OSD2 50 Ω FBL OSD1 OSD2 1 32 2 31 3 30 4 29 REF1 FB1 VO1 VO1 1 kΩ channel 1 OSD3 OSD3 50 Ω CLI CLI 10 nF 50 Ω VI1 VI1 50 Ω 150 pF 10 nF VI2 50 Ω 150 pF 10 nF VP J1 0.47 µF (63 V) 100 nF 6 27 100 pF VI2 7 26 8 25 5 kΩ TDA4885 GND 9 J2 VI3 REF2 solder pin 24 10 23 11 22 12 21 13 20 14 19 15 18 10 kΩ FB2 VO2 RFB2 10 kΩ RFB1 channel 2 VO2 VP2 150 pF GND2 100 nF 10 kΩ 3 pF 0.47 µF (63 V) 5.6 Ω 5 kΩ probe HFB J3 HFB 28 5.6 Ω GND1 5 kΩ VI3 50 Ω 150 pF 5 VP1 GM1 50 Ω J4 GM2 REF3 FB3 VO3 channel 3 VO3 J5 J7 GM J8 GM3 VP3 VPX J6 VP1 sense SDA GND3 VFBDC VP sense 10 kΩ SCL SDA 5V 16 17 VP LIM GND 10 kΩ VINDC SCL LIM 5V MHA657 Fig.19 Test board. 1997 Nov 25 48 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 76.20 116.84 OSD3 OSD2 OSD1 FBL 5.6 Ω CLI 100 nF 150 pF J1 MP 10 kΩ 10 kΩ 3.3 pF MP 10 kΩ 10 kΩ 3.3 pF MP 10 kΩ 10 kΩ 3.3 pF VI1 J2 VI2 J3 1 kΩ IC1 0.47 µF VI3 10 kΩ 0.47 µF VO1 JP TP 10 kΩ 0.47 µF 10 kΩ 0.47 µF VO2 TP TP SDA VP GND SCL J6 I2C-bus VO3 J4 J7 J8 TP J5 GM HFB MHA658 Fig.20 Component layout and printed-circuit board; side A (for side B see Fig.21). 1997 Nov 25 49 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 handbook, full pagewidth 76.20 116.84 50 Ω 50 Ω 50 Ω 50 Ω 50 Ω 1 kΩ 5.6 Ω 5.6 Ω 5.6 Ω 150 pF 100 nF 100 nF 100 nF 150 pF 150 pF 100 nF 5 kΩ 10 nF 150 pF 5 kΩ 10 nF 150 pF 5 kΩ 10 nF 150 pF 50 Ω 50 Ω 50 Ω 150 pF 10 kΩ 50 Ω 10 kΩ MHA659 Fig.21 Component layout and printed-circuit board; side B (for side A see Fig.20). 1997 Nov 25 50 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus 13.2 Recommendations for building the application board • General – Double-sided board – Short HF loops by large ground plane on the rear – SMD components with minimum parasitics. • Voltage outputs – Capacitive loads as small as possible – Be aware of internal output resistance (80 Ω). • Supply voltages – Capacitors as near as possible to the pins – Use electrolytic capacitors with small serial resistance and inductance. • Smearing – Additional peaking circuit at emitter of driver transistor of cascode stage (time constant approximately 100 ns). 1997 Nov 25 51 TDA4885 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus TDA4885 14 PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1 ME seating plane D A2 A A1 L c e Z (e 1) w M b1 MH b 17 32 pin 1 index E 1 16 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.8 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 1.778 10.16 3.2 2.8 10.7 10.2 12.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT232-1 1997 Nov 25 EUROPEAN PROJECTION 52 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 15 SOLDERING 15.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 15.2 TDA4885 Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Nov 25 53 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus NOTES 1997 Nov 25 54 TDA4885 Philips Semiconductors Product specification 150 MHz video controller with I2C-bus NOTES 1997 Nov 25 55 TDA4885 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA56 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/02/pp56 Date of release: 1997 Nov 25 Document order number: 9397 750 02705