NSC DM74LS165WM

DM54LS165/DM74LS165 8-Bit Parallel
In/Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs,
which are enabled by a low level at the shift/load input.
These registers also feature gated clock inputs and complementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the load input high enables
the other clock input. The clock-inhibit input should be
changed to the high level only while the clock input is high.
Parallel loading is inhibited as long as the load input is high.
Connection Diagram
Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial
inputs.
Features
Y
Y
Y
Y
Y
Y
Complementary outputs
Direct overriding (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Typical frequency 35 MHz
Typical power dissipation 105 mW
Dual-In-Line Package
TL/F/6399 – 1
Order Number DM54LS165J, DM54LS165W, DM74LS165WM or DM74LS165N
See NS Package Number J16A, M16B, N16E or W16A
Function Table
Inputs
Shift/
Load
Clock
Inhibit
L
H
H
H
H
X
L
L
L
H
Clock
Serial
X
L
X
X
H
L
X
u
u
X
Internal
Outputs
Parallel
A...H
QA
QB
a...h
X
X
X
X
a
QA0
H
L
QA0
b
QB0
QAn
QAn
QB0
Output
QH
h
QH0
QGn
QGn
QH0
H e High Level (steady state), L e Low Level (steady state)
X e Don’t Care (any input, including transitions)
u e Transition from low-to-high level
a...h e The level of steady-state input at inputs A through H, respectively.
QA0, QB0, QH0 e The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established.
QAn, QGn e The level of QA or QG, respectively, before the most recent
transition of the clock.
u
C1995 National Semiconductor Corporation
TL/F/6399
RRD-B30M105/Printed in U. S. A.
DM54LS165/DM74LS165 8-Bit Parallel In/Serial Output Shift Registers
May 1992
Absolute Maximum Ratings
(Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
DM54LS
DM74LS
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54LS165
Parameter
DM74LS165
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
mA
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
b 0.4
b 0.4
IOL
Low Level Output Current
4
8
mA
fCLK
Clock Frequency (Note 1)
30
0
25
MHz
fCLK
Clock Frequency (Note 2)
0
20
MHz
tW
Pulse Width
(Note 2)
Clock
18
25
Load
15
15
Setup Time
(Note 6)
Parallel
10
10
Serial
10
20
Enable
10
30
Shift
10
45
tSU
2
tH
Hold Time (Note 6)
TA
Free Air Operating Temperature
5
Electrical Characteristics
Symbol
Parameter
125
Conditions
VOH
High Level Output
Voltage
VCC e Min, II e b18 mA
VCC e Min, IOH e Max
VIL e Max, VIH e Min
Low Level Output
Voltage
VCC e Min, IOL e Max
VIL e Max, VIH e Min
IIL
IOS
ICC
Note
Note
Note
Note
Note
4.5V,
Note
ns
ns
0
Min
DM54
2.5
DM74
2.7
70
Typ
(Note 3)
§C
VCC e Max, VI e 7V (DM74)
VI e 10V (DM54)
High Level Input
Current
Units
V
V
0.4
DM74
Input Current @ Max
Input Voltage
Max
b 1.5
3.4
DM54
IOL e 4 mA, VCC e Min
IIH
ns
over recommended operating free air temperature range (unless otherwise noted)
Input Clamp Voltage
II
V
0
b 55
VI
VOL
2
0.35
0.5
0.25
0.4
Shift/Load
0.3
Others
0.1
VCC e Max
VI e 2.7V
Shift/Load
60
Others
20
Low Level Input
Current
VCC e Max
VI e 0.4V
Shift/Load
b 1.2
Others
b 0.4
Short Circuit
Output Current
VCC e Max
(Note 4)
DM54
b 20
b 100
DM74
b 20
b 100
Supply Current
VCC e Max (Note 5)
21
36
V
mA
mA
mA
mA
mA
1: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V
2: CL e 50 pF, RL e 2 kX, TA e 25§ C and VCC e 5V
3: All typicals are at VCC e 5V, TA e 25§ C.
4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
5: With all outputs open, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the CLOCK input, ICC is measured first with the parallel inputs at
then again grounded.
6: TA e 25§ C and VCC e 5V.
2
Switching Characteristics
at VCC e 5V and TA e 25§ C
DM54LS
Symbol
Parameter
From (Input)
To (Output)
CL e 15 pF
Min
Max
25
DM74LS
DM74LS
CL e 15 pF
RL e 2 kX
CL e 50 pF
Min
Max
25
Min
Units
Max
fMAX
Maximum Clock Frequency
20
tPLH
Propagation Delay Time
Low to High Level Output
Load to
Any Q
MHz
30
35
37
ns
tPHL
Propagation Delay Time
High to Low Level Output
Load to
Any Q
30
35
42
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clock to
Any Q
30
40
42
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Any Q
30
40
47
ns
tPLH
Propagation Delay Time
Low to High Level Output
H
to QH
20
25
27
ns
tPHL
Propagation Delay Time
High to Low Level Output
H
to QH
30
30
37
ns
tPLH
Propagation Delay Time
Low to High Level Output
H
to QH
30
30
32
ns
tPHL
Propagation Delay Time
High to Low Level Output
H
to QH
25
25
32
ns
Timing Diagram
Typical Shift, Load, and Inhibit Sequences
TL/F/6399 – 3
3
TL/F/6399 – 2
Logic Diagram
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS165J
NS Package Number J16A
16-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS165WM
NS Package Number M16B
5
DM54LS165/DM74LS165 8-Bit Parallel In/Serial Output Shift Registers
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS165N
NS Package Number N16E
16-Lead Ceramic Flat Package (W)
Order Number DM54LS165W
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.