PRELIMINARY CY2283 Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs Features • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium® /II, Cyrix 6x86, and AMD K6 processor-based motherboards — Four CPU clocks at 2.5V or 3.3V — Twelve 3.3V SDRAM clocks[1] — Five synchronous PCI clocks, one free-running — One 3.3V 48 MHz USB clock — One 3.3V Ref. clock at 14.318 MHz — Two AGP clocks at 3.3V • Support for ALI (-1 option) and VIA (-2 option) • I2C™ Serial Configuration Interface • Full EMI control with factory-EPROM programmable output drive and slew rate • Factory-EPROM programmable CPU clock frequencies for custom configurations • Power-down, CPU stop, and PCI stop pins • Available in space-saving 48-pin SSOP package SDRAM outputs in place of the CY2283 and can be placed in close proximity to the SDRAM modules. The CY2283 possesses power-down, CPU stop, and PCI stop pins for power management control. These inputs are multiplexed with SDRAM clock outputs, and are selected when the MODE pin is driven LOW. Additionally, the signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2283 outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control. CY2283 Selector Guide Functional Description The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix, or AMD processor-based PCs using the ALI Aladdin V (-1 option) or VIA MVP3 (-2 option) chipset. The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI clocks is free-running. Additionally, the part outputs twelve 3.3V SDRAM clocks[1], one 3.3V USB clock at 48 MHz, and one 3.3V reference clock at 14.318 MHz. Finally, the part outputs two AGP clocks running at 66.66 MHz or 60 MHz. The CY2283 has the flexibility to work as either a one-chip or as part of a two-chip clocking solution. In 100-MHz board designs based on the ALI Aladdin V chipset, it is recommended that the CY2283 be used with an external SDRAM buffer solution such as the CY2318NZ or CY2314NZ. In this configuration the SDRAM outputs on the CY2283 must be either turned off using I2C or left floating. The CY231xNZ family provides the Clock Outputs -1 (ALI V) -2 (VIA MVP3) CPU (66.6, 75, 83.3, 100MHz) 4 4 SDRAM 12 PCI (30, 33.3 MHz) 5[2] 1 1 AGP (66.6, 60MHz) 2 2 Ref. (14.318 MHz) CPU-PCI delay In phase with CPU Pin Configuration (48 SSOP) 14.318 MHz OSC. AVDD VSS XTALIN 1 2 3 4 XTALOUT VDDQ3 5 6 PCICLK_F 7 8 9 10 11 12 REF0 STOP LOGIC CPU PLL CPUCLK [0-3] SDRAM5/PWR_DWN SDRAM [0-4],[8-11] EPROM SDRAM6/CPU_STOP MODE Delay (-2 option) SDRAM7/PCI_STOP SYS PLL /1, /1.25, /1.5 AGP STOP LOGIC /2 Cypress Semiconductor Corporation PCICLK1 PCICLK2 PCICLK3 AGP0 VDDQ3 SDRAM11 SDRAM10 PCI [0-3] VDDQ3 SDRAM9 PCICLK_F SERIAL INTERFACE CONTROL LOGIC PCICLK0 VSS AGP1 VSS Delay (-1 option) SDATA In phase with PCI Notes: 1. SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the ALI V chipset, an external CY231xNZ buffer should be used. 2. One free-running PCI clock VDDCPU SCLK 1 2.5−5.5 ns AGP clock REF0 (14.318 MHz) SEL0 SEL1 1 2.5−5.5 ns SDRAM8 VSS USBCLK SDATA SCLK • 3901 North First Street • San Jose • 48 47 46 45 44 VDDQ3 USBCLK SEL1 VSS CPUCLK0 43 42 41 CPUCLK1 VDDCPU 40 39 38 CPUCLK3 14 15 37 36 35 34 SDRAM1 VDDQ3 SDRAM2 16 17 18 33 32 31 19 20 21 22 23 24 30 29 28 27 26 25 13 CY2283-1,-2 XTALOUT 12 5[2] USB (48MHz) Logic Block Diagram XTALIN [1] CA 95134 CPUCLK2 VSS SDRAM0 SDRAM3 VSS SDRAM4 SDRAM5/PWR_DWN VDDQ3 SDRAM6/CPU_STOP SDRAM7/PCI_STOP VSS SEL0 MODE • 408-943-2600 October 12, 1998 PRELIMINARY CY2283 Pin Summary Name Pins Description VDDQ3 6, 14, 19, 30, 36, 48 3.3V Digital voltage supply VDDCPU 42 CPU Digital voltage supply, 2.5V or 3.3V AVDD 1 Analog voltage supply, 3.3V VSS 3, 9, 16, 22, 27, 33, 39, 45 Ground 4 Reference crystal input XTALOUT 5 Reference crystal feedback SDRAM7/ PCI_STOP 28 SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled when MODE is LOW. SDRAM6/CPU_STOP 29 SDRAM clock output. Also, active LOW control input to stop CPU clocks, enabled when MODE is LOW. SDRAM5/ PWR_DWN 31 SDRAM clock output. Also, active LOW control input to power down device, enabled when MODE is LOW. SDRAM[0:4],[8:11] 38, 37, 35, 34, 32, 21, 20, 18, 17 SDRAM clock outputs SEL0 26 CPU frequency select input, bit 0 (see table below) SEL1 46 CPU frequency select input, bit 0 (see table below) CPUCLK[0:3] 44, 43, 41, 40 CPU clock outputs PCICLK[0:3] 8, 10, 11, 12 PCI clock outputs, at one-half the CPU frequency. PCICLK_F 7 Free-running PCI clock output AGP[0:1] 13, 15 AGP clock outputs REF0 2 3.3V Reference clock output USBCLK 47 USB Clock output SDATA 23 Serial data input for serial configuration port SCLK 24 Serial clock input for serial configuration port MODE 25 Mode Select pin for enabling power management features XTALIN[3] [3] Note: 3. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. Function Table CPU/PCI Ratio CPUCLK[0:3] SDRAM[0:11] PCICLK[0:3] PCICLK_F SEL1 SEL0 0 0 2.5 83.33 MHz 33.33 MHz 66.66 MHz 14.318 MHz 48 MHz 0 1 2 66.67 MHz 33.33 MHz 66.66 MHz 14.318 MHz 48 MHz 1 0 3.0 100.0 MHz 33.33 MHz 66.66 MHz 14.318 MHz 48 MHz 1 1 2.5 75.0 MHz 30.0 MHz 60.0 MHz 14.318 MHz 48 MHz 2 AGP[0:1] REF0 USBCLK PRELIMINARY Actual Clock Frequency Values Target Frequency (MHz) Clock Output CY2283 CPU and PCI Clock Driver Strengths Actual Frequency (MHz) • Matched impedances on both rising and falling edges on the output drivers • Output impedance: 25Ω (typical) measured at 1.5V PPM CPUCLK 66.67 66.51 –2346 CPUCLK 75.0 75.0 0 CPUCLK 83.33 83.14 -2346 CPUCLK 100.0 99.77 -2346 USBCLK 48.0 48.01 167 Power Management Logic[4] - Active when MODE pin is held ‘LOW’ CPUCLK PCICLK PWR_DWN X X 0 Low Low Stopped Stopped Off 0 0 1 Low Low Running Running Running Running 0 1 1 Low 33/30 MHz Running Running Running Running 1 0 1 66/75/83/100MHz Low Running Running Running Running 1 1 1 66/75/83/100MHz 30/33.3 MHz Running Running Running Running Serial Configuration Map Bit Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0”. • I2C Address for the CY2283 is: A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 ---- Osc. PLLs Off Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable) • The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 A6 PCICLK_F Other Clocks CPU_STOP PCI_STOP Pin # Description Bit 7 -- (Reserved) drive to ‘0’ Bit 6 -- (Reserved) drive to ‘0’ Bit 5 -- (Reserved) drive to ‘0’ Bit 4 -- (Reserved) drive to ‘0’ Bit 3 -- (Reserved) drive to ‘0’ Bit 2 -- (Reserved) drive to ‘0’ Bit 1 -Bit 0 Bit 1 1 1 0 0 Bit 0 1 - Three-State 0 - N/A 1 - Testmode 0 - Normal Operation Select Functions Outputs Functional Description CPU PCI, PCI_F SDRAM Ref IOAPIC USBCLK AGP Three-State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Test Mode[6] TCLK/2[5] TCLK/4 TCLK/2 TCLK TCLK TCLK/2 TCLK/2 Notes: 4. AGP clocks are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table. 5. TCLK supplied on the XTALIN pin in Test Mode. 6. Valid only for SEL1=0. 3 PRELIMINARY Byte 1: CPU Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # CY2283 Byte 2: PCI Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Description Bit Pin # Description Bit 7 47 USBCLK Bit 7 -- (Reserved) drive to ‘0’ Bit 6 N/A (Reserved) drive to ‘0’ Bit 6 7 PCICLK_F (Active/Inactive) Bit 5 N/A (Reserved) drive to ‘0’ Bit 5 15 AGP1 (Active/Inactive) Bit 4 N/A Not used - drive to ‘0’ Bit 4 14 AGP0 (Active/Inactive) Bit 3 40 CPUCLK3 (Active/Inactive) Bit 3 12 PCICLK3 (Active/Inactive) Bit 2 41 CPUCLK2 (Active/Inactive) Bit 2 11 PCICLK2 (Active/Inactive) Bit 1 43 CPUCLK1 (Active/Inactive) Bit 1 10 PCICLK1 (Active/Inactive) Bit 0 44 CPUCLK0 (Active/Inactive) Bit 0 8 PCICLK0 (Active/Inactive) Byte 3: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Byte 4: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Description Bit Pin # Description Bit 7 28 SDRAM7 (Active/Inactive) Bit 7 N/A Not used - drive to ‘0’ Bit 6 29 SDRAM6 (Active/Inactive) Bit 6 N/A Not used - drive to ‘0’ Bit 5 31 SDRAM5 (Active/Inactive) Bit 5 N/A Not used - drive to ‘0’ Bit 4 32 SDRAM4 (Active/Inactive) Bit 4 N/A Not used - drive to ‘0’ Bit 3 34 SDRAM3 (Active/Inactive) Bit 3 17 SDRAM11 Bit 2 35 SDRAM2 (Active/Inactive) Bit 2 18 SDRAM10 Bit 1 37 SDRAM1 (Active/Inactive) Bit 1 20 SDRAM9 Bit 0 38 SDRAM0 (Active/Inactive) Bit 0 21 SDRAM8 Byte 5: Peripheral Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Byte 6: Reserved, for future use Description Bit 7 N/A (Reserved) drive to ‘0’ Bit 6 N/A (Reserved) drive to ‘0’ Bit 5 N/A (Reserved) drive to ‘0’ Bit 4 N/A (Reserved), drive to ‘0’ Bit 3 N/A (Reserved) drive to ‘0’ Bit 2 N/A (Reserved) drive to ‘0’ Bit 1 N/A (Reserved) drive to ‘0’ Bit 0 2 REF0 (Active/Inactive) 4 PRELIMINARY CY2283 Storage Temperature (Non-Condensing) ... –65°C to +150°C Maximum Ratings Max. Soldering Temperature (10 sec) ...................... +260°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ............................................... +150°C Supply Voltage ..................................................–0.5 to +7.0V Package Power Dissipation .............................................. 1W Input Voltage .............................................. –0.5V to VDD+0.5 Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together) Operating Conditions[7] Parameter Description Min. Max. Unit AVDD, V DDQ3 Analog and Digital Supply Voltage 3.135 3.465 V VDDCPU CPU Supply Voltage 2.375 3.135 2.9 3.465 V TA Operating Temperature, Ambient 0 70 °C CL Max. Capacitive Load on CPUCLK, USBCLK, IOAPIC PCICLK, AGP, SDRAM REF0 10 20 20 20 30 45 f(REF) Reference Frequency, Oscillator Nominal Value 14.318 14.318 pF MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs VILiic Low-level Input Voltage I2C inputs only VOH High-level Output Voltage VDDCPU = VDDQ2 = 2.375V Min. Max. Unit 2.0 V 0.8 0.7 IOH = 16 mA CPUCLK 2.0 V V V IOH = 18 mA IOAPIC VOL Low-level Output Voltage VDDCPU = VDDQ2 = 2.375V IOL = 27 mA CPUCLK 0.4 V IOL = 29 mA IOAPIC VOH High-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V IOH = 16 mA CPUCLK 2.4 V IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 26 mA USBCLK IOH = 36 mA REF0 VOL Low-level Output Voltage VDDQ3, AVDD, V DDCPU = 3.135V IOL = 27 mA CPUCLK 0.4V V –10 +10 µA 10 µA –10 +10 µA IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 21 mA USBCLK IOL = 29 mA REF0 IIH Input High Current VIH = V DD IIL Input Low Current VIL = 0V IOZ Output Leakage Current Three-state IDD Power Supply Current[8] VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs, CPU clocks = 66.67 MHz 300 mA IDD Power Supply Current[8] 120 mA IDDS Power-down Current VDD = 3.465V, V IN = 0 or VDD, Unloaded Outputs Current draw in power-down state 500 µA Notes: 7. Electrical parameters are guaranteed with these operating conditions. 8. Power supply current will vary with number of outputs that are running. 5 PRELIMINARY CY2283 Switching Characteristics for CY2283-1[9, 10] Parameter Output Description [11] Test Conditions t1 = t1A ÷ t1B Min. Typ. 45 50 Max. Unit t1 All Output Duty Cycle 55 % t2 CPUCLK CPU Clock Rising and Falling Edge Rate Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V 0.75 4.0 V/ns t2 AGP, REF0 AGP, REF0 Clock Rising and Falling Edge Rate Between 0.4V and 2.4V 0.85 4.0 V/ns t2 PCI PCI Rising and Falling Edge Rate Between 0.4V and 2.4V 0.85 4.0 V/ns t3 CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V 0.4 0.5 2.13 2.67 ns t4 CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V 0.4 0.5 2.13 2.67 ns t5 CPUCLK CPU-CPU Clock Skew Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, VDDCPU = 3.3V 100 500 ps t6 CPUCLK, PCICLK CPU-PCI Clock Skew Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks 3.5 5.5 ns t8 PCICLK, PCICLK PCI-PCI Clock Skew Measured at 1.5V 500 ps t9 PCICLK, AGP PCI-AGP Clock Skew Measured at 1.5V 1,200 ps t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks 500 ps t10 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V 750 ps t10 AGP Cycle-Cycle Clock Jitter Measured at 1.5V 800 ps t11 CPUCLK, PCICLK, AGP Power-up Time CPU, PCI, AGP clock stabilization from power-up 3 ms Notes: 9. Guaranteed by Design and Characterization, not 100% tested in production. 10. Device characterized and parameters guaranteed with SDRAM outputs turned off. All other outputs at maximum load. 11. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V. 6 2.5 PRELIMINARY CY2283 Switching Characteristics for CY2283-2 Parameter Output Description Test Conditions Min. Typ. Max. Unit t1 All Output Duty Cycle t1 = t1A ÷ t1B TBD TBD TBD % t2 CPUCLK CPU Clock Rising and Falling Edge Rate Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V TBD TBD TBD V/ns t2 SDRAM, AGP, REF0 SDRAM, AGP, REF0 Clock Rising and Falling Edge Rate Between 0.4V and 2.4V TBD TBD TBD V/ns t2 PCI PCI Rising and Falling Edge Rate Between 0.4V and 2.4V TBD TBD TBD V/ns t3 CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V TBD TBD TBD ns t4 CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V TBD TBD TBD ns t5 CPUCLK CPU-CPU Clock Skew TBD TBD TBD ps t6 CPUCLK, PCICLK CPU-PCI Clock Skew Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, V DDCPU = 3.3V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks TBD TBD TBD ns t7 CPUCLK, SDRAM CPU-SDRAM Clock Skew Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks TBD TBD TBD ps t8 PCICLK, PCICLK PCI-PCI Clock Skew Measured at 1.5V TBD TBD TBD ps t9 PCICLK, AGP PCI-AGP Clock Skew Measured at 1.5V TBD TBD TBD ps t10 CPUCLK, SDRAM Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks TBD TBD TBD ps t10 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V TBD TBD TBD ps t10 AGP Cycle-Cycle Clock Jitter Measured at 1.5V TBD TBD TBD ps t11 CPUCLK, PCICLK, AGP,SDRAM Power-up Time CPU, PCI, AGP, and SDRAM clock stabilization from power-up TBD TBD TBD ms Timing Requirement for the I2C Bus Parameter Description Min. Max. Unit 0 100 kHz t12 SCLK Clock Frequency t13 Time the bus must be free before a new transmission can start t14 Hold time start condition. After this period the first clock pulse is generated. t15 t16 t17 Set-up time for start condition. (Only relevant for a repeated start condition.) t18 Hold time DATA for CBUS compatible masters for I2C devices t19 DATA input set-up time t20 Rise time of both SDATA and SCLK inputs 1 µs t21 Fall time of both SDATA and SCLK inputs 300 ns t22 Set-up time for stop condition 4.7 µs 4 µs The LOW period of the clock 4.7 µs The HIGH period of the clock 4 µs 4.7 µs µs 5 0 250 4.0 7 ns µs PRELIMINARY CY2283 Switching Waveforms Duty Cycle Timing t1A t1B OUTPUT All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t4 t2 t3 CPU-CPU Clock Skew CPUCLK CPUCLK t5 CPU-SDRAM Clock Skew CPUCLK SDRAM t7 CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI-PCI Clock Skew PCICLK PCICLK t8 8 PRELIMINARY CY2283 Switching Waveforms (continued) AGP-PCI Clock Skew AGPCLK PCICLK t9 CPU_STOP[12, 13] CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) PCI_STOP[14, 15] CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Timing Requirements for the I2C Bus SDA t13 t20 t21 t14 SCL t14 t15 t18 t16 t19 Notes: 12. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 13. CPU_STOP may be applied asynchronously. It is synchronized internally. 14. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 15. PCI_STOP may be applied asynchronously. It is synchronized internally. 9 t17 t22 PRELIMINARY CY2283 Application Circuit Clock traces must be terminated with either series or parallel termination, as they are normally done Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. • Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF. In some cases, smaller value capacitors may be required. • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace – Rout • Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout and Termination Techniques for Cypress Clock Generators” for more details. • If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 10 PRELIMINARY CY2283 Test Circuit VDDQ3 1 48 0.1 µF 0.1 µF 3 45 VDDCPU 6 42 0.1 µF 0.1 µF 9 14 0.1 µF 0.1 µF CY2283-1,-2 39 36 0.1 µF 16 33 19 30 22 27 0.1 µF OUTPUTS CLOAD Note: All Capacitors must be placed as close to the pins as is possible Ordering Information Ordering Code Package Name Operating Range Package Type CY2283PVC–1 O48 48-Pin SSOP Commercial CY2283PVC–2 O48 48-Pin SSOP Commercial Document #: 38–00685–A Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation. 11 PRELIMINARY CY2283 Package Diagram 48-Lead Shrunk Small Outline Package O48 51-85061-B © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.