0 CY2220 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Features Benefits ® • Compliant to Intel CK00 Clock Synthesizer/Driver Specifications Supports next generation Pentium® processors using differential clock drivers • Multiple output clocks at different frequencies Motherboard clock generator — Four pairs of differential CPU outputs, up to 133 MHz — Support Multiple CPUs and a chipset — Ten synchronous PCI clocks — Support for PCI slots and chipset — Two Memory Reference clocks, 180 degrees out of phase — Drives up to two Direct Rambus™ Clock Generators (DRCG) — Four AGP and Hub Link clocks at 66 MHz — Supports USB host controller and SuperI/O chip — Two 48-MHz clocks — Supports ISA slots and I/O chip — Two reference clocks at 14.318 MHz • Spread Spectrum clocking Enables reduction of EMI and overall system cost — 31 kHz modulation frequency — Default is –0.6%, which is recommended by Intel • Power-down features Enables ACPI compliant designs • Three Select inputs Supports up to eight CPU clock frequencies • Low-skew and low-jitter outputs Meets tight system timing requirements at high frequency • OE and Test Mode support Enables ATE and “bed of nails” testing • 56-pin SSOP package Widely available, standard package enables lower cost Pin Configuration Logic Block Diagram SSOP Top View MultSel0 VSSREF REFCLK0/MultSel_0 1 56 VDDMEM 2 55 MemRef REFCLK1/MultSel_1 3 54 MemRefB VDDREF 4 53 VSSMEM XTALIN 5 52 SPREAD XTALOUT VSSPCI 6 51 CPUCLK_3 7 50 CPUCLK_3B PCICLK_0 8 49 VDDCPU PCICLK_1 VDDPCI 9 48 10 47 CPUCLK_2 CPUCLK_2B PCICLK_2 11 46 VSSCPU PCICLK_3 45 CPUCLK_1 VSSPCI 12 13 44 CPUCLK_1B PCICLK_4 14 43 VDDCPU PCICLK_5 VDDPCI 15 42 CPUCLK_0 16 41 PCICLK_6 PCICLK_7 VSSPCI 17 40 CPUCLK_0B VSSCPU 18 39 IREF 19 38 PCICLK_8 20 37 AVDD AVSS PCICLK_9 21 36 VDD3V66 VDDPCI 22 35 Sel133 VSSUSB 23 34 3V66_3 3V66_2 24 25 33 VSS3V66 32 VSS3V66 26 31 3V66_1 27 30 28 29 3V66_0 VDD3V66 CPUCLK [0–3] MultSel1 XTALIN XTALOUT SELA SELB SEL133 14.318 MHz OSC. Divider and Stop Logic CPU PLL CPUCLKB [0–3] MemRef, MemRefB PCICLK [0–9] (33.33 MHz) EPROM SPREAD 3V66 [0–3] (66.67 MHz) PWR_DWN SYS PLL USBCLK [0-1] (48 MHz) USBCLK0/SelA USBCLK1/SelB VDDUSB PWR_DWN CY2220 REFCLK [0–1] Intel and Pentium are registered trademarks of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc. Cypress Semiconductor Corporation Document #: 38-07206 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 30, 2002 CY2220 Pin Summary Name Pins Description VSSREF 1 3.3V Reference ground VDDREF 4 3.3V Reference voltage supply VSSPCI 7, 13, 19 3.3V PCI ground VDDPCI 10, 16, 22 3.3V PCI voltage supply VSS3V66 32, 33 3.3V AGP and Hub Link ground VDD3V66 29, 36 3.3V AGP and Hub Link voltage supply VSSUSB 24 3.3V USB ground VDDUSB 27 3.3V USB voltage supply VSSCPU 40, 46 3.3V CPU ground VDDCPU 43, 49 3.3V CPU voltage supply VSSMEM 53 3.3V Memory ground VDDMEM 56 3.3V Memory voltage supply AVSS 37 Analog ground for PLL and Core AVDD 38 Analog voltage supply to PLL and Core IREF 39 Reference current for external biasing XTALIN[1] 5 Reference crystal input XTALOUT[1] 6 Reference crystal feedback CPUCLK [0–3] 42, 45, 48, 51 CPU clock outputs CPUCLK [0–3]B 41, 44, 47, 50 Inverse CPU clock outputs PCICLK [0–9] 8, 9, 11, 12, 14, 15, 17, 18, 20, 21 PCI clock outputs, synchronously running at 33.33 MHz MemRef 55 MemRef clock output, drives memory clock generator MemRefB 54 MemRefB clock output 180 degrees out of phase with MemRef 3V66_ [0–3] 30, 31, 34, 35 AGP and Hub Link clock outputs, running at 66 MHz USBCLK [0–1]/Sel[A–B] 25, 26 Sel [A–B] inputs are sensed then internally latched on power-up before the pins are used for 48-MHz USB clock outputs REFCLK[0–1]/MultSel[0–1] 2, 3 MultSel[0–1] inputs are sensed then internally latched on power-up before the pins are Reference clock outputs, 14.318 MHz PWR_DWN 28 Active LOW input, powers down part when asserted SPREAD[2] 52 Active LOW input, enables spread spectrum when asserted SEL133 23 CPU frequency select input (See Function Table) Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, “Crystal Oscillator Topics.” 2. Input is static HIGH or LOW. Frequency of toggling cannot exceed 30 MHz. Document #: 38-07206 Rev. *A Page 2 of 11 CY2220 Function Table[3] SEL133 SELA SELB CPUCLK (MHz) MemRef (MHz) 3V66CLK (MHz) PCICLK (MHz) USBCLK (MHz) REFCLK (MHz) 0 0 0 100 50 66 33 48 14.318 0 0 1 N/A N/A N/A N/A N/A N/A 0 1 0 N/A N/A N/A N/A N/A N/A 0 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 0 0 133 66 66 33 48 14.318 1 0 1 N/A N/A N/A N/A N/A N/A 1 1 0 N/A N/A N/A N/A N/A N/A 1 1 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK Actual Clock Frequency Values Clock Output Target Frequency (MHz) CY2220-1 CY2220-2 Actual Frequency (MHz) PPM Actual Frequency (MHz) PPM CPUCLK 100 99.126 –8741 100.227 +2270 CPUCLK 133 132.769 –1740 133.269 +2022 USBCLK 48 48.008 167 48.008 167 Swing Select Functions Output Current VOH @ Z, Iref = 2.32 mA Rr = 475 ± 1%, Iref = 2.32 mA IOH = 5*Iref 0.71 @ 60 50Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 5*Iref 0.59 @ 50 1 60Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 6*Iref 0.85 @ 60 0 1 50Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 6*Iref 0.71 @ 50 1 0 60Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 4*Iref 0.56 @ 60 1 0 50Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 4*Iref 0.47 @ 50 1 1 60Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 7*Iref 0.99 @ 60 1 1 50Ω Rr = 475 ± 1%, Iref = 2.32 mA IOH = 7*Iref 0.82 @ 50 MultSel0 MultSel1 Board Target Reference R, IREF = 0 0 60Ω 0 0 0 Clock Driver Impedances Impedance Buffer Name VDD Range CPUCLK, CPUCLKB Buffer Type Minimum Ω Typical Ω Maximum Ω Type X1 USB, REF 3.135–3.465 Type 3 20 40 60 PCI, 3V66 3.135–3.465 Type 5 12 30 55 MemRef, MemRefB 3.135–3.465 Type 5 12 30 55 Note: 3. TCLK is a test clock driven in on the XTALIN input in test mode. Document #: 38-07206 Rev. *A Page 3 of 11 CY2220 Maximum Ratings Storage Temperature (Non-Condensing).......–65°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature.................................................. +150°C Supply Voltage....................................................–0.5 to +7.0V Package Power Dissipation................................................1W Input Voltage...............................................–0.5V to VDD + 0.5 Static Discharge Voltage (per JEDEC EIA/JESD22-A114-A)................................2000V Operating Conditions Over which Electrical Parameters are Guaranteed Parameter Description VDDREF, VDDPCI, AVDD, VDD3V66, VDDUSB, VDDCPU, VDDMEM 3.3V Supply Voltages TA Operating Temperature, Ambient Cin Input Pin Capacitance Nominal Value CXTAL XTAL Pin Capacitance CL Max. Capacitive Load on MemRef, USBCLK, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. Max. Unit 3.135 3.465 V 0 70 °C 18 pF 18 pF pF 22.5 pF pF 20 30 14.318 14.318 MHz 0.05 50 ms Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage MemRef, USB, REF, 3V66 0.8 V IOH = –1 mA 2.4 V IOH = –1 mA 2.4 V MemRef, USB, REF, 3V66 IOL = 1 mA PCI IOL = 1 mA Low-level Output Voltage IIH Input High Current 0 < VIN < VDD IIL Input Low Current 0 < VIN < VDD IOH High-level Output Current CPU For IOH =6*IRef Configuration Low-level Output Current V PCI VOL IOL 2.0 Type X1, VOH = 0.65V 0.4 V 0.55 V –5 5 µA –5 5 µA –12.9 –14.9 mA USB, REF Type 3, VOH = 2.4V –15 –51 3V66, PCI, MemRef, MemRefB Type 5, VOH = 2.4V –30 –100 USB, REF Type 3, VOL = 0.4V 10 24 3V66, PCI, MemRef, MemRefB Type 5, VOL =0.4 V 20 49 mA µA IOZ Output Leakage Current Three-state 10 IDD3 3.3V Power Supply Current AVDD/VDD33 = 3.465V, FCPU = 133 MHz 250 mA IDDPD3 3.3V Shutdown Current 60 mA Document #: 38-07206 Rev. *A AVDD/VDDQ3 = 3.465V Page 4 of 11 CY2220 - Switching Characteristics[4] Over the Operating Range Parameter Output Description Test Conditions Min. Max. Unit t1 All Output Duty 45 55 % t2 CPU Rise Time Measured at 20% to 80% of VOH 175 700 ps t2 USB, REF Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t2 PCI, 3V66, MemRef Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t3 CPU Fall Time Measured at 80% to 20% of VOH 175 700 ps t3 USB, REF Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 V/ns t3 PCI, 3V66, MemRef Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t5 3V66 3V66-3V66 Skew Measured at 1.5V 250 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66,PCI 3V66-PCI Clock Skew 3V66 leads. Measured at 1.5V 3.5 ns t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 200 ps t9 Mref Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 300 ps t9 USB Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps CPU, PCI Settle Time CPU and PCI clock stabilization from power-up 3 ms CPU Rise/Fall Matching Measured with test loads[6, 7] Voh Cycle[5] t1A/(t1B) 1.5 20% [7] CPU Overshoot Measured with test loads CPU Undershoot Measured with test loads[7] –0.2 Measured with test loads[7] 0.65 loads[7] CPU High-level Output Voltage Vol CPU Low-level Output Voltage Measured with test Vcrossover CPU Crossover Voltage Measured with test loads[7] VOH + 0.2 V V 0.74 V 0.0 0.05 V 45% of VOH 55% of VOH V Notes: 4. All parameters specified with loaded outputs. Parameters not tested in production, but are guaranteed by design characterization. 5. Duty cycle is measured at 1.5V with VDD at 3.3V on all output except CPU. Duty Cycle on CPU is measured at VCrossover. 6. Determined as a fraction of 2*(tRP – tRN)/(tRP + tRN)Where tRP is a rising edge and tRN is an intersecting falling edge. 7. The test load is specified in test circuit. Document #: 38-07206 Rev. *A Page 5 of 11 CY2220 Switching Waveforms Duty Cycle Timing (Single Ended Output) t1A t1B Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VOH OUTPUT 0V t2 t3 CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 Document #: 38-07206 Rev. *A Page 6 of 11 CY2220 Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t6 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B t9A t9B Host_b Host Cycle-Cycle Clock Jitter CLK PWR_DOWN[8] CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Note: 8. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Document #: 38-07206 Rev. *A Page 7 of 11 CY2220 Test Circuit[9, 10] VDDPCI, VDD3V66, VDDUSB, VDDREF, AVDD, VDDCPU, VDDMRef Rs 33.2Ω Rp 49.9Ω 1, 7, 13, 19, 24, 32, 33, 37, 40, 46, 53 4, 10, 16, 22, 27, 29, 36, 38, 43, 49, 56 Rp CY2220 Ref, USB Outputs Test Node CPU Test Nodes OUTPUTS 20 pF PCI, 3V66, MRef Outputs Test Node Rs Rs Rp 30 pF Ordering Information Ordering Code Package Name Package Type Operating Range CY2220PVC-1 O56 56-Pin SSOP Commercial CY2220PVC-2 O56 56-Pin SSOP Commercial Notes: 9. Each supply pin must have an individual decoupling capacitor. Document #: 38-07206 Rev. *A 10. All capacitors must be placed as close to the pins as is physically possible. Page 8 of 11 CY2220 Layout Example +3.3V Supply FB VDDQ3 C4 0.005 µF G G G G G G C3 G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 V V V V CY2220 G 10 µF V V V V V V 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 G G G G G FB = Dale ILB1206 - 300 (30Ω @ 100 MHz) Cermaic Caps C3 = 10–22 µF G = VIA to GND plane layer C4 = 0.005 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.01 µF ceramic Document #: 38-07206 Rev. *A Page 9 of 11 CY2220 Package Diagram 56-Lead Shrunk Small Outline Package O56 51-85062-*C Document #: 38-07206 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2220 Document Title: CY2220 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Document Number: 38-07206 ECN NO. Issue Date Orig. of Change ** 111730 01/17/02 DSG Change from Spec number: 38-00813 to 38-07206 *A 121841 12/30/02 RBI Power up requirements added to Operating Conditions Information REV. Document #: 38-07206 Rev. *A Description of Change Page 11 of 11