FPAL30SL60 FPAL30SL60 Smart Power Module (SPM) General Description Features FPAL30SL60 is an advanced smart power module (SPM) that Fairchild has newly developed and designed to provide very compact and low cost, yet high performance ac motor drives mainly targeting low speed low-power inverter-driven application like air conditioners. It combines optimized circuit protection and drive matched to low-loss IGBTs. Highly effective short-circuit current detection/protection is realized through the use of advanced current sensing IGBT chips that allow continuous monitoring of the IGBTs current. System reliability is further enhanced by the built-in over-temperature and integrated under-voltage lock-out protection. The high speed built-in HVIC provides optocoupler-less IGBT gate driving capability that further reduce the overall size of the inverter system design. In addition the incorporated HVIC facilitates the use of single-supply drive topology enabling the FPAL30SL60 to be driven by only one drive supply voltage without negative bias. • UL Certified No. E209204 • 600V-30A 3-phase IGBT inverter bridge including control ICs for gate driving and protection • Single-grounded power supply due to built-in HVIC • Typical switching frequency of 3kHz • Built-in thermistor for over-temperature monitoring • Inverter power rating of 2kW / 100~253 Vac • Isolation rating of 2500Vrms/min. • Very low leakage current due to using ceramic substrate • Adjustable current protection level by varying series resistor value with sense-IGBTs Applications • AC 100V ~ 253V three-phase inverter drive for small power (2kW) ac motor drives • Home appliances applications requiring low switching frequency operation like air conditioners drive system • Application ratings: - Power : 2kW / 100~253 Vac - Switching frequency : Typical 3kHz (PWM Control) - 100% load current : 15A (Irms) External View and Marking Information Top View Bottom View 57 mm 55 mm Marking Device Name Version, Lot Code Fig. 1. ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Integrated Power Functions • 600V-30A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3) Integrated Drive, Protection and System Control Functions • For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting Control circuit under-voltage (UV) protection Note) Available bootstrap circuit example is given in Figs. 11, 16 and 17. • For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC) Control supply circuit under-voltage (UV) protection • Temperature Monitoring: System over-temperature monitoring using built-in thermistor Note) Available temperature monitoring circuit is given in Fig. 17. • Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side supply) • Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input Pin Configuration Top View VS(U) VB(U) VCC(UH) IN(UH) VCC(L) COM(L) IN(UL) IN(VL) IN(WL) VFO CFOD CSC VS(V) VB(V) VCC(VH) IN(VH) COM(H) RSC NC VS(W) VB(W) VTH RTH VCC(WH) IN(WH) W V U N P Fig. 2. Pin Descriptions Pin Number 1 Pin Name VCC(L) Pin Description Low-side Common Bias Voltage for IC and IGBTs Driving 2 COM(L) 3 IN(UL) Signal Input Terminal for Low-side U Phase 4 IN(VL) Signal Input Terminal for Low-side V Phase 5 IN(WL) Signal Input Terminal for Low-side W Phase 6 VFO 7 CFOD Capacitor for Fault Output Duration Time Selection 8 CSC Capacitor (Low-pass Filter) for Short-current Detection Input 9 RSC Resistor for Short-circuit Current Detection 10 NC NO Connection Thermistor Bias Voltage Low-side Common Supply Ground Fault Output Terminal 11 VTH 12 RTH 13 W Output Terminal for W Phase 14 V Output Terminal for V Phase 15 U Output Terminal for U Phase ©2003 Fairchild Semiconductor Corporation Series Resistor for the Use of Thermistor (Temperature Detection) Rev. C1, May 2003 FPAL30SL60 Pin Descriptions (Continued) Pin Number 16 Pin Name N Negative DC–Link Input Pin Description 17 P Positive DC–Link Input 18 IN(WH) 19 VCC(WH) 20 VB(W) High-side Bias Voltage for W Phase IGBT Driving 21 VS(W) High-side Bias Voltage Ground for W Phase IGBT Driving 22 COM(H) 23 IN(VH) 24 VCC(VH) 25 VB(V) High-side Bias Voltage for V Phase IGBT Driving 26 VS(V) High-side Bias Voltage Ground for V Phase IGBT Driving 27 IN(UH) Signal Input Terminal for High-side U Phase 28 VCC(UH) 29 VB(U) High-side Bias Voltage for U Phase IGBT Driving 30 VS(U) High-side Bias Voltage Ground for U Phase IGBT Driving Signal Input Terminal for High-side W Phase High-side Bias Voltage for W Phase IC High-side Common Supply Ground Signal Input Terminal for High-side V Phase High-side Bias Voltage for V Phase IC High-side Bias Voltage for U Phase IC Internal Equivalent Circuit and Input/Output Pins (29) VB(U) (1) VCC(L) VCC VB Vcc HO IN (28) VCC(UH) (27) IN(UH) VS COM (2) COM(L) COM(L) (3) IN(UL) IN(UL) (4) IN(VL) IN(VL) (5) IN(WL) IN(WL) (6) VFO V(FO) (7) CFOD C(FOD) (8) CSC C(SC) (30) VS(U) Uout (25) VB(V) Vout VB Vcc HO IN VS COM (23) IN(VH) (22) COM(H) (26) VS(V) Wout (20) VB(W) (9) RSC VB Vcc HO IN (19) VCC(WH) (18) IN(WH) VS COM (10) NC (11) VTH (24) VCC(VH) (21) VS(W) THERMISTOR (12) RTH W (13) V (14) U (15) N (16) P (17) Note 1. Inverter low-side ( (1) – (12) pins) is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current sensing and protection functions. 2. Inverter power side ( (13) – (17) pins) is composed of two inverter dc-link input terminals and three inverter output terminals. 3. Inverter high-side ( (18) – (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT. Fig. 3. ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Absolute Maximum Ratings Inverter Part (TC = 25°C, Unless Otherwise Specified) Item Symbol VDC Supply Voltage Supply Voltage (Surge) VPN(Surge) Collector-emitter Voltage Condition Applied to DC - Link Rating 450 Applied between P- N VCES Unit V 500 V 600 V A Each IGBT Collector Current ± IC TC = 25°C (Note Fig. 4) 30 Each IGBT Collector Current (Peak) ± ICP TC = 25°C (Note Fig. 4) 60 A Collector Dissipation PC TC = 25°C per One Chip 56 W Operating Junction Temperature TJ (Note 1) -55 ~ 150 °C Note 1. It would be recommended that the average junction temperature should be limited to TJ ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation. Control Part (TC = 25°C, Unless Otherwise Specified) Item Control Supply Voltage Symbol Condition Applied between VCC(H) - COM(H), VCC(L) - COM(L) VCC High-side Control Bias Voltage VBS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) VS(W) Input Signal Voltage VIN Applied between IN(UH), IN(VH), IN(WH) - COM(H) IN(UL), IN(VL), IN(WL) - COM(L) Fault Output Supply Voltage VFO Applied between VFO - COM(L) Fault Output Current IFO Sink Current at VFO Pin Current Sensing Input Voltage VSC Applied between CSC - COM(L) Rating 18 Unit V 20 V -0.3 ~ 6.0 V -0.3~VCC+0.5 V 5 mA -0.3~VCC+0.5 V Total System Item Self Protection Supply Voltage Limit (Short Circuit Protection Capability) Module Case Operation Temperature Symbol Condition VPN(PROT) Applied to DC - Link, VCC = VBS = 13.5 ~ 16.5V TJ = 125°C, Non-repetitive, less than 6µs TC Storage Temperature TSTG Isolation Voltage VISO ©2003 Fairchild Semiconductor Corporation Note Fig. 4 60Hz, Sinusoidal, AC 1 minute, Connection Pins to Heat-sink Plate Rating 400 Unit V -20 ~ 100 °C -55 ~ 150 °C 2500 Vrms Rev. C1, May 2003 FPAL30SL60 Case Temperature (TC) Detecting Point VS(U) VB(U) VCC(UH) IN(UH) VCC(L) COM IN(UL) IN(VL) IN(WL) VFO CFOD CSC VS(V) VB(V) VCC(VH) IN(VH) COM RSC NC VS(W) VB(W) VTH RTH Ceramic Substate VCC(WH) IN(WH) W V U N P Fig. 4. Tc Measurement Point ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 Thermal Resistance Item Junction to Case Thermal Resistance Contact Thermal Resistance Symbol Condition Rth(j-c)Q Each IGBT under Inverter Operating Condition (Note 2) Min. Typ. - Max. 2.2 Unit °C/W Rth(j-c)F Each FWDi under Inverter Operating Condition (Note 2) - - 3.18 °C/W Rth(c-f) Ceramic Substrate (per 1 Module) Thermal Grease Applied - - 0.06 °C/W Max. 2.5 Unit V Note 2. For the measurement point of case temperature (Tc), please refer to Fig. 4. Electrical Characteristics Inverter Part (Tj = 25°C, Unless Otherwise Specified) Item Collector - emitter Saturation Voltage Symbol VCE(SAT) VCC = VBS = 15V VIN = 0V Condition IC = 30A, Tj = 25°C - - 2.6 V IC = 30A, Tj = 25°C - - 2.6 V VFM VIN = 5V Switching Times tON VPN = 300V, VCC = VBS = 15V IC = 30A, Tj = 25°C VIN = 5V ↔ 0V, Inductive Load (High-Low Side) IC = 30A, Tj = 125°C tOFF tC(OFF) trr Collector - emitter Leakage Current ICES Typ. - IC = 30A, Tj = 125°C FWDi Forward Voltage tC(ON) Min. - - - 2.4 V - 0.45 - us - 0.18 - us - 0.9 - us - 0.36 - us (Note 3) - 0.1 - us VCE = VCES, Tj = 25°C - - 250 uA Note 3. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally. For the detailed information, please see Fig. 5. ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Absolute Maximum Ratings 100% IC VCE IC IC V IN VCE V IN t ON VIN(ON) FPAL30SL60 t rr t OFF t C(ON) 90% IC 10% IC 10% VCE V IN(OFF) tC(OFF) 10% VCE (a) Turn-on 10% IC (b) Turn-off Fig. 5. Switching Time Definition VCE : 100V/div. IC : 10A/div. time : 100ns/div. (a) Turn-on IC : 10A/div. VCE : 100V/div. time : 100ns/div. (b) Turn-off Fig. 6. Experimental Results of Switching Waveforms Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), TC=25°°C ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 Control Part (Tj = 25°C, Unless Otherwise Specified) Item Control Supply Voltage High-side Bias Voltage Symbol Condition Applied between VCC(H),VCC(L) - COM VCC VBS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) Min. 13.5 Typ. Max. Unit 15 16.5 V 13.5 15 16.5 V IQCCL VCC = 15V IN(UL, VL, WL) = 5V VCC(L) - COM(L) - - 26 mA IQCCH VCC = 15V IN(UH, VH, WH) = 5V VCC(U), VCC(V), VCC(W) - COM(H) - - 130 uA Quiescent VBS Supply Current IQBS VBS = 15V IN(UH, VH, WH) = 5V VB(U) - VS(U), VB(V) -VS(V), VB(W) - VS(W) - - 420 uA Fault Output Voltage VFOH VSC = 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V VFOL VSC = 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 1.1 V PWM Input Frequency fPWM TC ≤ 100°C, TJ ≤ 125°C - 3 - kHz Allowable Input Signal Blanking Time considering Leg Arm-short tdead -20°C ≤ TC ≤ 100°C 3 - - us Quiescent VCC Supply Current Short Circuit Trip Level Sensing Voltage of IGBT Current Supply Circuit UnderVoltage Protection Fault-out Pulse Width VSC(ref) VSEN 0.45 0.51 0.56 V -20°C ≤ TC ≤ 100°C, @ RSC = 82 Ω and IC = 30A (Note Fig. 8) 0.37 0.45 0.56 V TJ ≤ 125°C 11.5 12 12.5 V UVCCR Reset Level 12 12.5 13 V UVBSD Detection Level 7.3 9.0 10.8 V UVBSR Reset Level 8.6 10.3 12 V 1.4 1.8 2.0 ms UVCCD tFOD ON Threshold Voltage VIN(ON) OFF Threshold Voltage VIN(OFF) ON Threshold Voltage VIN(ON) OFF Threshold Voltage VIN(OFF) Resistance of Thermistor TJ = 25°, VCC = 15V (Note 4) RTH Detection Level VCC = 15V, C(sc) = 1V CFOD = 33nF (Note 5) High-Side Low-Side Applied between IN(UH), IN(VH), IN(WH) - COM(H) - - 0.8 V 3.0 - - V Applied between IN(UL), IN(VL), IN(WL) - COM(L) - - 0.8 V 3.0 - - V @ TC = 25°C (Note Figs. 4 and 7) - 50 - kΩ @ TC = 80°C (Note Figs. 4 and 7) - 6.3 - kΩ Note 4. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be selected around 56 Ω in order to make the SC trip-level of about 45A. Please refer to Fig. 8 which shows the current sensing characteristics according to sensing resistor RSC. 5. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F] ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Electrical Characteristics FPAL30SL60 R-T Curve 70 60 Resistance [kΩ] 50 40 30 20 10 0 20 30 40 50 60 70 80 90 100 110 120 130 Temperature [℃] Fig. 7. R-T Curve of The Built-in Thermistor 180 SC Trip Current ISC [A] 160 140 120 100 80 60 40 20 10 20 30 40 50 60 70 80 90 Sensing Resistor RSC [Ω] Fig. 8. Relationship between Sensing Resistor and SC Trip Current for Short-Circuit Protection (ISC = 82 × Rating Current(30A) / RSC ) ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 Item Mounting Torque Limits Condition Mounting Screw: M3 (Note 6 and 7) Ceramic Flatness Units Recommended 10Kg•cm Min. 8 Typ. 10 Max. 12 Kg•cm Recommended 0.98N•m 0.78 0.98 1.17 N•m 0 - +100 um - 56 - g (Note Fig. 9) Weight Fig. 9. Flatness Measurement Position of The Ceramic Substrate Note 6. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction. 7. Avoid one side tightening stress. Fig.10 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to be damaged. 4 2 1 3 Fig. 10. Mounting Screws Torque Order (1 → 2 → 3 → 4) ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Mechanical Characteristics and Ratings Item Symbol Value Condition Supply Voltage VPN Applied between P - N Control Supply Voltage VCC Applied between VCC(H) - COM, VCC(L) - COM 13.5 15 16.5 V High-side Bias Voltage VBS Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) 13.5 15 16.5 V Blanking Time for Preventing Arm-short tdead For Each Input Signal 3 - - us fPWM TC ≤ 100°C, TJ ≤ 125°C - 3 - kHz PWM Input Signal Typ. 300 Max. 400 Unit Min. - V Input ON Threshold Voltage VIN(ON) Applied between UIN,VIN, WIN - COM 0 ~ 0.65 V Input OFF Threshold Voltage VIN(OFF) Applied between UIN,VIN, WIN - COM 4 ~ 5.5 V ICs Internal Structure and Input/Output Conditions RBS CBSC CBS DBS P 15V Line VB(UH,VH,WH) VCC(UH,VH,WH) UV DETECT LEVEL SHIFT 5V Line RP CBP15 IN(UH,VH,WH) R R S Q PULSE FILTER PULSE GENERATOR VS (UH,VH,WH) COM CPH HVIC VCC(L) 5V Line RP BANDGAP REFERENCE RPF IN(UL,VL,WL) U,V,W LVIC UV DETECT PULSE GENERATOR (HYSTERISIS) TIME DELAY UV LATCH_UP UV PROTECTION BUFFER OUTPUT (UL,VL,WL) SOFT_OFF CONTROL SC PROTECTION VFO CPL FAULT OUTPUT DURATION CPF SC LATCH_UP TIME DELAY SC DETECTION CFOD CFOD N CSC RF RSC Note 1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect short-circuit current. Low-side part of the inverter consists of three sense-IGBTs 2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs 3. Each IC has under voltage detection and protection function. 4. The logic input is compatible with standard CMOS or LSTTL outputs. 5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each SPM gating input pin. 6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics. Fig. 11. ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Recommended Operating Conditions FPAL30SL60 Time Charts of SPMs Protective Function Input Signal Internal IGBT Gate-Emitter Voltage P3 Control Supply Voltage P2 P5 UV detect UV reset P6 P1 Output Current P4 Fault Output Signal P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : Fault signal generation P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 12. Under-Voltage Protection (Low-side) Input Signal P3 P5 VBS UV detect UV reset P2 P6 P1 Output Current Fault Output Signal P4 P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : No fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current Fig. 13. Under-Voltage Protection (High-side) ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 P5 Input Signal P6 Internal IGBT Gate-Em itter Voltage SC Detection P1 P4 P7 Output Current P2 SC Reference Voltage (0.5V) Sensing Voltage RC Filter Delay Fault Output Signal P8 P3 P1 : Normal operation - IGBT ON and conducting currents P2 : Short-circuit current detection P3 : IGBT gate interrupt / Fault signal generation P4 : IGBT is slowly turned off P5 : IGBT OFF signal P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation P7 : IGBT OFF state P8 : Fault-output reset and normal operation start Fig. 14. Short-circuit Current Protection (Low-side Operation only) 5V-Line FPAL30SL60 4.7k Ω 4.7k Ω 4.7k Ω 100 Ω CPU IN (UH) , IN (VH) , IN(WH) 100 Ω IN (UL) , IN (VL) , IN (WL) 100 Ω VFO 1nF 1nF 0.47nF 1.2nF COM Note It would be recommended that by-pass capacitors for the gating input signals, IN(XX) should be placed on the SPM pins and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible. Fig. 15. Recommended CPU I/O Interface Circuit ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 One-leg Diagram of FPAL30SL60 15V-Line P 20Ω 0.1uF 56uF Vcc VB IN HO COM VS Inverter Output Vcc 0.1uF 1000uF IN OUT COM N Fig. 16. Recommended Bootstrap Operation Circuit and Parameters ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 Gating VL Gating WL Gating UH CPU Gating VH Fault Gating WH CBPF RS R S RS RS RS RS RS V B(U) (29) 5V line (1) V CC(L) RP RP RP (2) COM(L) RP (3) IN (UL) (4) IN(VL) VCC VB Vcc HO IN COM(L) IN(UL) Uout VB(V) (25) Vout VB Vcc HO IN VS COM (6) VFO CSC (8) CSC RF (9) RSC RSC RP C(FOD) DBS RBS CPH CPH CPH IN(VH) (23) COM(H) (22) VB(W) (20) Wout CBSC CBS DBS RBS VCC(WH) (19) VB Vcc HO IN C(SC) IN(WH) (18) 15V line V S(W) (21) (10) NC (11) VTH CSP05 RP VS COM 5V line Tem p. Monitoring RP CBSC CBS V CC(VH) (24) VS(V) (26) V(FO) (7) CFOD 5V line IN(UH) (27) V S(U) (30) IN (VL) IN (WL) CFOD RBS VS COM (5) IN(WL) CPF CPL CPL CPL DBS VCC(UH) (28) THERMISTOR CSPC15 (12) RTH CSPC05 RTH CBSC CBS (13) W (14) V (15) U CSP15 (17) P (16) N CDCS M - Vdc + Note 1. RPCPL/RPCPH coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM input pin. 2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please refer to Fig. 15. 4. CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended. 5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin7) and COM(L)(pin2). (Example : if CFOD = 5.6 nF, then tFO = 300 µs (typ.)) Please refer to the note 5 for calculation method. 6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2nF by-pass capacitor should be used across each power supply connection terminals. 7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible. 8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 µs. RF should be at least 30 times larger than RSC. (Recommended Example: RSC = 56 Ω, RF = 3.9kΩ and CSC = 1nF) 9. Each capacitor should be mounted as close to the pins of the SPM as possible. 10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency noninductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended. 11.Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays. It is recommended that the distance be 5cm at least Fig. 17. Application Circuit ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 FPAL30SL60 Gating UL FPAL30SL60 Detailed Package Outline Drawings ©2003 Fairchild Semiconductor Corporation Rev. C1, May 2003 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ Bottomless™ FAST® FASTr™ CoolFET™ CROSSVOLT™ FRFET™ GlobalOptoisolator™ DOME™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ EnSigna™ I2C™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™ ImpliedDisconnect™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic® TruTranslation™ UHC™ UltraFET® VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2003 Fairchild Semiconductor Corporation Rev. I2