ETC IL-P3

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DALSA IL-P3
Image Sensors
Fast and sensitive, DALSA’s IL-P3 has been designed and
fabricated using the industry’s most sophisticated technology. The IL-P3 delivers consistently high image quality, and
its single output design reduces the cost and complexity of
support electronics.
Features
n
n
n
n
n
n
n
n
Single output, 40MHz data rate
Surface gated photodiodes for low lag
Line rate to 73kHz (512 model)
Low voltage clocks (<5V)
14µm (H) x 14µm (V) pixels, 100% fill factor
512, 1024, or 2048 pixels
Antiblooming and exposure control
Highly sensitive, with responsivity reaching
43V/(µJ/cm2)
Description
Physical Characteristics
IL-P3
Pixel dimensions
Active area 14µm x
Active pixels per line
Isolation pixels per line
Shielded pixels per line
14µm x 14µm
7.2 / 14.4 / 28.7mm
512 / 1024 / 2048
20
6
Table 1. IL-P3 Pin Functional Description
Pin
Symbol
Name
1
2
3
4, 11
5
6, 20
7, 10, 14
8
9
12
13
15, 16
17, 18
19
21
22
23
24
VSS
OS
VDD
TCK
PR
VLS
NC
VPR
VSTOR
VLOW
VHIGH
CR2
CR1
VBB
CRLAST
VSET
RST
VOD
Amplifier Return
Output Signal
Amplifier Supply
Transfer Gate
Pixel Reset Gate
Light Shield
No Connection
Pixel Reset Drain, Guard Ring
Pixel Storage Gate
Low Bias Voltage
High Bias Voltage
Readout Register, Phase 2
Readout Register, Phase 1
Substrate
Last Register
Output Node Set Gate
Output Reset Gate
Output Reset Drain
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VSS 1
OS 2
VDD 3
TCK 4
PR 5
VLS 6
NC 7
VPR 8
VSTOR 9
NC 10
TCK 11
VLOW 12
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24
23
22
21
20
19
18
17
16
15
14
13
VOD
RST
VSET
CRLAST
VLS
VBB
CR1
CR1
CR2
CR2
NC
VHIGH
1
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IL-P3
Line Scan Sensors
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Figure 1. IL-P3 Block Diagram
1S
1I
5S
2I
N Surface Gated Photodiodes (14 µm x 14 µm)
2I
VSTOR
PR
VPR
Storage Well with Anti-blooming and Exposure Control
VDD
CCD Readout Shift Register
15 I
S
OS
I
VSS
11
VBB VOD
Light-shielded pixels
Isolation pixels
N = 512,1024,or 2048
RST VSET CRLAST
Relative position of package Pin 1
Table 3. # of DC Biases Required
DC Biases
# Required
Regulated?
PR off
PR on
Table 2. # of Clock Drivers Required
Clock Drivers
Min. # Required
Type
Speed
PR off
PR on
1
1
2
2
Low Voltage
Low Voltage
Glitch
1.
2.
High
Low
High
2
1
1
2
2
1
Redundant clock drivers may be required to drive
the CCD input capacitance. Refer to Figure 7 for
details.
PR = Pixel Reset (exposure control).
DALSA’s IL-P3 series of linear CCD image sensors use proprietary technology to provide a single output at 40MHz.
The series employs buried channel CCD shift registers to
maximize output speed and reduce noise. The sensor has a
dynamic range of >1800:1 and provides output which is linear for the operating range of light input. The IL-P3’s exposure control allows integration times shorter than the
readout time. Proprietary DALSA image sensor architecture provides low image lag pixels and high blue response.
The IL-P3 sensor’s superior performance makes it ideally
suited for applications requiring maximum speed and high
resolution, such as:
n High performance document scanning
n Inspection
n Optical character recognition
Functional Description
The IL-P3 sensor is composed of three main functional
groups: surface gated photodiodes in which the signal
charge packets are generated, a single CCD readout shift
registers, and an output amplifier where the charge packets
are converted to voltage pulses.
2
ISO 9001
TCK
CR1 CR2
Yes
No
1.
2.
7
1
7
1
Refer to Figure 7 for details.
PR = Pixel Reset (exposure control).
Detection
The IL-P3 series includes sensors with 512, 1024, or 2048
pixels with active imaging area lengths of 7, 14, and 28mm,
respectively. Photoelements are 14µm square for a photo2
sensitive area of 196µm and a 1:1 aspect ratio. Light incident on these photoelements is converted into charge
packets whose size (i.e., number of electrons) is linearly dependent on the light intensity and the integration time. The
charge is collected into a separate storage well (VSTOR) adjacent to each photoelement. This helps to minimize image
lag, nonuniformities associated with the use of pixel reset,
and crosstalk between the photodiode and the CCD shift
register.
With exposure control disabled, integration time is the period between successive pulses of the transfer (TCK) clock.
Integration time can be further reduced with electronic exposure control using the pixel reset (PR) clock. The pixel
reset clock resets not the photoelements themselves but
the storage well adjacent to each photoelement. When PR
is clocked, the integration time becomes the duration between the falling edge of the PR clock and the rising edge of
the TCK clock.
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When PR is clocked, the PR pulse must be damped to produce a smooth PR pulse. If PR switches too rapidly, the uniformity of the OS signal will be affected by the PR clock
feedthrough. A current-drive PR clock circuit generally introduces less feedthrough than a voltage-drive circuit.
Antiblooming is always present when biases fall within the
specified operating conditions. By adjusting VSTOR however, the user has the added flexibility of selecting the antiblooming level (the signal level beyond which the additional
signal charge is drained away). A higher VSTOR bias results
in a higher antiblooming level.
Transfer
The TCK clock controls the transfer of electrons from the
storage well into the 2-phase buried-channel CCD readout
register. Transfer is from the storage wells into the CR1
phases of the readout register. The readout register is then
used to serially shift the charge packets to the high-speed
low-noise output amplifier.
The final phase of the readout register is connected separately to CRLAST. This provides the flexibility of timing the
transfer of signal charges to the output node. CRLAST is
normally clocked in phase with CR1, but may be delayed
(see Figure 4) to shift the sampled portion of the output
video away from clock feedthroughs.
All CR clocks operate with 50% duty cycle.
Additional details on driving the sensor are provided on Figure 7.
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IL-P3
Line Scan Sensors
Output
The signal charge packets from the readout shift register are
transferred serially from the last readout gate (CRLAST),
over the set gate (VSET), to a floating sense node diffusion.
The set gate isolates the sense node diffusion from the last
readout gate and the rest of the readout shift register. As
signal charges accumulate on the floating node diffusion, the
potential of this diffusion decreases. The floating node diffusion is connected to the input of a 2.5-stage low-noise amplifier, producing an output signal voltage on the amplifier
output (OS). The floating diffusion is cleared of signal charge
by the reset gate (RST) in preparation for the next signal
charge packet. The voltage level of the floating diffusion after each reset is determined by the output reset drain voltage (VOD). AC coupling the output is recommended to
eliminate the DC offset.
The output signal (OS) requires an off-chip load drawing approximately 10mA of load current. If the load capacitance
(CLOAD) is greater than 10pF, larger load current (up to the
18mA operating limit) may be required. As the load current
increases, the amplifier bandwidth increases. The amplifier
can also drive larger capacitive loads when the load current
is larger. We recommend however that just enough bandwidth be used since larger bandwidth also results in increased noise.
If an off-chip current load is not available, the amplifier output (OS) can be connected to a 1kW load resistor. The use
of a passive (resistive) load reduces the amplifier gain, resulting in lower responsivity and saturation output signal.
We do not recommend passive loads at data rates greater
than 25 MHz because variations in DC offset will result in
variations in bandwidth.
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3
ISO 9001
IL-P3
Line Scan Sensors
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Table 4. IL-P3 Absolute Maximum Ratings
Unit
Min.
Parameter
Max.
Storage Temp
°C
-20
80
Operating Temp
°C
-20
60
Voltage on CR1, CR2, VSTOR, TCK, PR, VLS with
respect to VBB
Voltage on OS, VDD, VOD, VSS, VPR, VHIGH,
CRLAST, RST, VSET, VLOW with respect to VBB
Voltage on OSn with respect to VSS
V
-10
18
V
0
18
V
VDD-8
VDD+1
Amplifier Load Current (ILOAD)
WARNING:
mA per output
20
Exceeding these values will void product warranty and may damage the device.
CAUTION! These devices are sensitive to damage from electrostatic discharge (ESD). The leads
should be shorted together during storage or handling to prevent damage to the device.
WARNING: To prevent damage to the sensor, a Schottky diode must connect
VBB and VSS. See Figure 7.
Input Characteristics:
Table 5. IL-P3 Input/Output Characteristics
Capacitance to VBB
Unit
Typical
1
from CR1, CR22
from CRLAST
from RST
from PR
from TCK
pF
pF
pF
pF
pF
512
1024
2048
70
9
7
31
20
125
9
7
53
36
250
9
7
99
70
Output Characteristics:
Output Impedance (ROUT)3
Amplifier Supply Current (IDD) 4
DC Output Offset (VOS) 5
Notes:
W
mA
V
130W with ILOAD = 10mA
14mA with ILOAD = 10mA
8.3V with ILOAD = 10mA
1.
2.
Using 1V pk-pk 1MHz signal with +5V DC offset.
The two CR1 pins (pins 17 and 18) are internally connected, as are the two CR2 pins (pins 15 and 16).
3.
4.
5.
-0.389
, ILOAD in mA.
In general, ROUT(W) ~ 324 * (ILOAD)
In general, IDD (mA) = 4 + ILOAD, ILOAD in mA.
2
In general, VOFFSET (V) = 0.0018 * (ILOAD) - 0.17 * (ILOAD) + 9.8, ILOAD in mA.
4
ISO 9001
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Line Scan Sensors
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Table 6. IL-P3 DC Operating Conditions
Unit
Min.
Rec.
Symbol
Description
ILOAD
VDD
VOD
VSET
VSTOR 2
VPR
VHIGH
VLOW
VBB3
VLS
VSS3
Load current to the output (OS)
Amplifier supply
Output reset drain
Output node set gate
Pixel storage gate
Pixel reset drain, guard ring
High bias voltage
Low bias voltage
Substrate
Light shield
Amplifier return
Notes:
1.
2.
3.
mA
V
V
V
V
V
V
V
V
V
V
7.5
13.5
12.0
0.7
1.1
13
13
-0.5
-2.5
1
10.0
14.0
12.5
1.2
1.5
14
14
0
-2
VBB
0
Max.
18.0
15.0
13.0
1.4
1.7
15
15
15
-1.5
When deviating from the recommended biases, ensure that the new biases still meet the essential conditions on
Table 8.
VSTOR may be adjusted to affect the antiblooming level. VSAT decreases by ~ 870mV for every 1.0V reduction in
VSTOR.
VBB should never be forward biased with respect to VSS. To protect against damage, a Schottky diode between
VBB and VSS is recommended (see Figure 7).
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IL-P3
Line Scan Sensors
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Table 7. IL-P3 AC Operating Conditions
Symbol
Description
CRx
All CR Clocks
RST2
Reset Clock
TCK
Transfer Clock
PR
Pixel Reset Clock
ƒDATA3
ƒLINE4
Data rate
Line rate
Notes:
1.
2.
3.
4.
Unit
low*
swing*
low
swing
low
high
low
swing
0512
1024
2048
V
V
V
V
V
V
V
V
MHz
kHz
1
Min.
Rec.
0
5.0
0
7.0
-3.5
5.0
0
4.0
4.8
7.0
-5.0
4.5
3.5
5
Max.
6.5
9.0
-3.5
6.0
6.0
45
82.3
42.5
21.6
When deviating from the recommended biases, ensure that the new biases still meet the essential conditions on
Table 8.
If it is important that RST have a 5-V swing, an alternate set of biases is available. Contact DALSA for additional
information. The alternative biases result in a reduction of either the antiblooming performance or VSAT.
The minimum data rate can be lower than 5MHz if 100x antiblooming is not required.
Unless the pixel is reset using the PR clock, the integration time increases as line rate decreases. Dark signal is
proportional to the integration time. The minimum line rate is determined by the maximum dark signal or the
maximum dark signal shot noise that the application can tolerate.
*
Table 8. IL-P3 Essential Bias Conditions
Conditions
If condition not satisfied, the sensor will exhibit…
CR1 high + 1 > TCK > VSTOR + 3
PR high > VSTOR + 1.5
RST high + 5.5 > VOD
VOD < VDD - 1.5
VLOW > VBB + 2
6
ISO 9001
Larger lag
High PRNU when exposure control is enabled
Poor MTF
Higher non-linearity
Spurious charge injection under certain power-up
conditions
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Line Scan Sensors
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Specification
Table 9. IL-P3 Performance Specifications
Unit
Min.
Saturation Output Voltage (VSAT)1
rms Noise
Wavelength of Peak Responsivity
Peak Responsivity
Dynamic Range
Charge Conversion Efficiency (CCE)
Noise Equivalent Exposure (NEE)
Saturation Equivalent Exposure (SEE)
Full Well Capacity1
Fixed Pattern Noise (FPN) 2,3
Photoresponse Non-Uniformity (PRNU) 4
8 pixel local neighborhood
mV
mV
nm
V/(µJ/cm2)
-
µV/e
pJ/cm2
nJ/cm2
kemV
680
41.3
1420:1
8.8
9
15
73
% OS
Global
Charge Transfer Efficiency (CTE) (readout register)
First Field Lag 5
Dark Signal, Integration time = 52µs
Notes:
1.
2.
3.
4.
5.
mV
mV
0.99997
3.1
Typ.
Max.
800
0.44
700
43.7
1820:1
9.3
10
18
86
< 0.5
930
0.48
46.5
2110:1
9.9
12
3.0
6.5
5.0
8.5
0.999999
4.3
0.19
5.4
0.22
1.0
VSTOR can be adjusted to increase VSAT and full well. As these quantities increase, the antiblooming capability is
compromised.
Maximum peak-to-peak variation of all outputs.
Due to its general purpose design, DALSA's camera and sensor evaluation hardware provides an output that cannot
be used to directly measure low FPN.
The peak-to-peak variation is measured at ~50% SEE.
Lag is measured at 500 mV. Lag is lower if signal is lower.
Test Conditions:
n
n
n
n
n
n
Operating temperature = 35°C.
ƒRST = data rate per output = 40MHz.
ILOAD = 10mA.
CLOAD = 10pF.
Tungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter.
See Sensor Measurement Definitions (doc# 03-36-00149) for specification definitions.
Life Support Applications
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. DALSA customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such
improper use or sale.
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Line Scan Sensors
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50
45
40
35
30
25
20
15
10
5
0
400 500 600 700 800 900 1000
Wavelength (nm)
Responsivity
100µW/cm2 25µW/cm2
100
Signal Output
(%)
Saturation Output
2
Responsivity [V/(µJ/cm )]
Figure 2. Performance Measurements
80
60
40
20
10µW/cm2
0
0.2 0.4 0.6 0.8 1.0
Integration Time (ms)
Output vs. Integration Time
(@700nm)
Table 10. IL-P3 Timing Parameters
Unit
Min.
Symbol Description
Rec.
Max.
tCR
Period of CRx clocks
t1
Integration time (PR disabled)
t2
Integration time (PR enabled)
t3
TCK to first valid pixel
pixels
24
t4
Overclock pixels
pixels
0
t5
CRLAST rising edge to CR2 falling edge
ns
-0.25tCR
0
t6
TCK high overlap with CR1 high
ns
200
200
t7
TCK falling edge to CR1 falling edge
ns
2
t8
CRLAST rising to RST rising edge
ns
-0.25tCR
0.5tCR - t11
0.5tCR - t11
t9
RST falling edge to CRLAST falling edge
ns
0
0
0.5tCR-t11
t10
RST pulse width (FWHM)1
ns
3.5
5
0.25tCR
t11
CR rise and fall time
ns
1
2
0.25tCR
24
2
Notes:
1.
0.25tCR
Full Width Half Maximum
8
ISO 9001
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Line Scan Sensors
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Figure 3. IL-P3 Overall Timing
CR1
CR2
CRLAST
t1
TCK
RST
t2
PR
OS
Line 1
Line 2
Active Pixels
t3
Line 3
t3
t4
Figure 4. IL-P3 Detailed Readout Register Timing
t7
CR1
t11
t11
tCR
t5
CR2
t9
CRLAST
t6
t8
TCK
t11
t11
t10
RST
OS
Overclock Overclock
Pixel
Pixel
Isolation
Pixel
Isolation
Pixel
Figure 5. IL-P3 Gate Structure Diagram
VPR
PR
VDD
Pixel
OS
VSTOR
n+
VSS
TCK
n+
CR1
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CR2
CR1
CR2
CRLAST VSET
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n+
RST
VOD
9
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IL-P3
Line Scan Sensors
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10
ISO 9001
Isolation Pixel.
I
S Light-Shielded Pixel.
OC Overclock Pixel.
Sample video
OS
RST
TCK
CRLAST
CR2
CR1
OC
OC
I1
I16
S2
S6
I17
I18
Pixel
1
Pixel
2
Pixel
N-1
Pixel
N
I19
I20
OC
Figure 6. IL-P3 Readout Register Timing
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CR22=CR1
CR11
PR
(with
exposure
control)
TCK
Low-speed
Low-voltage
Clock Drivers
RST
Glitch Circuit
(PINS 4, 11)
TCK
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OS
+
-
(PIN 2)
VSTOR
VSTOR5
ILOAD
BIAS
(PIN 9)
VSET
OS Buffer
(PIN 6, 20)
(PIN 22)
VLS
VLS
(PINS 19)
VBB
VSET
VBB
(PIN 1)
(PIN 12)
VSS
VLOW
VLOW
(PIN 3)
(PIN 24)
VPR,VHIGH (PINS 8, 13)
(PIN 5)
(PIN 23)
RST
PR
(PINS 15, 16)3
VDD
VSS
(PINS 17, 18)3
(PIN 21)
Figure 7. IL-P3 Sensor Operation Connections
CR2
CR1
CRLAST
IL-P3
VOD
10W
1kW
50W
Schottky diode
Possible
Interface
Circuitry
VDD4
VPR,
VHIGH
Non-Critical
DC Bias
VOD
VSS
(without
exposure
control)
Regulated
DC Bias
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IL-P3
Line Scan Sensors
ISO 9001
11
IL-P3
Line Scan Sensors
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Notes to Figure 7.
1.
2.
3.
4.
5.
Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total
capacitances of CRLAST and CR1 (see Table 5) exceed CMAX, more than one CR1 driver is required.
Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total
capacitances of CR2 (see Table 5) exceed CMAX, more than one CR2 driver is required.
Each pin should be connected to a clock driver, though not necessarily to the same clock driver. If more than one
clock driver is used, it is acceptable to drive each pin from separate drivers.
Need to source IDD = 4 + ILOAD mA.
May have an optional antiblooming level adjustment.
ISO 9001 DALSA maintains a registered quality system meeting the ISO 9001 standard.
12
ISO 9001
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Line Scan Sensors
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0.085±0.007 [2.2±0.2]
0.040±0.004 [1.0±0.1]
0.025±0.003 [0.6±0.1]
1.669±0.012 [42.4±0.3]
Pin 24
Pin 13
0.018±0.002 [0.5±0.1]
0.100±0.005 [2.5±0.1]
0.190±0.020 [4.8±0.5]
1.100±0.005 [27.9±0.1]
0.085±0.007 [2.2±0.2]
0.040±0.004 [1.0±0.1]
0.025±0.003 [0.6±0.1]
1.669±0.012 [42.4±0.3]
Pin 24
Pin 13
Pin 12
Pin 1
0.040±0.002 [1.0±0.1]
0.016±0.002 [0.4±0.1]
0.284±0.010 [7.2±0.3]
0.834±0.010 [21.2±0.3]
1.100±0.005 [27.9±0.1]
NOTES: 1) THE DIE IS PLACED IN THE MIDDLE OF
THE PACKAGE ±0.010[±0.3]
2) THE CENTER OF THE ACTIVE AREA VS THE
CENTER OF THE DIE IS dx=575um AND dy=-65um
RESPECTIVELY
0.190±0.020 [4.8±0.5]
0.018±0.002 [0.5±0.1]
0.100±0.005 [2.5±0.1]
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UNITS: IN.[mm]
0.300±0.010 [7.6±0.3]
0.148±0.010 [3.7±0.3]
0.295±0.005 [7.5±0.1]
0.059±0.002 [1.5±0.1]
NOTES: 1) THE DIE IS PLACED IN THE MIDDLE OF
THE PACKAGE ±0.010[±0.3]
2) THE CENTER OF THE ACTIVE AREA VS THE
CENTER OF THE DIE IS dx=575um AND dy=-65um
RESPECTIVELY
0.050±0.010 [1.3±0.3]
0.040±0.002 [1.0±0.1]
0.016±0.002 [0.4±0.1]
0.284±0.010 [7.2±0.3]
0.834±0.010 [21.2±0.3]
1024
0.300±0.010 [7.6±0.3]
Pin 12
Pin 1
0.050±0.010 [1.3±0.3]
0.059±0.002[1.5±0.1]
0512
0.148±0.010 [3.7±0.3]
0.295±0.005 [7.5±0.1]
Figure 8. IL-P3 Package Dimensions
UNITS: IN.[mm]
DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746
13
ISO 9001
IL-P3
Line Scan Sensors
0.085±0.007 [2.2±0.2]
0.040±0.004 [1.0±0.1]
0.025±0.003 [0.6±0.1]
1.669±0.012 [42.4±0.3]
Pin 24
Pin 13
0.040±0.002 [1.0±0.1]
0.016±0.002 [0.4±0.1]
0.284±0.010[7.2±0.3]
0.834±0.010[21.2±0.3]
1.100±0.005 [27.9±0.1]
UNITS: IN.[mm]
NOTES: 1) THE DIE IS PLACED IN THE MIDDLE OF
THE PACKAGE ±0.010[±0.3]
2) THE CENTER OF THE ACTIVE AREA VS THE
CENTER OF THE DIE IS dx=575um AND dy=-65um
RESPECTIVELY
14
ISO 9001
0.190±0.020 [4.8±0.5]
0.018±0.002 [0.5±0.1]
0.100±0.005 [2.5±0.1]
0.300±0.010 [7.6±0.3]
Pin 12
Pin 1
0.050±0.010 [1.3±0.3]
0.059±0.002 [1.5±0.1]
2048
0.148±0.010 [3.7±0.3]
0.295±0.005 [7.5±0.1]
For product information and updates visit www.dalsa.com
DALSA INC.: Phone: 519-886-6000 Fax: 519-886-8023
DALSA EUROPE: Phone: +49-8142-46770 Fax: +49-8142-467746
03-36-00166-06
www.dalsa.com