8
r.
ANALOG
L.III DEVICES
CMOS
10-BitMonolithic
AID Converter
FEATURES
8- and 10-Bit Resolution
20llS Conversion Time
Microprocessor Compatibility
Very Low Power Dissipation
Parallel and Serial Outputs
Ratiometric Operation
TTL/DTL/CMOS Logic Compatibility
CMOS Monolithic Construction
OBS
8
GENERAL
8
8
DESCRIPTION
OLE
FUNCTIONAL
The AD7570 is a monolithic CMOS 10-bit successive approximation AID converter on a 120 by 13 5 mil chip, requiring
only an external comparator,
reference and passive clocking
components.
Ratiometric
operation is inherent, since an extremely accurate multiplying DAC is used in the feedback loop.
The AD7570 parallel output data lines and Busy line utilize
three-state logic to permit bussing with other AID output and
control lines or with other I/O interface circuitry. Two enables
are available: one controls the two MSBs; the second controls
the remaining 8 LSBs. This feature provides the control interface
for most microprocessors
which can accept only an 8-bit byte.
The AD7570 also provides a serial data output line to be used
in conjunction
with the serial synchronization
line. The clock
can be driven externally or, with the addition of a resistor and
a capacitor, can run internally as high as 0.6MHz allowing a
total conversion time (8 bits) of typically 201ls. An 8-bit short
cycle control pin stops the clock after exercising 8 bits, normally used for the "J" version (8-bit resolution).
The AD7570 requires two power supplies, a +15V main supply
and a +5V (for TTL/DTL logic) to + 15V (for CMOS logic)
supply for digital circuitry. Both analog and digital grounds
are available.
DIAGRAM
OUT1
AIN
VREF
TE
OUT2
I
I
10
,..,....--0 DB9 (MSB)
DB8
18
DB1
19
28
DBO (lSBI
BUSY
8
SRO
CaMP
STRT
ClK
27
20
SUCCESSIVE
APPROXIMATION
lOGIC
21
9
L-221-13l-1l-6T220
Vcc
236
16
DGND voo
BSEN
HBEN
lBEN
- SYNC
-l
66
AGND
The AD7570 is a monolithic device using a proprietary
CMOS
process featuring a double layer metal interconnect,
on-chip
thin-film resistor network and silicon nitride passivation
ensuring high reliability and excellent long term stability.
8
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringementS of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
--
P.O. Box 280;
Tel:617/329-4700
Telex: 924491
Norwood,
Massachusetts 02062 U.S.
Twx: 710/394-65'
Cables: ANALOG NORWOODMA:
(VOO 0=+15V, VCC 0=+5V, VREF0=:!:lOV unless otherwise
SPECIFICATIONS
VERSIONS
PARAMETERI
ACCURACY
Resolution
OVER SPECIFIED
TEMP. RANGE
TA = +25°C
'
noted)
TEST CONDITIONS
'--
-
J
L
J, L
1.L
J, L
J, L
----------------
8 Bits min
10 Bits min
:!:1/2LSB max
ILSB max
J, L
L
J, L
J, L
10kQ typ
-150ppm/C
typ
10kQ typ
-I 5.9"p_n1/C- ty I' ---------------
J, L
J, L
1.L
1.L
J, L
lUnA typ
120pF typ
40pF typ
40pF typ
120pF typ
VINL2
VINH2
IINL' IINH 3
CLK Input Current
1.L
J, L
J, L
J, L
J, L
J, L
+1.4V
+2.4V
+1.5V
:!:O_IIlA typ, :!:IOIlA max
+0.4011\ typ, +lmA max
VIN = 0 to VCC
During Conversion Vcc = +5V;
2_4V « VIN « Vcc
CLK
J, L
+1.7m1\
1.L
:!:IIlA typ
During Conversion VCC = +15V;
10V « VIN « VCC
Vcc = +5V to +15V
Conversion Complete or CLK IN
« VINL
J, L
2pF typ
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Temperature
ANALOG INPUTS
Coefficient
Analog Input Resistance
Analog Input Resistance Tempco
Reference Input Resistance
Reference Input Resistance Tempco
ANALOG OUTPUTS
Output Leakage Current
(OUT!, OUT2)
Output Capacitance OUTI
OUT2
OUT!
OUT2
1.
8
5ppm Reading per 0 C typ
10ppm Reading per
--------.-.----------.-------
0
C max
5kQ Olin, 20kQ max
5kQ min, 20kQ max
200nA
max
Voun, 2 = OV
DBOthrough DB9 = Logic "I"
DBO through DB9 = Logic "0"
----------.-
INPUTS
VINL 2
VINH2
Input
Current
CLK Input Current
Cm
u
DIGITAL
---.
OUTPUTS
J, L
1.L
1.L
J, L
J, L
VOUTL
YOUTH
VOUTL
YOUTH
CoUT (Floating)
(SYNC, SRO,
DBO thro~gh
BUSY,
LBEN, HBEN Propagation
tON
IoFF
BSEN Propagation
tON
tOFF
Duration
+ 1.5V max
+ 13.5V min
Requirement
Vcc = +15V
OLE
+13-5V
min
typ,
+3mA
max
+0.5V max
+2.4V min
+1.5V max
+13.5V min
5pF typ
+0_8V max
+2.4V
+1.5V
+13.5V
min
max
min
TE
Vcc = +5V, ISINK = 1.6mA
VCC = +5V, IsOURCE = 40llA
VCC = +15V, ISINK = 3mA
VCC = +15V, ISOURCE = ImA
VCC = +5V to +15V
SRO and SYNC; Conversion
Complete
BUSY; BSEN = Logic "0"
DBO-DB9; HBEN, LBEN =
Logic "0"
VCC = +5V to +15V
SRO and SYNC; Conversion
Complete
BUSY; BSEN = Logic "0"
DBO-DB9; HBEN, LBEN =
Logic "0"
VOUT = OV and VCC
J
L
J, L
20lls typ, 40lls max
40lls typ, 120lls max
100kHz typ
1.L
100kHz typ
J, L
1.L
650ns typ
200ns typ
J, L
1.L
450ns typ
200ns ryp
40lls
I
t
See Figure 5
Vcc = +5V; CLK Duty Cycle =
50%, R = 33k, C = 760pF
VCC = +15V, CLK Duty Cycle =
50%, R = lOk; C = 2500pF
Vcc = +5V
LBEN, HBEN = OV to +3V
Data Bit Load = 5k, 16pF
Measured from 50% of Enable
Input to 50% Point of Data
Bit Output
Delay
J, L
max
I
120llS max
Delay
(STRT)4
Vcc = +5V
Olin
:!:5nA typ
Internal CLK Frequency
(See Figure 2, and Section 6
of Pin Function Description)
Start
+2.4V
and
DYNAMIC PERFORMANCE
Conversion Time
Convert
+0_8V max
typ, +0.8V max
min, + 1.4V typ
max
DB9)
ILKG (Floating)
(SYNC, SRO, BUSY and
DBO through DB9)
Pulse
SC8 = Logic "0"
SC8 = Logic "I"
fCLK = 100kHz
See Figure 5
0.3% Reading typ
OBS
DIGITAL
8 Bits min
10 Bits min
:!:1/2LSB max
ILSB max
Vcc = +5V
BSEN = OV to +3V
BUSY Load = 5k, 16pF
Measured from 50% Point of
BSEN Input Waveform to 50%
Point of BUSY Output Waveform
,
'
-~
0.51ls Olin
.--
~
"
-2--
W
i
-
----------
8
PARAMETER
VERSIONS
I
- ------
TA
OVER SPECIFIED
TEMP_RANGE
~ +25°C
TEST CONDITIONS
POWER SUPPLIES
VDD
VCC
IDD
J. L
J. L
J. L
+5V to +15V typ
+5V to VDD typ
0.2mA typo 2mA max
See Figures 3 and 4
Icc
J. L
0.02mA typ, 2mA max
VCC ~ +5V. fcLK ~ 0 to 100kHz
Continuous
Conversion
(80% Duty
J, L
O_lmA typ, 2mA max
VCC = +15V,
Continuous
Cycle)
VDD ~
+15V,
Continuous
Cycle)
fCLK ~ 0 to 100kHz
Conversion
(80% Duty
Cycle)
fcLK = 0 to 100kHz
Conversion
(80% Duty
, "J" version parameters specified for SC8 ~ O.
VJNL and VJNH specifications applicable to all digital inputs except COMP. COMP terminal must be driven with CMOS levels (i.e., comparator
output pullup must be tied to VCc).
'IJNL,IJNH specifications not applicable to CLK terminal. See "CLK input current" in specifications table.
. STRT falling edge should not coincide with CLK in falling edge.
2
..
OBS
Specifications
subject to change without notice.
8
ABSOLUTE
8
MAXIMUM
OLE
RATINGS
VootoGND
VcctoGND
VcctoVOO"""""""""""""'"
VREFtoGND
AnaloglnputtoGND
Digital Input Voltage
Range.
ORDERING INFORMATION
+17V
+17V
+OAV
:t25V
:t25V
Resolution
----
8-Bit
la-Bit
. . . . . . . . . . . . . VOO to GND
'oUTl,'oUTZ
O.3V,VoO
Power Dissipation (package)
upto+50°c
IOOOmW
Derate above +50°C by. - . . . . . . . . . . . . . . . . . . IOmW/C
Operating Temperature.
. . . . . . . . . . . . . . . -25°C to +85°C
Storage Temperature.
. . . . . . . . . . . . . . . -65°C to +150°C
Suffix D:
PIN CONFIGURATION
8
CAUTION:
apply
voltages
higher
GND to any input/output
or AIN.
than
terminal
V cc or less than
except
VREF
2. The digital control inputs are zener protected; however
permanent
damage may occur on unconnected
units
under high energy electrostatic
fields. Keep unused
units in conductive foam at all times.
Range
to +85°C
AD7570j
AD7570L
Ceramic
Package
1.
2a
rmw
VREF
27
BSEN
AIN
26
oun
25
STAT
OUT2
24
ClK
AGND
23
DGND
COMP
22
Vcc
SAD
21
lBEN
20
HBEN
SYNC
(MSB)DB9
DBa
DB7
3. Vcc should never exceed Voo by more than OAV,
especially during power ON or OFF sequencing.
8
-
-25°C
TOP VIEW
VDD
1. Do not
TE
Temperature
-3-
10
11
12
19
DBa IlSB)
18
DBI
17
DB2
DB6
16
DB3
DB5
15
DB4
TYPICAL PERFORMANCE CHARACTERISTICS
1000.0
+0.25
VDD : +15V
CLK IN : 0 TO +3V (VCC : +5VI,
0 TO +15V IVcc : +15VI
CONVERSION.TO.STANDBY DUTY CYCLE:
HBEN, LBEN, BSEN, COMP,
100,0
+0.20
80%
+0.15
SClf. Vcc
:
>-
AD7570J
~
t
+0,10
~
~
.y
;::. +0.05
~'jj
0'"
z=
0
10.0
0
_0
<!~
~', -0.05
~
-0.10
is
-0,15
~
1.0
}AD7570L
.0.20
0.1
100
lk
10k
-0,25
lOOk
5
10
CLOCK FREOUENCY - H,
OBS
Figure "
IDD, Ice vs. fCLK at Different
Temperatures
Figure
1M
VDD: +15V
TA:25C
,
Vcc
~
u
R
10k
~
~
~
22
24
C
GENERATING
[
lk
10
AD7570
INTERNAL CLK
Differential
~
."
2.
fCLK vs. Rand
Cat
15
Nonlinearity
vs. VDD
8
0.25
~
" 0.20
,
0:
0
0:
0:
w
z
0.15
0.10
0.00
10k
5
Vce = +5V, +15V
Figure
4,
TE
10
pF
VDD
Figure
14
0.30
lk
-
3,
0.05
II
CAPACITANCE
13
0.35
~
100
12
OLE
lOOk 1---,-
:I:
11
VDD - VOL TS
-
11
12
14
15
VOL TS
Gain Error vs. VDD (Normalized
TEST CIRCUITS
-10V
13
8
for VDD = 15V)
8
+15V
0 TO .10V
+5V
SW.l
3k
--
BIT 1
I (MSBI
~3
I BIT 10
-
BIT 11
LBENI 21
12 BIT
DAC
HBEN
20
BSEN
27
BIT 12
1M
250k
(LSBI
10 BIT
TEST
rv
8 BIT
TEST
ANALOG DITHER INPUT
5-40 H, SINE WAVE.
lOV P1'
100kH,
DUT 23
10.BIT,
TEST
sc8126
AD7570
8B'J1,
TESV
7
161 DB3
18
..9:.!i
CLOCK
STRT
CONVERT START
0.5", PULSE DN 130", INTERVALS. TRAILING
EDGE SYNCED TO CLOCK LEADING EDGEI
D80 (LSB)
24
19
25
28 I BUSY
10 BIT TEST
OSCILLOSCOPE
20k
HORIZONTAL
(X) INPUT
NOTE, ADJUST COMPARATOR
6
01
02
VERTICAL
(YI INPUT
10k
IAD311 I OFFSET TO LESS THAN O1mV.
e
DUAL "D"
TYPE LATCH
Figure 5. Dynamic Crossplot Accuracy Test
-4III
8
PIN FUNCTION
DESCRIPTION
8. Vcc (pin 22)
Vcc is the logic power supply. If +5V is used, all control
inputs/outputs (with the exception of comparator terminal)
are DTL/TTL compatible. If +15V is applied, control
inputs/outputs are CMOS compatible.
INPUT CONTROLS
1. Convert Start (pin 25 - STRT)
When the start inpu t goes to Logical" 1 ", the MS B data
latch is set to Logic "1" and all other data latches are set to
Logic "0". When the start input returns low, the conversion
sequence begins. The start command must remain high for
at least 500 nanoseconds.
If a start command is reinitiated
during conversion,
the conversion
sequence
OUTPUT
1. Busy (pin 28 - BUSY)
The Busy line indicates whether conversion is complete or
in process. Busy is a three-state output and floats until the
Busy-Enable line is addressed with a Logic "1 ". When
addressed, Busy will indicate either a "1" (conversion complete) or a "0" (conversion in process).
starts over.
2. High Byte Enable (pin 20 - HBEN)
This is a three-state enable for the bit 9 (MSB) and bit 8.
When the control is low, the output data lines for bits
9 and 8 are floating. When the control is high, digital
data from the latches appears on the data lines.
~
~
~
OBS
8
<8
3. Low Byte Enable (pin 21 - LBEN)
Same as High Byte Enable pin, but controls
through 7.
2. Serial Output (pin 8
bits 0 (LSB)
4. Busy Enable (pin 27 - BSEN)
This is an interrogation
input which requests the status of
the converter, i.e., conversion in process or convert complete. The converter status is addressed by applying a Logic
"1" to the Busy Enable. (See Busy under Output Functions.)
SRO)
OLE
3. Serial Synchronization (pin 9 - SYNC)
Provides 10 positive edges, which are synchronized
to the
Serial Output pin. Serial Sync is floating if conversion is
not taking place.
5. Short Cycle 8 Bits (pin 26 - SCS)
With a Logic "0" input, the conversion stops after 8 bits
reducing the conversion time by 2 clock periods. This
control should be exercised for proper operation of the "J"
version. When a Logic "1" is applied, a complete 10-bit conversion takes place ("L" version).
shows
the
is <4.75V,
internal
CLK
the internal
frequency
versus
Rand
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C. If V cc
CLK will not operate.
(
R
24
TE
Note that all digital inputs/outputs
are TTL/DTL
when Vcc is +5V, and CMOS compatible
+5V
AD7570
CI
Generating Internal Clock Frequency
8
-
Provides output data in serial format. Data is available only
during conversion. When the A/D is not converting, the
Serial Output line "floats." The Serial Sync (see next function) must be used, along with the Serial Output terminal
to avoid misinterpreting
data.
6. Clock (pin 24 - CLK)
With an external RC connected, as shown in the figure
below, clock activity begins upon receipt of a Convert-Start
command to the A/D and ceases upon completion of conversion. An external clock (CMOS or TTL/DTL levels) can
directly drive the clock terminals, if required. Figure 2
8
FUNCTIONS
7. VDD (pin 1)
VDD is the positive supply for all analog circuitry plus some
digital logic circuits that are not part of the TTL compatible
input/output
lines (back-gates to the P-channel devices).
Nominal supply voltage is +15V.
MNEMONIC
VDD
VREF
AIN
oun
OUT2
AGND
COMP
SRO
SYNC
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBO
HBEN
LBEN
VCC
DGND
CLK
STRT
SC8
BSEN
BUSY
FUNCTION
Positive Supply (+ 15V)
Voltage REFerence (:t10V)
Analog INput
DAC Current OUTput 1
DAC Current OUTput 2
Analog GrouND
COMParator
SeRial Output
Serial SYNChronization
Data Bit 9 (MSB)
Data Bit 8
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (LSB)
High Byte ENable
Low Byte ENable
Logic Supply (+ 5V to + 15V)
Digital GrouND
CLocK
STaRT
Short Cycle 8 Bits
BuSy ENable
BUSY
Table 1. Function
-5-
compatible
when VCC is +15V.
Table
FUNCTIONAL
ANALYSIS
BASIC DESCRIPTION
The AD7570
is a monolithic
CMOS AID converter
(STRT) goes HIGH, the MSB(DB9) is set to the Logic "1"
state, while DBO through DB8 are reset to the "0" state.
which uses
the successive approximations
technique to provide up to 10
bits of digital data in a serial and parallel format. Most AID
applications require the addition of only a comparator and a
voltage or current reference.
Two clock pulses plus 200ns after STRT retUrns LOW, the
MSB decision is made, and DB8 is tried. Each succeeding trial
and decision
8-BIT SHORT CYCLE NOTES
If the AD7570 is short cycled to 8 bits (SC8 = OV), the
following will occur:
OBS
Each successive bit is tried, compared to AIN, and set or reset
in this manner until the least significant bit (DBO) decision is
made. At this time, the AD7570 output is a valid digital representation of the analog input, and will remain in the data
latches until another convert start (STRT) is applied.
DESCRIPTION
1. The SYNC terminal
output pulses.
II
STRT2
OLE
,
SROS,8
0B87
:///////1
IMSBI8 17 f6l
RY'DBB-!
OB77 ////////1
E
TRYDB7--/
OB67 ////////1
DB8DECISION
I~
DB7 DECISION
E
TRY DB6==:/
OB57 ///////~
TRY DB5
0B47 ////////1
DB6 DECISION
~
TRY DB4
OB37 :///////~
E
DB4 DECISION
E
TRY DB2==:1
OB17 ////////1
DB3 DECISION
EDB2
E
TRY DB1 ==:/
all////~
TRY LSB ==:/
BSEN2
BUSY
~
t
DBS DECISION
E
d
TRY DB3
OB27 ////////1
DBa (lSB)7
TE
t
!LSBr---------
5 14 13 1211
TRYMSB1-- MSBDECISION
////////1T
t
3. BUSY goes "high" one clock period after the DB2 (DB2 is
the LSB when short cycled) decision is made.
---------
SYNC3, 4,8
OB9 (MSB)6,7
will provide 8, instead of 10, positive
2. OBI goes "high" coincident with the LSB (DB2 is the LSB
when short cycled to 8 bits) decision, and remains high
until another STRT is initiated. DBO remains in the "0"
state.
Figure 6 is the AD7570 timing diagram, showing the successive
trials and decisions for each data bit. When convert start
ClK1
is made at tCLK + 200ns.
Serial NRZ data is available during conversion at the SRO
terminal. SYNC provides 10 positive edges which occur in the
middle of each serial output bit. SYNC out must be used in
conjunction
with SRO to avoid misinterpretation
of data.
Both SYNC and SRO "float" when conversion is not taking
place.
In the successive approximations
technique, successive bits,
starting with the most significant bit (DB9) are applied to the
input of the 01 A converter.
The DAC output is then compared to the unknown analog input voltage (AIN) using a zero
crossing detector (comparator).
If the DAC output is greater
than AIN, the data latch for the trial bit is reset to zero, and
the next smaller data bit is tried. If the DAC output is less
than AIN, the trial data bit stays in the "1" state, and the next
smaller data bit is tried.
TIMING
t
,
--
DECISION
DB1 DECISION
E
BUSY
DBO (LSBI DECISION
JCOMPLETE
CONVERT
L..- - - -
NOTES:
1.
2.
3.
4.
INTERNAL CLOCK RUNS ONLY DURING CONVERSION CYCLE (EXTERNAL CLOCK SHOWN!.
EXTERNALLY INITIATED.
SERIAL SYNC LAGS CLOCK BY '" 200ns.
DOTTED LINES INDICATE "FLOATING" STATE.
5. FOR ILLUSTRATIVEPURPOSES,SERIAL OUTSHOWNAS 1101001110.
6. CROSS HATCHING INDICATES "DON'T CARE" STATE.
7. SET AND RESET OF OUTPUT DATA BITS LAGS CLOCK POSITIVE EDGE BY '" 200ns.
8.
SHOWN
FOR sca
= 1.
Figure 6. AD7570 Conversion Timing Sequence
-6--
411
DYNAMIC
(8
~
PERFORMANCE
The upper clock frequency limitation (hence the conversion
speed limitation) of the AD7570 is due to the output settling
characteristics
of the current weighting DAC in conjunction
with the propagation
delay of the comparator,
not to speed
limitations in the digital logic.
DAC EQUIVALENT
CIRCUIT
The Df A converter section of the AD75 70 is a precision lO-bit
multiplying DAc. The simplified DAC circuit, shown in Figure
7, consists of ten single-pole-double-throw
current steering
switches and an "inverted"
R-2R current weighting network.
(For a complete description of the DAC, refer to the AD7520
data sheet.)
OBS
The output resistance and capacitance at OUTI (and OUT2)
are code dependent,
exhibiting resistive variations from 0.5
"R" to 0.75 uR", and capacitive variations from 40pF to
l20pF.
J
. , (8
10k
10k
VREF
20k
2Ok
.
-
.
I
I
oB9
8
10k
I
I
oB8
20k
I
I
oB7
Worst case settling requirements
occur when a trial bit causes
the OUTI terminal to charge towards a final value which is
precisely 1/2 LSB beyond zero crossing. When this occurs,
the trial bit must settle and remain within 1/2 LSB of final
val ue, or an incorrect
1. Load OUTI with a lk resistor.
the time
OLE
20k
2. Use a zero input impedance comparator.
Figure 9 illustrates
a comparator circuit which has an input impedance of
approximately
26D.. Proper circuit layout will provide
lO-bit accuracy for clock frequencies >500kHz.
20k
A / ANALOG
GNo
OUT2
TE
1
ClK IN
oun
COMPARATOR
INPUT
louni
NOTES'
TIME ANALYSIS
1 "',mUNG"
"1 . '01 IS THE TIME REOUIRED FOR THE oun
TERMINAL TO
SETTLE WITHIN .1/2LS6 OF THE FINAL VALUE.
2. "'COM'" 11, . 1, I IS THE COMPARATOR SWITCHING TIME
3 "'O'lAY"
11, - 1,IIS AN INTERNAllY
GENERATED TIME DELAY EOUAL TO
APPROXIMATEL Y 400 NANOSECONDS.
Due to the changing COUTI and ROUTl, the time constant
on OUTI falls anywhere between 250 and 900ns, depending
on the instantaneous
state of the AD7570 digital output code.
8
4
COMPARATOR
OUTPUT
IS LATCHES
Vcc
R2
1k
0.01%
R6
1k
OUT1
R4
I
OUT2
CaMP \AI
7.5k
0.05%
R5
100
7.5k
0.05%
R3U
!
-15V
Figure 9. Current Comparator With Low Input Impedance
-7-
AT
TIME
"
Figure 8. Expanded Timing Diagram
+5V
R1
1k
0.01%
(8
This reduces
constant by a factor of 10. Further reduction
of the lkD.
load reduces the amount of comparator
overdrive, thus increasing the comparator
propagation delay, resulting in a
reduction of available settling time (tl - to on Figure 8).
AIN
AD7570
will be made by the comparator.
For 10-bit accuracy, the first MSB must settle to within 0.1 %
of final value; the second MSB to within 0.2%. The LSB
settling requirement
is only 50% of the LSB value. Figure 8
illustrates the settling time available during a given clock
period. The pulse shown on the OUTI terminal falling midway between to and q is a feed through from internal clock
mechanisms and is due primarily to bonding wire and header
capacitance.
Two methods may be used to reduce the OUTI
settling time:
Figure 7. DAC Circuit
SETTLING
decision
OPERATION
UNIPOLAR
GUIDELINES
BINARY
ADJUSTMENT
OPERATION
Figure 10 shows the circuit connections required for unipolar
analog inputs. If positive analog inputs are to be quantized,
VREF must be negative, and the OUT1 (pin 4) terminal of the
AD7570 must be connected to the "+" comparator
input. For
negative analog inputs, VREF must be positive, and the OUT1
terminal connected to the "-" input of the comparator.
Gain Adjustment
1. Apply continuous
AD7570.
OPERATION
to the STRT input of the
t
to AIN.
as described
under zero offset
procedure above, and adjust the gain potentiometer
(R4)
until the LSB flickers between 0 and I, and all other data
bits equal "I". An alternate
instead of using R4.
method
is to adjust
VREF
vcc
+5V TO +15V
VDD
+15V
+15V
R2
3k
22
OBS
BINARY)
start commands
3. Observe the S RO terminal
The input voltage/output
code relationship for unipolar
operation is shown in Table 2. Due to the inherent multiplying
capability of the internal D/A converter, the AD7570 can accurately quantize full scale ranges of 10V to 1V. It should be
noted, however, that for smaller full scale ranges, the resolution and speed limitations of the comparator impose a
limitation on the maximum conversion rate.
(OFFSET
UNIPOLAR
2. Apply full scale minus 1-1/2LSB
For clarity, the digital control functions have been omitted
from the diagram. For proper use of the digital input/output
control functions, refer to the pin function description.
BIPOLAR
PROCEDURES
4
VREF. 2
~fJv
OPERATION
~N:ci"~~o~N
I oun
R3
20011
~
AD7570
t
3
R4
OLE
Figure 11 shows the AD7570 configured for offset binary
(modified 2's complement)
operation.
Input voltage/output
codes are shown in Table 3.
I
GAI~kADJ
Amplifier AI, in conjunction
with resistors R1, R2, and R3,
0ffsets the bipolar analog input by full scale, and reduces its
gain by a factor of 2. The analog signal applied to the AIN
terminal is, therefore, a unipolar signal of 0 to +V or 0 to -V,
depending on the polarity of VREF'
23
TE
NOTE:
IF POSITIVE VREF IS USED. THE ANALOG INPUT RANGE IS 0 TO -VREF. AND THE
COMPARATOR'S (-) INPUT SHOULD BE CONNECTED TO oun
(PIN 4) OF THE
AD7570.
Figure 10. Unipolar Operation
VREF
-10V
VDD
+15V
Vcc
+5V TO
+15V
t
+15V
R6
3k
R2
20k
20k
2
R3
10k
VREFI
R5
200
2
22
R5
4 rUTl1k
t
3
5 OUT2'
R1
AD7570
BIPOLAR
ANALOG
INPUT
AGND
3
+10V TO -10V
7
COMP
A
NOTE: IF POSITIVE VREF IS USED, CONNECT
TO oun
(PIN 4) OF THE AD7570.
Figure 11. Bipolar Operation
-8-
MINUS INPUT OF COMPARATOR
I
Analog Input
(AIN)
Digital Output
Code
Notes
MSB
LSB
1, 2, 3
FS - lLSB
FS - 2LSB
3/4 FS
1/2 FS + lLSB
1/2 FS
1/2 FS - lLSB
1/4 FS
lLSB
0
Analog Input
(AIN)
Notes 1, 2, 3
1111111111
+(FS - 2LSB)
+(1/2 FS)
1111111110
1000000000
+(1LSB)
0
1000000001
1000000000
01111
-(1LSB)
0111111111
-(1/2
0100000000
1000000001
11 111
0100000000
0000000001
0000000000
shown are nominal
(8
ADJUSTMENT
BIPOLAR
Gain Adjustment
center
0000000001
0000000000
NOTES:
1. Analog inputs
of code.
values
shown are nominal
2. "FS" is full scale; i.e., (VREF)'
3. For 8-bit operation,
lLSB equals
(Z-7); for to-bit operation,
lLSB
start commands
(-VREF)
to the STRT input of
OPERA TING PRECAUTIONS
1. Do not allow Vcc to exceed VDD' In cases where Vcc
could exceed VDD' the diode protection
scheme in Figure
12 is recommended.
2. Do not
HINTS
apply
voltages
greater
3. Load the OUTI
time constant
>50kHz.
terminal
Vcc
retUrns.
V cc or lower
Voo
HP5082-2811
at clock frequencies
22
(8
than
which can sup-
1N459,
1N914
with a 1k resistor to reduce the
when operating
than
from sources
3. Do not apply voltages (from a source which can supply
more than SmA) lower than ground to the OUTI or OUT2
terminal (see Figure 12).
1. Unused CMOS digital inputs should be tied to their appropriate logic level and not left floating. Open digital inputs
may cause undesired digital activity in the presence of noise.
should have separate
(-VREF)
equals
TE
ground to any digital output
ply >20mA.
2. Analog and digital grounds
values
6. If an external clock is used, the negative transition of STRT
should not coincide with the trailing edge of the clock
input.
3. Trim the gain potentiometer
R4 for a flickering LSB, and
all other data bits equal to Logic "1". Observe the SRO
terminal, as described in zero offset procedure above.
APPLICATION
center
(2-9).
OPERATION
2. Apply 1-1/2LSB less than positive full scale (FS = VREF)
to the bipolar analog input of Figure 11.
(8
FS)
OLE
(2-10).
PROCEDURES
1. Apply continuous
the AD7570.
1100000000
-(FS - lLSB)
-FS
2. "FS" is full scale, i.e., (-VREF)'
3. For 8-bit operation,
lLSB equals (-VREF)
(Z-8); for to-bit operation,
lLSB equals
(-VREF)
LSB
+(FS - 1LSB)
1100000000
Code
MSB
1111111110
NOTES:
1. Analog inputs
of code.
Digital Output
1111111111
OBS
(8
Table 3. Bipolar Operation
Table 2. Unipolar Operation
(8
4 .OUT1
4. For 10-bit operation, the comparator offset should be
adjusted to less than ImV. Each millivolt of comparator
offset will cause approximately
0.015% of differential
nonlinearity
when a 10V reference is used.
AD7570
5. The comparator
input and output should be isolated to
prevent oscillations due to stray capacitance. (See layout
on the next page).
Figure 12. Diode Protection Scheme
-9-
APPLICA nONS
OPTIMIZED LAYOUT
'j
t
i ~ ..
~
~
AD7570-t
oun
Ik LOAD
OBS
-
t
~
NOTES:
1. ALL PC TRACES ON BOTTOM OF BOARD.
2. LAYOUT SHOWN TERMINATES
oun
INTO + INPUT OF AD311 TYPE COMPARATOR.
IVREF
BUSING MULTIPLE
AD7570
.
OLE
-JOY. AIN'
OUTPUTS
0 TO +IOV).
Figure 13. PC Layout
(Top View)
TE
available at the AID output only after conversion is complete,
and until another "convert start" is initiated.
The timing
diagram of Figure 15 illustrates how the STRT signals of the
twelve AD7570's might be staggered to provide a total system
throughput
twelve times as great as the classic method of data
acquisition (an analog multiplexer feeding multichannel
analog
data to a single AID converter).
Several AD7570's may be paralleled to a data bus to provide
an AID converter per analog channel, this providing increased
system throughput
rate. For example, Figure 14 shows such
a system for 12 AD7570's in parallel.
The three-state output logic enables of each AD7570 is controlled by its own BUSY (status) outputs.
Thus, data is
STRT 1
t
.
OB9 (MSB)
BSEN1
I
I
AIN 1
LBEN
A07570
NO.1
t
lOBO (LSB) I
I
BUSY 1
CLK 0
--,
I
CLK
I/O
-11
DATA
STRn CD
REA01
BUSS.
VREF
BUSY 1
STRT12
STRn
OB9 (MSB)
.
I
I
AIN 12
A07570
LBEN
NO.
lOBO
(LSB)
I
12
READ1
BUSY2
STRT 12
~
REA02
~
---1L
READ 2
~
CONVERSION
IN PROCESS
n
CD
READ 12
I
BUSY
BUSY 12
3
CONVERSION IN PROCESS
NOTE: STRT SIGNAL 0.5!,s PULSE WIDTH, LEADING
EDGE SYNCHRONIZED TO CLK TRAILING EDGE.
NOTE:
~
CONVERSION IN PROCESS
CD
I
BSEN 12
~
L-
,OB9,OB8,OB7,OB6,OB5,084,OB3,OB2,081,OBO,
BSEN ON EACH A07570 IS "ENABLEO"
(LOGIC 1).
Figure 14. Busing Multiple AD7570's
Figure 15. Timing Diagram
-10-
~
8
MICROPROCESSOR
8
INTERFACE
3. LBEN is enabled, and the eight least significant data bits
(DBO-DB7) are applied to the data bus for subsequent transfer to the 8080. When the data transfer is complete, LBEN
is disabled, and DBO-DB7 return to their floating state.
Since most 8-bitmicroprocessors
utilize a bidirectio~al data
bus, each input peripheral (such as the AD7570) must be
capable of isolating itself from the data bus when other I/O
devices, memory, or the CPU takes control of the bus. The
AD7570 output data and status (BUSY) lines all utilize threestate logic to provide this requirement.
4. HBEN is enabled, and the two most significant AD7570 data
bits (DB8 and DB9) are applied to the data bus for subsequent transfer to the 8080. When the data transfer is
complete, HBEN is disabled, and DB8 and DB9 return to
their floating state.
Figure 16 illustrates a method of interfacing a TTY keyboard
and printer to the AD7570, using an 8080 microprocessor
as
the interface controller.
5. The 8080 (in conjunction
with the programmed
Read Only
Memory) performs a binary to decimal conversion.
The program (stored in Read Only Memory) waits for a keystroke on the TTY keyboard.
When a keystroke is detected,
an AID conversion is started. When conversion is complete,
the 8080 reads in the binary data from the AD7570, converts
it to ASCII, and prints out the decimal number (preceded by a
carriage return and line feed) on the teletype printer.
OBS
8
~
More specifically,
follows:
the main sequence
6. SWE (Status Word Enable) on the UAR/T transmitter
of events would be as
7. TDS (Transmitter
Data Strobe) strobes the converted
decimal number into the UAR/T transmitter
for subsequent
OLE
1. When a TTY keystroke is detected by the CPU (via the
UAR/T Receiver), a "convert start" (STRT) is applied to
the AD7570.
serial clocking into the keyboard.
The interface scheme shown below is only one example of a
myriad of possible data acquisition/control
systems which
could conveniently use the AD7570 to provide digital data to
a microprocessor
or minicomputer
bus.
2. BSEN is enabled, placing BUSY (conversion status) on the
data bus. When the 8080 detects BUSY = 1, conversion is
complete, and BSEN is disabled,
its floating state.
8
~
A15
causing BUSY to return
TE
to
A8
DBFLlN . MEMR . A2
I
DBFLlN . MEMR . A4
A7
ADDRESS
BUSS
AO
DBFLlN
HBEN
BSEN
8
~
AD7570 ADC
-,
(MSBI
BOSY DB9 8
7
,
. MEMR
DBFLlN
6
5
4
(lSB)
BDO
3
2
1
03
D2
D1
8080
DATA
BUSS
DO
DO-D7
DO
DO
D1
D7
Dol
UAR/T
RDAR
UAR/T
REC
RDE
SWE
XMT
WR
8
Figure
16.
. AO
TO PRINTER
. MEMR
. AO
:J1
ClK
O.MEMR
. SYNC
. MEMR . AT
Microprocessor
Controlled
-11..
Q
WR A2
DBFLlN
DBFLlN
D
TDS
DBFLlN
SYNC
DO
07'
MEMR
RSI
WR
DO D7 D6
XBMT
RDA
FROM
KEYBOARD
.
is
enabled, applying XBMT (Transmitter
Buffer Empty) to
the data bus. When a Logic "1" is detected by the 8080,
SWEis disabled, and XBMT returns to a floating state.
TTY IADC Interface
TERMINOLOGY
Resolution
Resolution is the relative value of the LSB, or Z-n for binary
devices, for n-bit converters.
It may be expressed as 1 part in
Zn, as a percentage, in parts-per-million,
or simply by "n bits."
Differential Nonlinearity
In a converter, differential linearity error describes the variation
in the analog value of transitions between adjacent pairs of
digital numbers, over the full range of the digital input or
output.
If each transition is equal to its neighbors (i.e., 1LSB),
the differential nonlinearity is zero. If a transition differs
from one of its neighbors by more than 1LSB (e.g., if, at the
transition OIl. .11 to 100. . .00, the MSB is low by 1.1LSB),
a DI A converter can be non-monotonic,
or an AID converter
Relative Accuracy
Relative accuracy error is the difference between the nominal
and actUal ratios to full scale of the analog value corresponding
to a given digital input, independently
of the full-scale calibration. This error is a function of the linearity of the converter,
and is usually specified at less than :!:l/2LSB.
4
using it may miss one or more codes. A sp,ecified maximum
differential nonlinearity
of 1 LSB ensures that monotonic
behavior exists.
Gain Error
The "gain" of a converter is that analog scale factor setting
that establishes the nominal conversion relationship, e.g., lOV
full scale. It is adjusted either by setting the feedback resistor
of a DAC, the input resistor in a current-comparing
ADC, or
the reference (voltage or current).
OBS
[2.j~1
M.AX
L
Output Leakage Current
Current which appears at the OUT1 terminal when all digital
output (DBO through DB9) are LOW, or on the OUTZ terminal
when all digital outputs are HIGH. The effect of output leakage
current will be on the offset of the AID converter.
OUTLINE
DIMENSIONS
shown in inches and (mm).
~~~~~c=J~~~~li~
.
1414[35921
138 135061'
I
"
~012
I
,
.
r
4
OLE
Dimensions
~.--
~
--11--
--1
f--
0.065
[1.661
0.02
10.5081
0105
[2671
0.045
[1151
0015
[0381}
0.095
12.42}
LEADS
~
0125
I
t
0.606
1--~--1
[1541
1
1318}
LEAD NO 1 IDENTIFIED BY DOT OR NOTCH
ARE GOLD PLATED [50 MICROINCHES
MIN[ KOVAR
OR ALLOY 42
[1531
L
TE
4
:::::::::
28 Pin Ceramic Dip
4
~
-12-