DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2147A01 DEFLECTION PROCESSOR 42-SDIP-600 The S1D2147A01is a monolithic integrated circuit assembled in a 42 pins shrunk dual in line plastic package. The goal of this IC is to control all the functions related to the horizontal and vertical deflection in multimodes or multisync monitors. FUNCTIONS • Positive or Negative sync polarities • Auto-sync horizontal processing • H-PLL lock/unlock identification • Auto-sync Vertical processing • East/West signal processing block • B+ controller ORDERING INFORMATION • Safety blanking output FEATURES Device Package Operation Temperature S1D2147A01-A0B0 42-SDIP 0 °C — 70°C (HORIZONTAL) • Dual Pll concept • Self-adaptative (30 to 70kHz) • X-ray protection input • DC adjustable duty-cycle • Internal 1st PLL lock/unlock information • Wide range DC controlled H-position • ON/OFF switch (for PWR management) • Two H-drive polarities (VERTICAL) • Vertical ramp generator (GENERAL) • 50 to 120Hz AGC Loop • Accept Positive or Negative Horizontal & Vertical sync polarities • DC controlled V-amp, V-pos, S-amp & S-centring • Separate H & V TTL input • ON/OFF Switch • Safety blanking output (B+ REGULATOR) (EWPCC) • Internal PWM generator for B+ current mode step-up conveter • Vertical parabola generator with DC • DC adjustable B+ voltage • controlled keystone & amplitude • Output pulse synchronised on horizontal frequency • Internal MAX current limitation 0 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS HSYNC 17 INPUT INTERFACE PLL1NHIB H-POS PLL1F R0 C0 FH-MIN HLOCK-CAP HFLY PLL2C H-DUTY H-OUTEM H-OUTCOL BLOCK DIAGRAM 35 15 12 11 10 14 13 3 1 2 20 21 1st PHASE COMP 2nd PHASE COMP VCO PHASE SHAPER OUTPUT BUTTER 23 SBLKOUT LOCK DETECT XRAY-IN 16 VREF HREF 4 26 V-VREF VGND VCC 24 - + EA - SAFETY PROCESSOR BANDGAP VREF B+ADJ 42 I SENSE 22 B+OUT 41 COMP 40 REGIN 36 E/WOUT 5 H-VREF HGND 39 R + S OUTPUT INHIBITION PARABOLA GENERATOR 1 19 18 27 25 29 28 33 31 30 32 38 37 VS-CENT VS-AMP V-POS V-AMP VOUT V DCOUT KEYST EW-AMP S CORRECTION VAGCCAP VERTICAL OSCILLATOR VCAP INPUT INTERFACE VCC 34 GND VSYNC DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2147A01 PIN CONFIGURATIONS PLL2C I-SENSE 42 2 H-DUTY COMP 41 3 HFLY REGIN 40 4 HGND B+ ADJ 39 5 HREF KEYST 38 6 NC E/W-AMP 37 7 NC E/WOUT 36 8 NC PLL1-INHIB 35 9 NC VSYNC 34 V-POS 33 V-DCOUT 32 V-AMP 31 VOUT 30 10 C0 11 R0 12 PLL1F S1D2147 1 13 HLOCK-CAP 14 FH-MIN VS-CENT 29 15 H-POS VS-AMP 28 16 XRAY-IN VCAP 27 17 HSYNC VREF 26 VAGCCAP 25 VGND 24 SBLK-OUT 23 B+ OUT 22 18 VCC 19 GND 20 H-OUTEM 21 H-OUTCOL 2 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS PIN DESCRIPTION Table 1. Pin Description Pin No Pin Name 1 PLL2C 2 H-DUTY 3 H-FLY 4 H-GND Horizontal section ground. Must be connected only to components related to H blocks. 5 H-REF Horizontal section reference voltage. Must be filtered by capacitor to pin 4. 6 NC 7 NC 8 NC 9 NC 10 C0 Horizontal Oscillator Capacitor. To be connected to pin 4. 11 R0 Horizontal Oscillator Resistor. To be connected to pin 4. 12 PLL1F 13 HLOCK-CAP 14 FH-MIN DC Control for free running frequency setting. Comming from DAC output or DC voltage generated by a resistor bridge connected between pin 5 and 4. 15 H-POS DC Control for Horizontal Centering 16 XRAY-IN X-RAY Protection input (with Internal latch function) 17 H-SYNC TTL Horizontal Sync Input 18 Vcc Supply Voltage (12V Typical) 19 GND Ground 20 H-OUTEM Horizontal Drive Output (emiter of internal transistor) 21 H-OUTCOL Horizontal Drive Output (open collector of internal transistor) 22 B+OUT 23 SBLK OUT Safety Blanking output. Activated during frequency changes, when X-RAY input is triggered or when VS is too low. 24 VGND Vertical Section Signal Ground 25 VAGCCAP 26 VREF 3 Description Second PLL Loop Filter DC Control of Horizontal Drive Output Pulse Duty-cycle. If this pin grounded, the horizontal and vertical outputs are inhibited. By connecting a capacitor on the this pin a soft-start function may be realized on h-drive output. Horizontal Flyback Input (Positive Polarity) First PLL Loop filter. To be connected to pin 4. First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the freqency change detected on pin 13. When frequency is changing, a blanking pulse is generated on pin 23, the duration of this pulse is proportionnal to the capacitor on pin 13. To be connected to pin 4. B+ PWM Regulator output Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2147A01 Table 1. Pin Description (Continued) Pin No Pin Name Description 27 VCAP 28 VS-AMP DC Control of Vertical S-Shape Amplitude 29 VS-CENT DC Control of Vertical S-Centering 30 V-OUT Vertical Ramp Output (with frequency independant amplitude and S-Correction) 31 V-AMP DC Control of Vertical Amplitude Adjustment 32 VDCOUT 33 V-POS 34 V-SYNC 35 PLL1INHIB 36 E/WOUT East/West Pincushion Correction Parabola Output 37 E/W-AMP DC Control East/West Pincushion Correction Amplitude 38 KEYST DC Control of Keystone Correction 39 B+ADJ DC Control of B+ Adjustment 40 REGIN Regulation Input of B+ Control Loop 41 COMP B+ Error Amplifier Output for Frequency Compensation and Gain Setting 42 ISENSE Sensing of External B+ Switching Transistor Emitter Current Vertical Sawtooth Generator Capacitor Vertical Position Reference Voltage Output Temperature matched with V-AMP output DC Control of Vertical Position Adjustment Vertical TTL Sync Input TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal) 4 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS ABSOLUTE MAXIMUM RATINGS NO Item Symbol Spec Unit 1 Supply Voltage (Pin 18) VCC 13.5 V 2 Maximum Voltage on Pins 2, 14,15, 28, 29, 31, 33, 37, 38, 39 Pin 3 Pins 17, 34 Pin 40 Pin 42 Pin 16 VIN 8 1.8 6 8 8 6 V 3 ESD Succeptibility Human Body Model, 100pF Discharge through 1.5kΩ EIAJ Norm, 200pF Discharge through 0Ω 2 300 kV V Tstg -40, +150 °C Tj 150 °C Topr 0, +70 °C Symbol Spec Unit θja 65 °C/W 4 Storage Temperature 5 Maximum Operating Junction Temperature 6 Operating Temperature VESD THERMAL CHARACTERISTICS NO 1 Item Junction-Ambient Thermal Resistance HORIZONTAL SECTION OPERATING CONDITIONS Parameter Symbol Conditions Min Typ Max Unit VCO Oscillator Resistor Min Value (Pin 11) R0min 6 kΩ Oscillator Capacitor Min Value (Pin 10) C0min 390 pF Maximum Oscillator Frequency Fmax Horizontal Sync Input Voltage (Pin 17) HsVR 0 Minimum Input Pulses Duration (Pin 17) MinD 1 Maximum Input Signal Duty Cycle (Pin 17) Mduty 25 % Maximum Input Peak Current (Pin 3) I3m 2 mA Horizontal Drive Output Max Current Pin 20 Pin 21 HOI1 HOI2 20 20 mA mA 70 kHz 5.5 V INPUT SECTION µS OUTPUT SECTION DC CONTROL VOLTAGE 5 Sourced current Sink current DEFLECTION PROCESSOR FOR MULTISYNC MONITORS Parameter Symbol DC Voltage Range on DC Controls (Pins 2-14-15) DCadj Conditions VREF-H = 8V S1D2147A01 Min 2 Typ Max Unit 6 V 6 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS ELECTRICAL CHARACTERISTICS (Vcc = 12 V, Tamb = 25 °C) Table 2. Horizontal Section Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit 10.8 12 13.2 V 40 60 mA 8 8.6 V 2 mA 8.6 V 2 mA 0.8 V SUPPLY AND REFERENCE VOLTAGES Supply Voltage (Pin 18) VCC Supply Current (Pin 18) ICC Reference Voltage for Horizontal Section (Pin 5) VREF-H Max Sourced Current on VREF-H (Pin 5) IREF-H Reference Voltage for Vertical Section (Pin 26) VREF-V Max Sourced Current on VREF-V (Pin 26) IREF-V See Figure 1 7.4 7.4 8 INPUT SECTION/PLL1 Horizontal Input Threshold Voltage (Pin 17) VINTH VCO Control Voltage (Pin 12) VVCO V REF-H = 8V 1.6 to 6.2 V VCO Gain, dF/dV (Pin 12) VCOG R0 = 6.49kΩ, C0 = 680pF 15 kHz/V Horizontal Phase Adjustment (Pin 15) Free running frequency adjustment (pin 14) PLL1 Capture Range Fh Min Fh Max PLL 1 Inhibition (Pin 35) PLL ON PLL OFF Low level voltage High level voltage 2 Hph % of Horizontal period ±10 % FFadj Without H-sync signal ±20 % CR See conditions on Figure 1 28 kHz kHz 0.8 V V 70 PLLinh V35 V35 2 SECOND PLL AND HORIZONTAL OUTPUT SECTION Flyback Horizontal Threshold Voltage (Pin 3) Horizontal Jitter Horizontal Drive Output Duty-cycle (Pin 20 or 21) Minimum Maximum Horizontal Drive Low Level Output Voltage 7 FBth 0.65 Hjit HDmin HDmax HDvd V 2 = 2V V 2 = 2V Pin 20 to GND, V21-V20, IOUT = 20mA 45 0.75 V 150 ppm 30 50 35 % % 1.1 1.7 V DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2147A01 Table 2. Horizontal Section Electrical Characteristics (Continued) Parameter Symbol Conditions Horizontal Drive High Level Output Voltage (output on Pin 20) HDem X-RAY Protection Input Threshold Voltage (Pin 16) XRAYth Maximum Output Current on Safety Blanking Output ISblkO I23 Low-Level Voltage on Safety Blanking output VSblkO V 23 with I23 = 10mA 0.25 1.6 3.2 V 1 V Pin 21 to V CC, IOUT = 20mA Min Typ 9.5 10 1.6 Internal Clamping Voltage on 2nd PLL Loop Filter Output (Pin 1) Vphi2 Vmin Vmax Pin2 Threshold Voltage to Stop H-out, V-out B+out and to Activate S-BLK (OFF Mode when V2 < V OFF) VOFF V2 Max Unit V 1.8 V 10 mA 0.5 V VERTICAL SECTION OPERATING CONDITIONS Parameter Symbol Vertical Sync Input Voltage (Pin 34) Conditions VSVR Min Typ 0 Max Unit 5.5 V Max Unit ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25 °C) Table 3. Vertical Section Electrical Characteristics Parameter Symbol Conditions Pin 23-28-29 bias current (Currnt sourced by PNP base) IBIASP For V23-28-29 = 2V Pin 31 bias Current (Current sunk by PNP base) IBIASN For V31 = 6V Vertical sync input threshold voltage VSth Pin 34; High-level Low -level Min Typ 2 °C 0.5 °C 2 0.8 V V Vertical sync input bias current (Current sourced by PNP base) VSBI V34 = 0.8V 1 µA Voltage at ramp bottom point VRB On Pin 27 2/8 VREF-V Voltage at ramp top point (with sync) VRT On Pin 27 5/8 VREF-V Voltage at ramp top point (without sync) VRTF On Pin 27 VRT-0.1 V 8 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS Table 3. Vertical Section Electrical Characteristics (Continued) Parameter Output current range on pin 27 during ramp charging time. Current to charge capacitor between pin 27 and ground Minimum Vertical sync pulse width Vertical sync input maximum duty-cycle Symbol IR27 Conditions V28 = 2V (2), 2V < V27 < 5V Min current Max current VSW Pin 34 VSmDut Pin 34 Min Typ Max Unit 15 135 20 100 µA µA µS 5 15 % Vertical Sawtooth discharge time duration VSTD On pin 27, with 150nF cap 85 µS Vertical Free running frequency ( V28 = 2V ) VFRF Measured on pin 27 Cosc (pin 27) = 150nF 100 Hz AUTO-SYNC frequency see (3) ASFR With C27 = 150nF ±5% Ramp Amplitude Thermal Drift RATD On pin 30 see (1) (0°C < Tamp < 70°C ) 100 ppm/ °C Ramp Amplitude Drift Versus Frquency RAFD V31 = 6V, C27 = 150nF 50Hz < F < 120Hz 200 ppm/ Hz V28 = 2V, V25 = X = 4.3V 2.5V < V27 < 4.5V 0.5 % Ramp Linearity on Pin 27 127 / I27 RIin Minimum Load on Pin 25 for less than 1% Vertical Amplitude Drift RIoad Vertical Position Adjustment Votlage on pin 32 Vpos Max Current on Vertical Position Control output (pin32) Vertical Output Votlage (on pin 30) (peak to peak voltage on pin 30) DC Votlage on Vertical Output (pin 30) 50 50 V33 = 2V V33 = 4V V33 = 6V 3.65 V31 = 2V V31 = 4V V31 = 6V VOUTDC See (4) 3.75 Hz kΩ 3.2 3.5 3.8 3.3 ±2 IVPOS Vor 120 2 3 4 V V V mA 2.2 V V V 7/16 VREF-V Vertical output maximum output current V0I On Pin 30 ±5 mA Max vertical S-Correction Amplifitude (V28 = 2V inhibits S-CORR; V28 = 6V gives maximum S-CORR) (see figure 3) dVS ∆V/V30pp at T/4 ∆V/V30pp at 3T/4 -4 +4 % % C-Correction adjustment range voltage on pin 27 for maximum slope on the ramp (with S-Correstion ) (see figure 4) Ccorr V29 = 2V V29 = 4V V29 = 6V 3 3.5 4 V V V 9 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2147A01 B+ SECTION OPERATING CONDITIONS Parameter Symbol Maximum Error Amplifier Output Current EAOI Minimum Feedback Resistor Conditions Min Typ Source by pin 14 Sunk by pin 41 FeedRes Resistor between pins 40 and 41 Max Unit 0.5 2 mA mA 5 kΩ ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25 °C) Table 4. B+ Section Electrical Characteristics Parameter Error Amplifier Open loop gain Symbol OLG Conditions At low frequency see Unity gain bandwidth UGBW Regulation input bias current IRI Min Typ Max Unit 85 dB 6 MHz 0.2 µA (1) see (1) Current sourced by pin 40 (PNP base) Maximum guaranted error amplifier output current EAOI Current sourced by pin 41 Current sink by pin 41 Current Sense Input Voltage Gain CSG Pin 42 3 Max Current Sense Input Threshold Votlage MCEth Pin 42 1.2 V Current sunk by pin 42 (NPN base) 1 µA 75 % Current Sense Input Bias Current ISI 0.5 2 mA mA Maximum External Power Transistor on Time Tonmax % of H-period @ f0 = 27kHz B+ Output Low Level Saturation voltage B+OSV V 22 with I22 = 10mA 0.25 V On error amp (+) input for V 39 = 4V 4.9 V 2V < V39 < 6V ±14 % Internal Reference voltage Internal Reference Voltage Adjustment IVref VRERADJ EAST/WEST PARABOLA GENERATOR ELECTRICAL CHARACTERISTICS (VCC = 12V, Tamb = 25 °C) Table 5. East/West Parabola Generator Electrical Characteristics Parameter Parabola symetry adjustment capability (for Keystone adjustment; with pin 38) Symbol Vsym Conditions See figure 2; Internal voltage V38 = 2V V38 = 4V V38 = 6V Min Typ Max Unit V 3.2 3.5 3.8 10 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS Table 5. East/West Parabola Generator Electrical Characteristics (Continued) Parameter Keystone adjustment capability B/A ratio A/B ratio Parabola amplitude adjustment capability Maximum amplitude on pin 36 Maximum ratio between max and min Symbol Kadj Paramp Conditions Min See figure 2; V37 = 4V V38 = 2V V38 = 6V V38 = 4.3V, V28 = 2V V37 = 2V 2V < V37 < 6V Typ Max Unit 2.3 2.0 V 3.3 2.4 3.8 3 4.3 NOTES: 1. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from comers of our processes and also temperature characterization. 2. When 2V are applied on pin 28 (Vertical S-Correction control ), then the S-Correction is inhibited, consequently the sawtooth have a linear shape. 3. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchorize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 4. 11 Typically 3.5V for vertical reference voltage typical value (8V). DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2147A01 APPLICATION CIRCUIT 1 PLL2C I-SENSE 42 I-SENSE 22nF 30k 1/8W AFC 24k 1/6W 1nF 50v H-DUTY COMP HFLY REGIN H-REF 1M 3 R 20k 40 D + 2.20nF 100V AFC R C 38 56K 1/6W 100nF 37 22K 1/6W 39 4 B+ ADJ HGND 1N4148 103 41 5.6k 1/6W 1k 1/6W 1N4148 H-ref 2 H-SIZE 5 HREF KEYST KEY-STONE + 20k 1/4W MF 100uF 16V 6 E/W-AMP S4 S-PIN 7 8 36 S3 E/WOUT S2 PLL1-INHIB E/W OUT 1N4148 35 82k 1/6W 5V 36K 1/6W 1uF 34 9 S1 V-sync VSYNC 1K 1/6W 33 10 C0 680pF MONO 5.6k 1/4W MF S1D2147A01 11 V-posi V-POS R0 10nF 1uF + 32 6.8k 12k 1/6W V-DCOUT To vertical Amp(+) 4.7uF + 1k 1/6w 220nF MP 31 12 PLL1F V-AMP V-SIZE 1.2k 1/6W 10nF 13 33k 1/6W 30 HLOCK-CAP VOUT 10k 1/6W 22nF MP 14 To vertical Amp 29 VS-CENT 47K 1/6W 18k 1/ 6W 4.7k 1/6W H-POSI FH-MIN 15 H-POS V-LIN 28 VS-AMP + 27k 1/ 6W 16 10uF 1K 1/6W 12V 1N4148 220 nF 64V 27 XRAY-IN VCAP HSYNC VREF 47k 15k 1/6W 22k 1/6W 17 Vref 26 H-SYNC1 100pF 50V 18 + 470uF 16V 1.8k 1/6W 1.5k 1/6W VAGCCAP + 19 GND + 0.47uF 24 VGND 12V 20 23 H-OUTEM 21 H-OUTCOL 100nF 100V 100uF 16V 25 VCC SBLK-OUT B+ OUT 47k 1/6W 22 3.3k 1/6W B+ DRIVE H-DRIVE Figure 1. Application Circuit 12 S1D2147A01 DEFLECTIONPROCESSORFORMULTISYNCMONITORS V36 V38 = 2V A B V38 = 4V V38 = 6V V27 3.8 3.5 3.2 Figure 2. Keystone Adjusment V27 4.0V 3.5V 3.0V 0 T Figure 3. Amplitude Adjusment V 30 ¡âV V30pp 0 T/4 T/2 3T/2 T ¡âV increase when V 28 increase. ¡âV = 0 when V28 = 0. Figure 4. Correction Adjusment 13