LT3750 Capacitor Charger Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®3750 is a flyback converter designed to rapidly charge large capacitors to a user-adjustable target voltage. A patented boundary mode control scheme* minimizes transition losses and reduces transformer size. The transformer turns ratio and two external resistors easily adjust the output voltage.* A low 78mV current sense accurately limits peak switch current and also helps to maximize efficiency. With a wide input voltage range, the LT3750 can operate from a variety of power sources. A typical application can charge a 100µF capacitor to 300V in less than 300ms. Charges Any Size Capacitor Easily Adjustable Output Voltage Drives High Current NMOS FETs Primary-Side Sense—No Output Voltage Divider Necessary Wide Input Range: 3V to 24V Drives Gate to VCC – 2V Available in 10-Lead MS Package U APPLICATIO S ■ ■ ■ ■ ■ Emergency Warning Beacons Professional Photoflash Systems Security/Inventory Control Systems High Voltage Power Supply Electric Fences Detonators The CHARGE pin gives full control of the LT3750 to the user. The DONE pin indicates when the capacitor has reached its programmed value and the part has stopped charging. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents, including 6518733, 6636021. U ■ TYPICAL APPLICATIO 300V, 6A Capacitor Charger T1 1:10 VTRANS 56µF ×2 10µF D1 VOUT 300V • 6A Charge Time + 300 100µF VCC 10µF 100k 60.4k VTRANS = 6V 200 43k DONE RDCM LT3750 OFF ON VTRANS = 18V 250 CHARGE GATE M1 VOUT (V) VCC 12V VTRANS RVOUT • VTRANS = 12V 150 100 SOURCE GND 50 RBG 12mΩ 2.49k 100pF 3750 TA01a 0 0 0.1 0.2 0.3 TIME (SECONDS) 0.4 0.5 3750 TA03c 3750fa 1 LT3750 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) TOP VIEW VCC, VTRANS, GATE, DONE, CHARGE ...................... 24V RBG ....................................................................... 1.5V SOURCE ................................................................... 1V Current into RDCM Pin ........................................ ±1mA Current into RVOUT Pin ........................................ ±1mA Current into DONE Pin ......................................... ±1mA Operating Temperature Range (Note 2) .. – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C VTRANS DONE CHARGE VCC GND 10 9 8 7 6 1 2 3 4 5 RBG RVOUT RDCM GATE SOURCE MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/ W ORDER PART NUMBER LT3750EMS MS PART MARKING LTBQD Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = VTRANS = 5V unless otherwise specified. PARAMETER CONDITIONS MIN ● Minimum VCC Minimum VTRANS ● TYP MAX 2.8 2.5 3 3 UNITS V V VCC Quiescent Current Not Switching, CHARGE = 5V Not Switching, CHARGE = 0V 1.6 2.5 1 mA µA VTRANS Quiescent Current Not Switching, CHARGE = 5V Not Switching, CHARGE = 0V 140 250 1 µA µA CHARGE Pin Current CHARGE = 24V CHARGE = 5V CHARGE = 0V 24 19 1 1.1 µA µA µA V 20 V µs CHARGE Pin Enable Voltage ● CHARGE Pin Disable Voltage Minimum CHARGE Pin Low Time ● High→Low→High VOUT Comparator Trip Voltage VOUT Comparator Overdrive Measured RBG Pin 1µs Pulse Width, Measured on RBG Pin RBG Pin Bias Current DCM Comparator Trip Voltage RBG = 1.2V Measured as VDRAIN – VTRANS, RDCM = 43k (Note 3) Current Limit Comparator Trip Voltage DONE Output Signal High 100kΩ to 5V DONE Output Signal Low DONE Pin Leakage Current 100kΩ to 5V DONE = 2.5V 0.87 0.2 ● 1.215 ● ● 0.6 1.24 30 1.265 V mV 5 70 36 500 80 nA mV 68 4.9 78 5 88 mV V 0.1 0.2 0.2 V µA NMOS Minimum On Time GATE Rise Time µs ns 0.6 50 GATE High Voltage CGATE = 1nF, VCC = 5V CGATE = 1nF, VCC = 24V GATE Turn Off Propagation Delay CGATE = 1nF Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 3 22 3.8 22.6 100 4.5 23.5 V V ns Note 2: The LT3750E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Refer to Block Diagram for VDRAIN definition. 3750fa 2 LT3750 U W TYPICAL PERFOR A CE CHARACTERISTICS VCC Pin Current VTRANS Pin Current 1.8 VCC = 12V 1.5 40 VCC = 3V 1.4 200 CHARGE PIN CURRENT (µA) VTRANS PIN CURRENT (µA) 1.6 45 VTRANS = 24V VCC = 24V 1.7 VCC PIN CURRENT (mA) CHARGE Pin Current 225 VTRANS = 12V 175 VTRANS = 3V 150 125 –50°C 35 30 25°C 25 20 125°C 15 10 5 1.3 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 100 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 100 3750 G01 0.6 CHARGE PIN DISABLE 0.5 0.4 8 12 16 VCHARGE (V) 24 20 GATE High Voltage 25 VDONE = 5V RDONE = 100k VCC = 24V 20 140 GATE PIN VOLTAGE (V) DONE PIN VOLTAGE (mV) 0.8 CHARGE PIN ENABLE 4 3750 G03 DONE Output Signal Low 160 0.9 CHARGE PIN VOLTAGE (V) 0 3750 G02 CHARGE Pin Enable/Disable Voltage 0.7 0 125 120 100 15 VCC = 12V 10 VCC = 5V 5 0.3 –25 50 25 75 0 TEMPERATURE (°C) 100 80 –50 125 –25 75 0 25 50 TEMPERATURE (°C) 100 DCM Comparator Trip Voltage VOUT Comparator Trip Voltage VOUT COMPARATOR TRIP VOLTAGE (V) DCM COMPARATOR TRIP VOLTAGE (mV) 1.240 RDCM = 43k 50 1.236 40 1.232 30 1.228 20 10 –50 1.224 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3750 G07 –25 50 25 0 75 TEMPERATURE (°C) 3750 G05 3750 G04 60 0 –50 125 1.220 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3750 G08 125 100 3750 G06 CURRENT LIMIT COMPARATOR TRIP VOLTAGE (mV) 0.2 –50 Current Limit Comparator Trip Voltage 82 80 78 76 74 72 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3750 G09 3750fa 3 LT3750 U U U PI FU CTIO S VTRANS (Pin 1): Transformer Supply Pin. Powers the primary coil of the transformer as well as internal circuitry that performs boundary mode detection. Bypass at the pin with a 1µF to 10µF capacitor. Bypass the primary winding of the transformer with a large capacitor. DONE (Pin 2): Open Collector Indication Pin. When target output voltage is reached, an NPN transistor turns on. Requires a pull-up resistor or current source. Any fault conditions such as thermal shutdown or undervoltage lockout will also turn on the NPN. CHARGE (Pin 3): Charge Pin. Initiates a new charge cycle when brought high or discontinues charging and puts part into shutdown when low. To properly enable the device, a step input with a minimum ramp rate of 1V/µs is required. Drive to 1.1V or higher to enable the device; drive below 0.2V to disable the device. VCC (Pin 4): Input Supply Pin. Bypass locally with a ceramic capacitor. A 1µF to 10µF ceramic capacitor should be sufficient for most applications. GND (Pin 5): Ground Pin. Connect directly to local ground plane. SOURCE (Pin 6): Source Pin. Senses NMOS drain current. Connect NMOS source terminal and current sense resistor to this pin. The current limit is 78mV/RSENSE. GATE (Pin 7): Gate Pin. Connect NMOS gate terminal to this pin. Internal gate driver will drive voltage to within VCC – 2V during each switching cycle. RDCM (Pin 8): Discontinuous Mode Sense Pin. Senses when current in transformer has decayed to zero and initiates a new charge cycle if output voltage target has not been reached. Place a resistor between this pin and the drain of the NMOS. A good choice is a 43k, 5% resistor. RVOUT (Pin 9): Output Voltage VI Converter Pin. Develops a current proportional to output capacitor voltage. Connect a resistor between this pin and the drain of the NMOS. RBG (Pin 10): Output Voltage Sense Pin. Senses the voltage across the RBG resistor, which is proportional to the current flowing into the RVOUT pin. When voltage equals 1.24V, charging is disabled and DONE pin goes low. Connect a resistor (2.5k or less is recommended) from this pin to GND. A 2.49k, 1% resistor is a good choice. 3750fa 4 LT3750 W BLOCK DIAGRA VTRANS RDONE 2 1 DONE 2.8V + VTRANS VCC UVLO D1 T1 1:N • VCC RVOUT VTRANS UVLO 2.5V VTRANS + VOUT – + DCM COMPARATOR – + 160°C – RVOUT 9 RDCM 8 ONE SHOT – DIE TEMP RDCM + COUT • TSD +– VTRANS 36mV VDRAIN VCC S M1 ENABLE R GATE Q 4 7 M1 Q Q S R + SOURCE + VOUT COMPARATOR 3 CHARGE – 6 1.24V CURRENT LIMIT COMPARATOR ONE SHOT GND 5 10 RBG – RSENSE + – 78mV 3750 BD RBG 3750fa 5 LT3750 U OPERATIO The LT3750 is designed to charge capacitors quickly and efficiently. Operation can be best understood by referring to Figures 1 and 2. Operation proceeds in four phases: 1. Start-up, 2. Primary-side charging, 3. Secondary energy transfer, 4. Discontinuous mode sensing. 1. Start-Up 2. Primary Side Charging When the NMOS on latch is set, the gate driver rapidly charges the gate pin to VCC – 2V. The external NMOS turns on forcing VTRANS – VDS(ON) across the primary winding. Consequently, current in the primary coil rises linearly at ILPRI Start-up occurs for approximately 20µs after the charge pin is raised high. During this phase, a one-shot enables the master latch and turns on the NMOS. The master latch will remain in the set state until the target output voltage is reached or a fault condition resets it. 1:N VTRANS + • ILPRI VPRI • + ILSEC VTRANS – VDS(ON) LPRI ILSEC S2 VOUT + VDIODE LSEC IPK N + VSEC – – 3750 F01a S1 VDRAIN IPK VPRI VTRANS – VDS(ON) – (1a) Equivalent Circuit During Primary-Side Charging 1:N VTRANS + ILSEC • ILPRI VPRI • + S2 –(VOUT + VDIODE) N + VSEC VSEC – VOUT + VDIODE – 3750 F01b S1 VDRAIN – (1b) Equivalent Circuit During Secondary Energy Transfer and Output Detection 1:N VTRANS + ILPRI VPRI • + VDRAIN – ILSEC • –N (VTRANS – VDS(ON)) S2 V + VDIODE VTRANS + OUT N VDRAIN + VTRANS VSEC – 3750 F01c S1 VDS(ON) VDS(ON) – (1c) Equivalent Circuit During Discontinuous Mode Detection Figure 1. Equivalent Circuits 3750 F02 1. PRIMARY-SIDE CHARGING 3. 2. DISCONTINUOUS SECONDARY MODE ENERGY TRANSFER DETECTION AND OUTPUT DETECTION Figure 2. Idealized Charging Waveforms 3750fa 6 LT3750 U OPERATIO a rate (VTRANS – VDS(ON))/LPRI. The input voltage is mirrored on the secondary winding –N • (VTRANS – VDS(ON)) which reverse biases the diode and prevents current flow in the secondary winding. Thus, energy is stored in the core of the transformer. 3. Secondary Energy Transfer When current limit is reached, the current limit comparator resets the NMOS on-latch and the device enters the third phase of operation, secondary energy transfer. The energy stored in the transformer core forward biases the diode and current flows into the output capacitor. During this time, the output voltage (neglecting the diode drop) is reflected back to the primary coil. If the target output voltage is reached, the VOUT comparator resets the master latch and the DONE pin goes low. Otherwise, the device enters the next phase of operation. 4. Discontinuous Mode Detection Once all the current is transferred to the output capacitor, (VOUT + VDIODE)/N will appear across the primary winding. A transformer with no energy cannot support a DC voltage, so, the voltage across the primary will decay to zero. In other words, the drain of the NMOS will ring down from VTRANS + (VOUT + VDIODE)/N to VTRANS. When the drain voltage falls to VTRANS + 36mV, the DCM comparator sets the NMOS on-latch and a new charge cycle begins. Steps 2-4 continue until the target output voltage is reached. 3750fa 7 LT3750 U W U U APPLICATIO S I FOR ATIO Safety Warning Switching Period Large capacitors charged to high voltage can deliver a lethal amount of energy if handled improperly. It is particularly important to observe appropriate safety measures when designing the LT3750 into applications. First, create a discharge circuit that allows the designer to safely discharge the output capacitor. Second, adequately space high voltage nodes from adjacent traces to satisfy printed circuit board voltage breakdown requirements. High voltage nodes are the drain of the NMOS, the secondary side of the transformer, and the output. The LT3750 employs an open-loop control scheme causing the switching period to decrease with output voltage. Typical switching frequency is between 100kHz to 300kHz. Figure 3 shows typical switching period in an application with a 3A peak current. 20 TIME (µs) 16 Transformer Selection The flyback transformer is critical to proper operation of the LT3750. It must be designed carefully so that it does not cause excessive current or voltage on any pin of the part. 8 4 0 As with all circuits, the LT3750 has finite bandwidth. In order to give the LT3750 sufficient time to detect the output voltage, observe the following restrictions on the primary inductance: LPRI ≥ 12 0 50 100 150 200 VOUT (V) 250 300 3750 F03 Figure 3. Typical Switching Period vs VOUT Output Diode Selection VOUT • 1µs N • IPK otherwise, the LT3750 may overcharge the output. Linear Technology has worked with several leading magnetic component manufacturers to produce flyback transformers for use with the LT3750. Table 1 summarizes the particular transformer characteristics. When choosing the rectifying diode, ensure its peak repetitive forward current rating exceeds the peak current (IPK/N) and that the peak repetitive reverse voltage rating exceeds VOUT + (N)(VTRANS). The average current through the diode varies during the charge cycle because the switching period decreases as VOUT increases. The average current through the diode is greatest when the Table 1. Recommended Transformers PART NUMBER SIZE L × W × H (mm) MAXIMUM IPRI (A) LPRI (µH) TURNS RATIO (PRI:SEC) DCT15EFD-U44S003 DCT20EFD-U32S003 22.5 × 16.5 × 8.5 30 × 22 × 12 5 10 10 10 1:10 1:10 Sumida (www.sumida.com) C8118 Rev P1 C8117 Rev P1 C8119 Rev P1 21 × 14 × 8 23 × 18.6 × 10.8 32.3 × 27 × 14 3 5 10 10 10 10 1:10 1:10 1:10 Midcom (www.midcom.com) 32050 32051 32052 23.1 × 18 × 9.4 28.7 × 22 × 11.4 28.7 × 22 × 11.4 3 5 10 10 10 10 1:10 1:10 1:10 Coilcraft (www.coilcraft.com) DA2032-AL DA2033-AL DA2034-AL 17.2 × 22 × 8.9 17.4 × 24.1 × 10.2 20.6 × 30 × 11.3 3 5 10 10 10 10 1:10 1:10 1:10 MANUFACTURER TDK (www.tdk.com) 3750fa 8 LT3750 U W U U APPLICATIO S I FOR ATIO output capacitor is almost completely charged and is given by: IAVG,D = ( IPK • VTRANS 2 VOUT(PK ) + N • VTRANS ) The output diode’s continuous forward current rating must exceed IAVG,D. At a minimum, the diode must satisfy all the previously mentioned specifications to guarantee proper operation. However, to optimize charge time, reverse recovery time and reverse bias leakage current should be considered. Excessive diode reverse recovery times can cause appreciable discharging of the output capacitor thereby increasing charge time. Choose a diode with a reverse recovery time of less than 100ns. Diode leakage current under high reverse bias bleeds the output capacitor of charge, also increasing charge time. Choose a diode that has minimal reverse bias leakage current. Table 2 recommends several output diodes for various output voltages with adequate reverse recovery time. Table 2. Recommended Output Diodes MANUFACTURER Diodes Inc. (www.diodes.com) Philips (www.semiconductors. philips.com) PART NUMBER IDC (A) PEAK REPETITIVE REVERSE VOLTAGE (V) MURS140 MURS160 ES2G US1M 1 1 2 1 400 600 400 1000 SMB SMB SMB SMA BYD147 BYD167 1 1 400 500 SOD87 SOD87 can result in improper operation. This most often manifests itself in two ways. The first is when the primary winding current looks distorted instead of triangular. This substantially reduces the efficiency and increases the charge time. The second way is when the LT3750 fails to detect discontinuous mode after the first switching cycle. Both of these problems are solved by increasing the amount of capacitive bypassing for the transformer. Choose capacitors that can handle the high RMS ripple currents common in flyback regulators. Output Capacitor Selection For photoflash applications, the output capacitor will be discharged into a Xenon flash bulb. Only a pulse capacitor or photoflash capacitor is able to survive such a harsh event. Igniting a typical Xenon bulb requires approximately 250V to 350V stored on a capacitor on the order of hundreds of microfarads. Table 3. Recommended Output Capacitor Vendors VENDOR WEBSITE Rubycon www.rubycon.com Cornell Dubilier www.cornell-dubilier.com NWL www.nwl.com NMOS Selection PACKAGE Bypass Capacitor Selection Use a high quality X5R or X7R dielectric ceramic capacitor placed close to the LT3750 to locally bypass the VCC and VTRANS pins. For most applications, a 1µF to 10µF ceramic capacitor should suffice for VCC and a 1µF to 10µF for the VTRANS pin. The high peak currents flowing through the transformer necessitate a larger (>>10µF) capacitor to bypass the primary winding of the transformer. Inadequate bypassing Choose an external NMOS with minimal gate charge and on resistance that satisfies current limit and voltage breakdown requirements. The gate is nominally driven to VCC – 2V during each charge cycle. Ensure that this does not exceed the maximum gate to source voltage rating of the NMOS but enhaces the channel enough to minimize the on resistance. Similarly, the maximum drain-source voltage rating of the NMOS must exceed VTRANS + VOUT/N or the magnitude of the leakage inductance spike, whichever is greater. The maximum instantaneous drain current must exceed current limit. Because the switching period decreases with output voltage, the average current through the NMOS is greatest when the output is nearly charged and is given by: IAVG,M = ( IPK • VOUT(PK ) 2 VOUT(PK ) + N • VTRANS ) 3750fa 9 LT3750 U W U U APPLICATIO S I FOR ATIO Table 4. Recommended NMOS Transisitors MANUFACTURER PART NUMBER ID (A) VDS(MAX) (V) VGS(MAX) (V) RDS(ON) (mΩ) PACKAGE Philips Semiconductor (www.semiconductors.philips.com) PHM21NQ15T PHK12NQ10T PHT6NQ10Y PSMN038-100K 22.2 11.6 6.5 6.3 150 100 100 100 20 20 20 20 55 28 90 38 HVSON8 SO-8 SOT223 SO-8 IRF7488 IRF7493 IRF6644 6.3 9.3 10.3 80 80 100 20 20 20 29 15 10.7 SO-8 SO-8 DirectFET International Rectifier (www.irf.com) The transistor’s continuous drain current rating must exceed IAVG,M. Table 4 lists recommended NMOS transistors. Setting Current Limit A sense resistor from the SOURCE pin to GND implements current limit. The current limit is nominally 78mV/RSENSE. The average power dissipation rating of the current sense resistor must exceed: PRESISTOR ≥ ⎞ VOUT(PK ) IPK 2 • RSENSE ⎛ ⎜ ⎟ 3 ⎝ VOUT(PK ) + N • VTRANS ⎠ Additionally, there is approximately a 100ns propagation delay from the time that peak current limit is detected to when the gate transitions to the low state. This delay increases the peak current limit by (VTRANS)(tDELAY)/LPRI. Setting The Target Output Voltage The parameters that determine the target output voltage are the resistors RVOUT and RBG, the turns ratio of the transformer (N), and the voltage drop across the output diode (VDIODE). The target output voltage is set according to the following equation: ⎛ ⎞ R VOUT = ⎜ 1 . 24V • VOUT • N⎟ – VDIODE RBG ⎝ ⎠ Use at least 1% tolerance resistors for RVOUT and RBG. Choosing large value resistors for RBG decreases the amount of current that charges the parasitic internal capacitances and degrades the response time of the VOUT comparator. This may result in overcharging of the output capacitor. The maximum recommended value for RBG is 2.5k for typical applications. When high primary currents are used, a voltage spike can prematurely trip the output voltage comparator. A 33pF to 100pF capacitor in parallel with RBG is sufficient to filter this spike for most applications. Always check that the voltage waveform on RBG does not overshoot and that it reaches a plateau at maximum VOUT. Discontinuous Mode Detection The RDCM resistor stands off voltage transients on the drain node. A 43k, 5% resistor is recommended for 300V applications. Higher output voltages will require a larger resistor. In order for the LT3750 to properly detect discontinuous mode and start a new charge cycle, the reflected voltage to the primary winding must exceed the discontinuous mode comparator threshold which is nominally 36mV. The worst-case condition occurs when VOUT is shorted to ground. When this occurs, the reflected voltage is simply the diode forward voltage drop divided by N. 3750fa 10 LT3750 U W U U APPLICATIO S I FOR ATIO Board Layout The high voltage operation of the the LT3750 demands careful attention to board layout. Observe the following points: 1. Minimize the area of the high voltage end of the secondary winding. 3. Keep the electrical path formed by C1, the primary of T1 and drain of the NMOS as small as possible. Increasing the size of this path effectively increases the leakage inductance of T1 resulting in an overvoltage condition on the drain of the NMOS. 2. Provide sufficient spacing for all high voltage nodes (NMOS drain, VOUT and the secondary winding of the transformer) in order to meet breakdown voltage requirements. RBG CHARGE 1 10 2 9 3 VCC CIN LT3750 T1 1:N PRIMARY RDONE DOUT CPRI 8 4 7 5 6 RDCM • • SECONDARY CTRANS VTRANS + COUT RVOUT RSENSE M1 3750 F04 Figure 4. Recommended Board Layout (Not to Scale) 3750fa 11 LT3750 U TYPICAL APPLICATIO S 300V, 3A Capacitor Charger T1 1:10 VTRANS C3 56µF C2 10µF VCC 12V VTRANS RVOUT VCC C1 10µF 100k 4, 5 D1 VOUT 300V 1 • • 60.4k 6, 7 + C4 100µF 10 43k DONE RDCM LT3750 OFF ON CHARGE GATE M1 SOURCE GND RBG 25mΩ 2.49k 33pF 3750 TA02a C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: DIODES INC. MURS160 M1: PHILIPS PHT6NQ10T T1: TDK DCT15EFD-U44S003 FLYBACK TRANSFORMER 3A Charging Efficiency 3A Charge Time 100 300 VTRANS = 18V VTRANS = 18V NMOS DRAIN CURRENT 1A/DIV 250 90 VTRANS = 6V VTRANS = 12V 200 VTRANS = 6V 80 VOUT (V) EFFICIENCY (%) Typical Switching Waveforms 70 VTRANS = 12V NMOS DRAIN VOLTAGE 20V/DIV 150 5µs/DIV 100 60 50 3750 TA02d 50 0 0 50 100 150 200 VOUT (V) 250 300 3750 TA02b 0 0.2 0.4 0.6 TIME (SECONDS) 0.8 1.0 3750 TA02c 3750fa 12 LT3750 U TYPICAL APPLICATIO S 300V, 6A Capacitor Charger T1 1:10 VTRANS C3 56µF ×2 C2 10µF VCC 12V VCC C1 10µF VTRANS RVOUT 3, 4, 5, 6 VOUT 300V 1 • • 60.4k 7, 8, 9, 10 100k D1 + C4 100µF 12 43k DONE RDCM LT3750 CHARGE OFF ON GATE M1 SOURCE GND RBG 12mΩ 2.49k 100pF 3750 TA03a C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: DIODES INC. MURS160 M1: PHILIPS PHT6NQ10T T1: TDK DCT20EFD-U32S003 FLYBACK TRANSFORMER 6A Charging Efficiency 6A Charge Time Typical Switching Waveforms 300 100 VTRANS = 18V VTRANS = 18V VTRANS = 6V VTRANS = 12V 80 200 VOUT (V) EFFICIENCY (%) 90 NMOS DRAIN CURRENT 2A/DIV 250 VTRANS = 6V VTRANS = 12V NMOS DRAIN VOLTAGE 20V/DIV 150 70 100 60 50 5µs/DIV 3750 TA03d 50 0 0 50 100 150 200 VOUT (V) 250 300 3750 TA03b 0 0.1 0.2 0.3 TIME (SECONDS) 0.4 0.5 3750 TA03c 3750fa 13 LT3750 U TYPICAL APPLICATIO S 300V, 9A Capacitor Charger T1 1:10 VTRANS C3 56µF ×3 C2 10µF VCC 12V VCC C1 10µF 3, 4, 5, 6 • 60.4k 7, 8, 9, 10 100k VOUT 300V 1 • VTRANS RVOUT D1 + C4 100µF 12 43k DONE RDCM LT3750 CHARGE OFF ON GATE M1 SOURCE GND RBG 8mΩ 2.49k 100pF 3750 TA04a C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: DIODES INC. MURS160 M1: PHILIPS PHM2INQ15T T1: TDK DCT20EFD-U32S003 FLYBACK TRANSFORMER 9A Charging Efficiency 9A Charge Time 100 Typical Switching Waveforms 300 VTRANS = 18V VTRANS = 18V VTRANS = 6V 200 VTRANS = 12V VOUT (V) EFFICIENCY (%) 90 VTRANS = 6V 80 NMOS DRAIN CURRENT 4A/DIV 250 VTRANS = 12V NMOS DRAIN VOLTAGE 20V/DIV 150 5µs/DIV 100 3750 TA04d 70 50 60 0 50 100 150 200 VOUT (V) 250 300 3750 TA04b 0 0 0.05 0.10 0.15 0.20 TIME (SECONDS) 0.25 0.30 3750 TA04c 3750fa 14 LT3750 U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS) 0603 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3750fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT3750 U TYPICAL APPLICATIO 300V, 9A, 2.5mF Capacitor Charger T1 1:10 VTRANS C2 10µF VCC 12V VCC C1 10µF VTRANS RVOUT C3 4, 5 56µF ×3 60.4k 100k D1 VOUT 300V 1 • • 6, 7 + C4 2.5mF 10 43k DONE RDCM LT3750 OFF ON CHARGE GATE M1 SOURCE GND RBG 8mΩ 2.49k 100pF 3750 TA05a C1, C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: CORNELL DUBILIER 7P252V360N082 D1: DIODES INC. MURS160 M1: PHILIPS PHM21NQ15T T1: MIDCOM 32052 FLYBACK TRANSFORMER Efficiency Charge Time 100 300 95 VTRANS = 18V 250 VTRANS = 12V 90 200 VTRANS = 12V VOUT (V) EFFICIENCY (%) VTRANS = 18V 85 VTRANS = 6V VTRANS = 6V 150 80 100 75 50 70 0 50 100 150 200 VOUT (V) 250 0 300 0 3750 TA05b 1 2 3 4 5 TIME (SECONDS) 6 7 8 3750 TA05c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3420/LT3420-1 1.4A/1A, Photoflash Capacitor Charger with Automatic Top-Off Charges 220µF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1µA, 10-Lead MS Package LT3468/LT3468-1 LT3468-2 1.4A, 1A, 0.7A, Photoflash Capacitor Charger VIN: 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, ThinSOT Package LT3484-0/LT3484-1 LT3484-2 1.4A, 0.7A, 1A Photoflash Capacitor Charger VIN: 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, 2mm × 3mm 6-Lead DFN Package LT3485-0/LT3485-1 LT3485-2/LT3485-3 1.4A, 0.7A, 1A, 2A Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT VIN: 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF, VIN = 3.6V), ISD < 1µA, 3mm × 3mm 10-Lead DFN Driver 3750fa 16 Linear Technology Corporation LT 0106 REV A • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005