TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Compact LCD Bias Supply for TFT-LCD TV Panels FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • • • • • • • 8.5V to 14.7V Input Voltage Range VS Output Voltage Range up to 19V Boost Converter with 4.2A Switch Current Step Down Converter with 2.6A Switch Current and Adjustable Output 2.5V to 3.3V 750kHz Fixed Switching Frequency Temperature Compensated Negative Supply High Voltage Stress Test (HVS) Adjustable Sequencing Gate Drive Signal for Isolation Switch Short Circuit Protection Internal Soft-Start 180° Phase Shift Between Buck and Boost P2P Short/Open Certified Optimized Dual Layer PCB Layout Low EMI Undervoltage Lockout Thermal Shutdown Available in 6×6mm 40 Pin QFN Package TYPICAL APPLICATION Vin 12V Boost Converter With HVS Vs 15V / 2.9A Buck Converter Vlogic 3.3V / 2.4A Positive Charge Pump VONE 28V / 150mA Inverting Buck Boost With Temperature Compensation LCD TV Panel with ASG Technology DESCRIPTION The TPS65166 offers a compact power supply solution to provide all voltages required by a LCD panel for large TV panel applications running from a 12V supply rail. The device is optimized to support LCD technology using ASG gate drive circuits. The device generates all voltage rails for the TFT LCD bias (VS, VONE, VOFFE, VSS). In addition to that it includes a step-down converter (Vlogic) to provide the logic voltage. By pulling the HVS pin high an implemented high voltage stress test feature programs the boost converter output voltage Vs to higher values. The boost converter operates at a fixed switching frequency of 750kHz. The positive charge pump is running from the boost converter and is regulated by an external transistor. A buck-boost converter provides an adjustable temperature dependent negative output voltage VOFFE. The negative output voltage VSS is regulated by a shunt regulator. Safety features like overvoltage protection of the buck-boost input voltage, the boost and buck output voltage, undervoltage lockout, short circuit protection of VONE, VOFFE, and Vlogic are included as well as thermal shutdown. VOFFE -22 to -11V / 200mA Negative Shunt Regulator Vss -7.5V / 100mA Sequencing And Logic Power Good 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) (1) (2) TA ORDERING PACKAGE PACKAGE MARKING –40°C to 85°C TPS65166RHAR 6 × 6mm 40 Pin QFN TPS65166 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The RHA package is available taped and reeled. Add R suffix to the device type (TPS65166RHAR) to order the device taped and reeled. The RHA package has quantities of 3000 devices per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Input voltage range AVIN, VIN1, VIN2, VIN3 (2) –0.3 to 20 V Voltage range at SW1, SW2, SW3, SW4, GD, BASE2, RHVS, OS –0.3 to 20 V Voltage range at EN1, EN2, HVS –0.3 to 20 V Voltage range at COMP, SS, FB1,VSNS, FB2, FB3, FB4, TS, SET, FB5, DLY1, DLY2, PG –0.3 to 7.0 V 40 V –9.5 to 0.3 V Voltage difference VIN3 to SW5 BASE1 ESD rating, Human Body Model 2 kV ESD rating, Machine Model 200 V ESD rating, Charged Device Model 700 V Continuous total power dissipation See Dissipation Rating Table Operating junction temperature range, TJ –40 to 150 °C Operating ambient temperature range, TA –40 to 85 °C Storage temperature range, Tstg –65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) (1) PACKAGE RθJA TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 40 pin QFN 35°C/W 2.8W 1.6W 1.1W Soldered Power Pad on a standard 2-Layer PCB without vias for thermal pad. See the Texas Instruments Application report (SLMA002) regarding thermal characteristics of the PowerPAD package. RECOMMENDED OPERATING CONDITIONS (1) MIN TYP MAX UNIT 14.7 V VIN Input voltage range (AVIN, VIN1, VIN2, VIN3) 8.5 VIN3 Overvoltage protection 15V for buck-boost converter 15 TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C (1) 2 V Refer to application section for further information Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS AVIN=VIN1=VIN2=VIN3=12V, EN1=EN2=VIN, VS=15V, Vlogic=3.3V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range IQIN Quiescent current into AVIN, VIN1,2,3 Not switching, FB=FB+5% 8.5 1.2 Isd Shutdown current into AVIN, VIN1,2,3 EN1=EN2=GND 170 VUVLO Under-voltage lockout threshold VIN falling 8.0 8.2 V VUVLO Under-voltage lockout threshold VIN rising 8.2 8.5 V Thermal shutdown Temperature rising 150 °C 15 °C Thermal shutdown hysteresis 14.7 V mA µA LOGIC SIGNALS EN1, EN2, HVS VIH High level input voltage VIN = 8.5V to 14.7V VIL Low level input voltage VIN = 8.5V to 14.7V II Input leakage current EN1=EN2=GND 1.7 V 0.01 0.4 V 0.1 µA POWER GOOD VIL Low level voltage (1) I(sink) = 500µA Ilkg Leakage current VPG = 5.0V 0.01 0.3 V 0.1 µA µA SEQUENCING DLY1, DLY2, and SOFT-START Ichrg DLY1, DLY2 charge current Vthreshold DLY1, DLY2 threshold voltage Rdischrg DLY1, DLY2 discharge resistor ISS Soft-start charge current Vthreshold = 1.24V 4 4.9 6.3 1.21 1.24 1.27 3.2 Vthreshold = 1.24V V kΩ 8 10 12 µA 600 750 900 kHz 19 V 19.0 19.5 20 V 1.225 1.24 1.252 V SWITCHING FREQUENCY fs Switching frequency BOOST CONVERTER (Vs) Vs Output voltage range Vswovp Switch overvoltage protection VFB1 Feedback regulation voltage IFB1 Feedback input bias current VFB1 = 1.24V 10 100 nA RDS(on) N-MOSFET on-resistance ISW = 500mA 120 170 mΩ ILIM N-MOSFET switch current limit 5.2 6.2 A Ileak Switch leakage current 1 10 µA ton Minimum on time Vs rising 4.2 Vsw = 15V 80 Line regulation 8.5V ≤ VIN ≤ 14.7V, Iout = 1mA Load regulation 1mA ≤ Iout ≤ 2.0A ns 0.006 %/V 0.1 %/A GATE DRIVE (GD) AND BOOST CONVERTER PROTECTION VGDM VIN – VGD (2) VIN = 12V, GD pulled down I(GD) Gate drive sink current EN2 = high 10 R(GD) Gate drive internal pull up resistance 10 kΩ ton Gate on time during short circuit FB1 < 100mV 1.4 ms 5 6 7 V µA BUCK CONVERTER (Vlogic) Vlogic Output voltage range 2.2 VFB2 Feedback regulation voltage FB2 connected to resistor divider, Iload = 10mA IFB2 Feedback input bias current VFB2 = 1.24V RDS(on) N-MOSFET on-resistance Isw3, Isw4 = 1.5A (1) (2) 1.215 4.0 V 1.24 1.265 V 10 100 nA 150 250 mΩ PG goes high impedance once Vs and VONE are in regulation. GD goes to VIN – VGD once the boost converter Vs is enabled. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 3 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVIN=VIN1=VIN2=VIN3=12V, EN1=EN2=VIN, VS=15V, Vlogic=3.3V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.6 3.4 4.2 UNIT ILIM N-MOSFET switch current limit Ileak Switch leakage current Vsw = 0V Line regulation 8.5V ≤ VIN ≤ 14.7V, Iout = 1mA 0.006 %/V 1mA ≤ Iout ≤ 100mA 0.042 %/mA 100mA ≤ Iout ≤ 2.5A 0.06 %/A Load regulation A µA 1 NEGATIVE SHUNT REGULATOR (Vss) VBase1 Base1 voltage range Transistor leakage maximum 5µA IBase1 Base1 drive source current VFB3 = VFB3nominal – 5% VFB3 Feedback regulation voltage IFB3 Feedback input bias current VFB3 = 1.24V Line regulation 8.5V ≤ VIN ≤ 14.7V, Iout = 1mA Load regulation 1mA ≤ Iout ≤ 100mA –9.5 0.3 5 –5% V mA 0.75 × Vlogic 5% 10 100 V nA 0.006 %/V 0.0004 %/mA NEGATIVE BUCK BOOST CONVERTER (VOFFE) Vovp VIN3 overvoltage protection VOFFE Adjustable output voltage range RDS(on) P-MOSFET on resistance ILIM P-MOSFET current limit 15 ISW5 at current limit Regulation accuracy upper limit VTS = 1V, VSET = 1.9V Regulation accuracy VTS = 1V, VSET = 2.4V Regulation accuracy lower limit VTS = 0.7V, VSET = 2.4V IFB5 Feedback input bias current ITS ISET VFB5 V –22 0.9 1.1 1.4 1.8 1.9 -5 V 1.6 Ω A 2.0 V V 1.9 2 2.1 1.57 1.65 1.73 V VFB5 = 2V 10 100 nA TS input bias current VTS = 1V 10 100 nA SET input bias current VSET = 3V 3 5 Line regulation 8.5V ≤ VIN ≤ 14.7V, Iout = 1mA Load regulation 1mA ≤ Iout ≤ 200mA, VOFFE = –11V µA 0.003 %/V 0.0005 %/mA POSITIVE CHARGE PUMP (VONE) IBase2 Base2 drive sink current VFB4 = VFB4nominal-5% Base2 drive sink current (SC-Mode) VFB4 = GND 8 14 40 50 70 µA 20 V 1.18 1.24 1.30 V 100 nA VBase2 Base drive voltage range VFB4 Feedback regulation voltage IFB4 Feedback input bias current VFB4 = 1.24V 10 Line regulation 8.5V ≤ VIN ≤ 14.7V, Iout = 1mA 0.9 Load regulation 1mA ≤ Iout ≤ 150mA, VOFFE = –11V mA %/V 0.004 %/mA HIGH VOLTAGE STRESS TEST (HVS), RHVS RHVS RHVS pull down resistance HVS = high, IHVS = 500µA IRHVS RHVS leakage current HVS = low, VRHVS = 5V 4 Submit Documentation Feedback 350 450 550 Ω 100 nA Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 DEVICE INFORMATION PACKAGE PGND1 PGND2 SW1 SW2 OS VL+ COMP FB1 RHVS VIN3 40 Pin 6mm x 6mm QFN (Top View) 40 39 38 37 36 35 34 33 32 31 GD 1 30 SW 5 AVIN 2 29 NC VIN1 3 28 NC VIN2 4 27 FB 5 NC 5 26 TS SW3 6 25 SET SW4 7 24 AGND/VL- NC 8 23 NC VSNS 9 22 NC 21 BASE2 14 15 16 17 18 EN2 HVS FB3 SS BASE1 19 20 FB4 13 DLY2 12 EN1 PG 10 11 DLY1 FB 2 Exposed Thermal Die * NOTE: The thermally enhance Power Pad is connected to GND PIN FUNCTIONS PIN NAME GD AVIN VIN1, VIN2 NC SW3, SW4 NO. I/O DESCRIPTION 1 I Gate drive pin for the external isolation MOSFET. 2 I Input voltage supply pin for the analog circuit. 3,4 I Input supply for the buck converter generating Vlogic 5 6,7 Not connected O Switch pin for the buck converter generating Vlogic NC 8 VSNS 9 I Not connected Reference voltage input for the buck-boost and negative shunt regulator FB2 10 I Feedback pin for the buck converter. PG 11 I Power good output latched high when VS and VONE are in regulation DLY1 12 O Delay pin EN2 high to enable boost converter VS EN1 13 I Enable of the buck converter Vlogic EN2 14 I Enable of the negative supplies VSS and VOFFE, enable DLY1 and DLY2 HVS 15 I Logic pin to enable high voltage stress test. This allows programming the boost converter VS to a higher voltage FB3 16 I Feedback of the negative supply VSS SS 17 O Soft-start for the boost converter VS Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 5 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION BASE1 18 O Base drive of the external npn transistor for the negative supply VSS DLY2 19 O Delay pin EN2 high to enable charge pump VONE FB4 20 I Feedback for the positive supply VONE BASE2 21 I Base drive of the external pnp transistor for the positive charge pump VONE NC 22, 23 Not connected AGND/VL- 24 SET 25 I Analog ground and connection of the bypass capacitor of VLInput pin for the reference voltage to set the higher limit for the temperature compensation for VOFFE TS 26 I Input pin for the NTC temperature sensor FB5 27 I Feedback pin for the negative buck-boost converter VOFFE NC 28, 29 Not connected SW5 30 O Switch pin for the negative buck-boost converter generating VOFFE VIN3 31 I Input supply for the buck-boost converter generating VOFFE RHVS 32 I This pin is pulled low when HVS is high. The resistor connected to this pin sets the boost converter output voltage when HVS is pulled high FB1 33 I Feedback for the boost converter VS COMP 34 O Compensation pin for the boost converter VL+ 35 O Output of the internal logic regulator. Connect a capacitor between this pin and AGND/VL- OS 36 I Connect this pin to the boost converter output for overvoltage protection SW1, SW2 37, 38 I Switch pin for the boost converter and the positive charge pump VONE PGND1, PGND2 39, 40 6 Power ground for the boost converter VS Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Functional Block Diagram Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 7 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Start-up Sequence Startup sequencing Figure 1 Startup sequencing Figure 2 Boost Converter Soft-start boost converter Figure 3 Efficiency boost converter vs load current Figure 4 PWM operation at nominal load current Figure 5 PWM operation at light load current Figure 6 Load transient response boost converter Figure 7 Overvoltage protection Figure 8 Buck Converter Efficiency buck converter vs load current Soft-start buck converter Figure 9 Figure 10 PWM operation at nominal load current Figure 11 PWM operation at light load current Figure 12 Load transient response buck converter Figure 13 180° Phase shift between boost and buck converter Figure 14 Buck Boost Converter Efficiency buck boost converter vs load current Figure 15 PWM operation at nominal load current Figure 16 Load transient response buck boost converter PWM operation Figure 17 at light load current Figure 18 Load transient response positive charge pump boost voltage Vs = 15V Figure 19 Load transient response positive charge pump boost voltage Vs = 18V Figure 20 Charge Pump Shunt Regulator Load transient response negative shunt regulator Figure 21 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 9 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com 10 Figure 1. Figure 2. Figure 3. Figure 4. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Figure 5. Figure 6. Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 11 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com 12 Figure 9. Figure 10. Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Figure 13. Figure 14. Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 13 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com 14 Figure 17. Figure 18. Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Figure 21. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 15 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION Figure 22. Control Block TPS65166 Thermal Shutdown A thermal shutdown is implemented to prevent damages because of excessive heat and power dissipation. Once a temperature of typlically 150°C is exceeded the device enters shutdown. It enables again if the temperature drops below the threshold temperature of typically 135 °C and does normal startup. Undervoltage Lockout To avoid mis-operation of the device at low input voltages an undervoltage lockout is included, which shuts down the device at voltages lower than typically 8.0V. Short Circuit Protection The positive charge pump controller VONE will run with reduced current (typ. 50 µA) and disables the boost converter if short circuit is detected (FB4 falls below 100 mV). An exception is made at startup. If VONE has once passed the short level threshold (FB4 is above 100 mV), the boost converter will not be disabled until Power Good of VONE has been detected. In case there is already a short when the device is activated the charge pump controller VONE will run with reduced current and the boost converter will not start until the short is removed and VONE passes the short level threshold. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 The buck converter detects a short circuit if FB2 falls below 400 mV and the whole device except the buck converter itself is shut down as if EN2 would be disabled. The switching frequency of the buck converter is reduced to 1/4th of the normal operation frequency. If the short is removed the buck converter will start operation again and the whole device auto recovers to normal operation by doing startup sequencing as if EN2 would be enabled. The negative buck boost converter VOFFE has a short circuit protection where the switch current is limited to typically 300 mA and switching frequency is reduced to about 150 kHz. A short is detected if VOFFE rises above -3 V. The shunt regulator Vss has no short circuit protection. Start-Up Sequencing The device has adjustable start-up sequencing to provide correct sequencing as required by the display. VIN EN1 Vlogic EN2 VSS VOFFE GD GD ok DLY1 DLY2 < DLY1 VS DLY2 VONE DLY2 > DLY1 Power Good for Scan Drive IC DLY2 PG Figure 23. Power Up Sequencing EN1 enables the buck converter. EN2 enables the negative buck boost converter VOFFE and Vss at the same time. DLY1 sets the delay time for the boost converter Vs and DLY2 sets the delay time for VONE. VONE does not start until DLY1 is elapsed. For simultaneous startup of Vs and VONE, DLY2 should be set to 0 by not connecting the DLY2 pin. Once VS and VONE are in regulation, PG goes high impedance to enable the scan driver IC. Power Good Output The power good output PG is an open drain output with typically 450Ω resistance and requires a pull-up resistor to the 3.3V rail. The power good goes high impedance when the Vs and VONE voltage rails are in regulation and provides an enable signal for the external scan driver IC. Once power good is high impedance, the signal is latched until Vs or VONE detect a short circuit. The resulting maximum PG voltage if PG is low is dependent on R22 connection voltage (Vlogic) and R22 value. To calculate maximum resulting PG voltage for power bad signal use following formula: Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 17 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com VPG _ low = 450W ´ Vlog ic 450W + R 22 (1) The resulting PG voltage if PG pin is high impedance is dependent on R22 connection voltage (Vlogic), R22 value and output current Iout of PG node. The output current is flowing to the external scan driver. Assuming a maximum switch leakage current of 1µA the minimum PG output voltage can be calculated as following: VPG _ high = Vlog ic - R 22 ´ (1m A + Iout ) (2) Recommended are R22 values between 5kΩ and 500kΩ. Typical value for R22 is 10kΩ. Setting the Delay Times DLY1, DLY2 Connecting an external capacitor to the DLY1 and DLY2 pins sets the delay time. The capacitor is charged with a constant current source of typically 5µA. The delay time is terminated when the capacitor voltage has reached the threshold voltage of Vth = 1.24V. If no capacitor is set, the delay time is zero. The external capacitors can be calculated as follows: 5 mA ´ DLY 5 mA ´ DLY CDLY = = , with DLY = Desired delay time Vth 1.24 V (3) Example for setting a delay time of 2.5ms: 5 mA ´ 2.5 ms CDLY = = 10.1 nF Þ CDLY = 10 nF 1.24 V (4) Boost Converter The non-synchronous current mode boost converter operates in Pulse Width Modulation (PWM) operation with a fixed frequency of 750 kHz. For maximum flexibility and stability with different external components the converter uses external loop compensation. At start up the boost converter starts with an externally adjustable soft-start. The boost converter provides the supply voltage for the LCD source driver as well as for the charge pump regulator VONE. This needs to be taken into account when defining the output current requirements for the boost converter. No feed-forward capacitor is needed for proper operation. 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 SW1 SW2 Switch GD Current Sampling & Slope Compensation IGD 10kW 6V AVIN VL ISS Current Limit & Softstart SS COMP Error Amplifier Comparator D N-MOS Control Logic FB1 S PGND1 1.24V Overvoltage Comparator PGND2 750kHz Oscillator 1.24V + 3% OS Overvoltage Comperator Short circuit Comparator 1.24V 100 mV HVS S D RHVS 450W Figure 24. Boost Converter Block Diagram Soft-Start (Boost Converter) To avoid high inrush current during start-up an internal soft-start is implemented. The soft-start time is set by an external capacitor connected to the SS pin. The capacitor is charged with a constant current of typically 10µA, which increases the voltage at the SS pin. The internal switch current limit is proportional to the SS pin voltage and rises with rising voltage until VS is in regulation or the maximum current limit is reached. The larger the soft-start capacitor value the longer the soft-start time. For a 100nF capacitor at the SS pin, the current limit is reached after 0.9ms. An estimation of the current limit slope ΔIinductor and CSS capacitor can be made by the following formulas. D Iinductor 0.43 mA 2 ´ = Dt CSS V CSS = 0.43 ´ D t mA 2 ´ D Iinductor V (5) Compensation (Boost Converter) The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The typical value of R4 = 39kΩ and C5 = 1nF is appropriate for most applications. The below formula calculates at what frequency the resistor R4 increases the high frequency gain. fZ = 1 2 ´ p ´ R 4 ´ C5 (6) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 19 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Gate Drive Pin (GD) and Isolation Switch Selection The external isolation switch disconnects the boost converter once the device is turned off. If the boost converter is enabled by EN2 and the delay time set by DLY1 passed by, the gate pin GD is pulled low by an internal 10 µA current sink to minimize inrush current until the Gate-Source voltage is clamped at about VIN -6 V. An internal 10 kΩ pull up resistor to VIN is connected to GD to open the isolation switch if the Gate Drive is disabled. Using a gate drain capacitor of typically 1 nF allows to increase the turn on time of the MOSFET for further inrush current minimization. If the boost feedback voltage falls below 100mV for more than 1.4 ms, GD is pulled high and the boost converter shuts down. The device does not recover automatically from shut down but Enable or unvervoltage lockout must be toggled. Using this configuration allows to optimize the solution to specific application requirement and different MOSFETs can be used. A standard P-Channel MOSFET with a current rating close to the maximal used switch current of the boost converter is sufficient. The worst case power dissipation of the isolation switch is the maximal used switch current x RDS(on) of the MOSFET. A standard SOT23 package or similar is able to provide sufficient power dissipation. Table 1. Isolation Switch Selection COMPONENT SUPPLIER CURRENT RATING Vishay Siliconix Si3443CDV 4.7 A / 60 mΩ Vishay Siliconix Si3433DS 6 A / 38 mΩ International Rectifier IRLML6402 3.7 A / 65 mΩ Switch GD I (GD) 6V R (GD) Vin Figure 25. GD Drive High Voltage Stress Test (HVS) The device has a high voltage stress test. This allows programming the boost converter output voltage VS higher by the resistor connected to RHVS once HVS is pulled high. With HVS = high the RHVS pin is switched to GND. The resistors R2 and R3 are connected parallel and therefore the overall resistance is reduced. This changes the output voltage during the High Voltage Stress Test to a higher value: R1 + R2||R3 R1 + R2||R3 VsHVS = VFB1 = 1.24V R2||R3 R2||R3 (7) R3 = R1 ´ R2 æ VsHV S ö - 1÷ ´ R2 - R1 ç è VFB 1 ø = R1 ´ R2 æ VsHVS ö - 1÷ ´ R2 - R1 ç è 1.24V ø (8) With: VsHVS = Boost converter output voltage with HVS high Overvoltage Protection The boost converter has two overvoltage protection mechanisms for the switch. Vs is monitored with an overvoltage protection comparator on the OS pin and as soon as 19.5V typical is reached, the boost converter stops switching. The converter also detects overvoltage if the feedback voltage at the feedback pin FB1 is 3% above the typical regulation voltage of 1.24V, which stops switching. The converter starts switching again if the output voltage falls below the overvoltage thresholds. 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Input Capacitor Selection For good input voltage filtering, low ESR ceramic capacitors are recommended. All input voltages (AVIN, VIN1, 2, 3) are shorted internally. It is recommended to short AVIN, VIN1, and VIN2 externally on the PCB by a thick conducting path to avoid high currents between the VIN pins inside the device and to place two 10µF input capacitors as close as possible to these pins. Another 10µF input capacitor should be placed close to VIN3. For better input voltage filtering the input capacitor values can be increased. If it is not possible to place the 10µF capacitors close to the device, it is recommended to add an additional 1µF or 4.7µF capacitor which should be placed next to the input pins. To reduce power losses at the external isolation switch, a filter capacitor C3 at the input terminal of the inductor is required. To minimize possible audible noise problems, two 10µF capacitors in parallel are recommended. More capacitance further reduces the ripple current across the isolation switch. See Table 2 for input capacitor selection. Table 2. Input Capacitor Selection CAPACITOR COMPONENT SUPPLIER 10µF/16V Murata, GRM31CR71C106KAC7 10µF/16V Taiyo Yuden, EMK325BJ106MN 10µF/16V Murata, GRM31CR61C106KA88 Boost Converter Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. To simplify the calculation, the fastest approach is to estimate the converter efficiency by taking the efficiency numbers from the provided efficiency curves or to use a worst case assumption for the expected efficiency, e.g., 90%. The calculation must be made with the minimum assumed input voltage where peak switch current is the highest. The inductor and external Schottky diode has to be able to handle this current. V ´ h 1. Converter Duty Cycle: D = 1 - in Vout V ´ Dö æ 2. Maximum output current: Iout = ç Iswpeak - in ÷ ´ (1- D) 2fs ´ L ø è V ´ D Iout 3. Peak switch current: Iswpeak = in + 2fs ´ L 1- D (9) With, Iswpeak = Converter peak switch current (minimum switch current limit = 4.2 A) fs = Converter switching frequency (typical 750 kHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption) Inductor Selection (Boost Converter) The boost converter is able to operate with 6.8µH to 15µH inductors, a 10µH inductor is typical. The main parameter for inductor selection is the saturation current of the inductor, which should be higher than the peak switch current as calculated in the Design Procedure section with additional margin to cover for heavy load transients. The alternative more conservative approach is to choose an inductor with saturation current at least as high as the minimum switch current limit of 4.2A. Another important parameter is the inductor dc resistance. Usually the lower the dc resistance the higher the efficiency. For a boost converter where the inductor is the energy storage element, the type and core material of the inductor influences the efficiency as well. The efficiency difference among inductors can vary up to 10%. Possible inductors are shown in Table 3. Table 3. Inductor Selection Boost Converter INDUCTOR VALUE COMPONENT SUPLIER SIZE (L×W×H mm) Isat/DCR 10 µH Sumida CDRH103R 10.3 × 10.5 × 3.1 3.2 A/45 mΩ 10 µH Sumida CDRH8D38 8.3 × 8.3 × 4.0 3 A/38 mΩ Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 21 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Table 3. Inductor Selection Boost Converter (continued) INDUCTOR VALUE COMPONENT SUPLIER SIZE (L×W×H mm) Isat/DCR 10 µH Sumida CDRH104R 10.3 × 10.5 × 4.0 4.4 A/26 mΩ 10 µH Sumida CDRH8D43 8.3 × 8.3 × 4.5 4 A/29 mΩ Rectifier Diode Selection (Boost Converter) To achieve high efficiency a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the boost converter. The average rectified forward current Iavg, the Schottky diode needs to be rated for, is equal to the output current Iout. Iavg = Iout (10) Usually a Schottky diode with 2A maximum average rectified forward current rating is sufficient for most applications. The Schottky rectifier can be selected with lower forward current capability depending on the output current Iout, but has to be able to dissipate the power. The dissipated power is calculated according to the the following equation: PD = Iavg × Vforward (11) Table 4. Rectifier Diode Selection (Boost Converter) Vr/Iavg Vforward RθJA SIZE COMPONENT SUPPLIER 20V/2A 0.44V at 2A 25°C/W SMB B220, DIODES Incorporated 20V/2A 0.44V at 2A 75°C/W SMB SL22, Vishay Semiconductor 20V/3A 0.44V at 3A 46°C/W SMC MBRS320, International Rectifier Output Capacitor Selection (Boost Converter) For the best output voltage filtering, low ESR ceramic output capacitors are recommended. Three 22µF or six 10µF ceramic output capacitors with sufficient voltage rating in parallel are adequate for most applications. Additional capacitors can be added to improve the load transient regulation. See Table 5 for output capacitor selection. Table 5. Output Capacitor Selection (Boost Converter) CAPACITOR COMPONENT SUPPLIER 22µF/25V Murata, GRM32ER61E226KE15 10µF/25V Murata, GRM31CR61E106KA12 10µF/50V Taiyo Yuden, UMK325BJ106MM Setting the Output Voltage (Boost Converter) The output voltage is set by an external resistor divider. A minimum current of 100µA through the feedback divider provides good accuracy and noise covering. The resistors are calculated as: R1 ö R1 ö æ æ Vs = VFB1 ´ ç 1+ ÷ = 1.24 V ´ ç 1+ R2 ÷ R2 è ø è ø R2 = VFB1 100 mA = 1.24 V » 12 kW 100 mA (13) æ V ö æ Vs ö R1 = R2 ´ ç s - 1÷ = R2 ´ ç - 1÷ è 1.24 V ø è VFB1 ø 22 (12) Submit Documentation Feedback (14) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Buck Converter VIN1 S D The non-synchronous current mode buck converter operates at fixed frequency PWM operation. The converter drives an internal N-channel MOSFET switch with an internal bootstrap capacitor. The output voltage can be set between 2.5V and 3.3V by an external feedback divider. If the feedback voltage FB2 is 15% above the reference voltage of 1.24V the converter stops switching and starts switching again if the FB2 voltage falls below the threshold. For 3.3V output voltage the overvoltage lockout is approximately 3.8 V. SW3 N-MOS Current Sampling & Slope Compenation VIN2 Current Comparator SW4 Error Amplifier Control Logic 1.24 V FB2 Current Limit & Softstart Overvoltage Comparator Clock 1.24 V + 15% Clock / 2 0.8 V Clock / 4 0.4 V Logic 750 kHz Oscillator Clock selection for short circuit and Softstart Figure 26. Buck Converter Block Diagram Soft-Start (Buck Converter) To avoid high inrush current during start-up, an internal soft-start is implemented. When the buck converter is enabled, its current limit is reduced and it slowly rises (1ms to 2ms) to the switch current limit. For further inrush current limitation, the switching frequency is reduced to 1/4 of the switching frequency fs until the feedback voltage FB2 reaches 0.4V, then the switching frequency is set to 1/2 of fs until FB2 reaches 0.8V when the full switching frequency fs (750kHz) is applied. See the internal Block diagram (Figure 26) for further explanation. The soft-start is typically completed in 1ms to 2ms. Buck Converter Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the buck converter supports the specific application requirements. To simplify the calculation, the fastest approach is to estimate the converter efficiency by taking the efficiency numbers from the provided efficiency curves or to use a worst case assumption for the expected efficiency, e.g., 80%. The calculation must be for the maximum assumed input voltage where the peak switch current is the highest. The inductor and external Schottky diode have to be able to handle this current. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 23 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com 1. Converter Duty Cycle: D= Vout Vin ´ h 2. Maximum output current: Iout = Iswpeak - 3. Peak switch current: Iswpeak = Iout + Vin ´ (1 - D) 2fs×L Vin ´ (1- D) 2fs ´ L ´D ´D (15) With; Iswpeak = Converter peak switch current (minimum switch current limit = 2.6A) fs = Converter switching frequency (typical 750kHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency curves or 0.8 as an assumption) Inductor Selection (Buck Converter) The buck converter is able to operate with 6.8µH to 15µH inductors, a 10µH inductor is typical. The main parameter for inductor selection is the saturation current of the inductor which should be higher than the maximum output current plus the inductor ripple current as calculated in the Design Procedure section. The highest inductor current occurs at maximum VIN. The alternative more conservative approach is to choose an inductor with saturation current at least as high as the minimum switch current limit of 2.6A. Another important parameter is the inductor dc resistance. Usually the lower the dc resistance the higher the efficiency; the type and core material of the inductor influences the efficiency as well. The efficiency difference among inductors can vary up to 10%. Possible inductors are shown in Table 6. Table 6. Inductor Selection Buck Converter INDUCTOR VALUE COMPONENT SUPPLIER SIZE (L×W×H mm) Isat/DCR 10µH Sumida CDRH6D38 7.0 × 7.0 × 4.0 2.0A/28mΩ 10µH Sumida CDRH8D28 8.3 × 8.3 × 3 2.5A/36mΩ 10µH Sumida CDRH103R 10.3 × 10.5 × 3.1 3.2A/45mΩ Rectifier Diode Selection (Buck Converter) To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the buck converter. The average rectified forward current Iavg, the Schottky diode needs to be rated for, is calculated as the off time of the buck converter times the output current. Iavg = Iout × (1 – D) (16) Usually a Schottky diode with a 2A maximum average rectified forward current rating is sufficient for most applications. The Schottky rectifier can be selected with lower forward current capability depending on the output current Iout, but has to be able to dissipate the power. The dissipated power is the average rectified forward current times the diode forward voltage. The efficiency rises with lower forward voltage. PD = Iavg × Vforward (17) Table 7. Rectifier Diode Selection (Buck Converter) 24 Vr/Iavg Vforward RθJA SIZE COMPONENT SUPPLIER 20V/2A 0.44V at 2A 25°C/W SMA B220A, DIODES Incorporated 20V/2A 0.5V at 2A 75°C/W SMB SS22, Vishay Semiconductor 20V/3A 0.5V at 3A 50°C/W SMA B320A, DIODES Incorporated Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Output Capacitor Selection (Buck Converter) For best output voltage filtering, low ESR ceramic output capacitors are recommended. Two 22µF or four 10µF ceramic output capacitors with sufficient voltage rating in parallel are adequate for most applications. Additional capacitors can be added to improve the load transient regulation. See Table 8 for output capacitor selection. Table 8. Output Capacitor Selection (Buck Converter) CAPACITOR COMPONENT SUPPLIER 22µF/6.3V Murata, GRM31CR60J226KE19 10µF/6.3V Murata, GRM21BR70J106KE76 47µF/6.3V Murata, GRM32ER60J476ME20 10µF/6.3V Taiyo Yuden, JWK212BJ106MD Setting the Output Voltage (Buck Converter) The output voltage is set by an external resistor divider. R6 should be chosen in the range of 0.5kΩ to 4.7kΩ. For good noise covering and accuracy the lower feedback resistor R6 is selected to obtain at least a 250µA minimum load current. æ R5 ö æ R5 ö Vlogic = VFB2 ´ ç 1+ ÷ = 1.24 V ´ ç 1+ R6 ÷ R6 è ø è ø R6 = VFB2 (18) 1.24 V » 1.2 k W 1 mA = 1mA (19) æ Vlogic ö æ Vlogic ö - 1÷ = R6 ´ ç - 1÷ R5 = R6 ´ ç çV ÷ ç 1.24 V ÷ è FB2 ø è ø (20) Negative Buck-Boost Converter VOFFE, Temperature Compensation The non-synchronous constant off-time current mode buck-boost converter generates the negative VOFFE voltage rail. This output rail is required to power the scan driver. The output voltage is temperature compensated and fully adjustable from –22V to –5V. The external resistor divider on pins FB5 and SET allow programming high and low voltage levels. The graph below shows the output voltage versus temperature in °C and series resistor R19 (5kΩ to 7.5kΩ). NTC (22kΩ) and R18 (30kΩ) define the slope of the curve, R19 allows selection of the temperature point where temperature compensation begins and ends. The converter is compensated internally, for further stabilization the feed-forward capacitor C22 can be chosen between 100pF and 2nF. Soft-start is also realized with this capacitor. The larger the capacitor value the longer the soft-start time. The recommended C22 value is 1nF. -10 V -11 V 7.5 kW 7 kW -12 V -14 V -15 V -16 V Vref 3.3 V 6.5 kW -13 V Slope of curve adjusted by NTC and R18 6 kW VOFFE_max set by resistor network FB5 and SET 5.5 kW 5 kW R18 NTC -17 V TS -18 V -19 V R19 -20 V VOFFE_min set by resistor network FB5 -21 V -22 V -23 V -10ºC 0ºC 10ºC 20ºC 30ºC 40ºC 50ºC Figure 27. VOFFE Temperature Compensation Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 25 TPS65166 S VIN3 D SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com SW5 P-MOS Overvoltage Protection Short circuit Protection Current Limit Current Mode Control SET Current Comparator 2x TS Error Amplifier V ref/ 2 clamp FB5 Figure 28. Buck-Boost Converter Block Diagram Setting the Minimal and Maximal Output Voltage, VOFFE Keep in mind that VOFFE has a negative value, while Vlogic and VSET have positive values: VOFFE_min = Vlogic 2 æ R21 ö æ R21 ö ´ ç 1÷ = 1.65 V ´ ç 1- R20 ÷ , select R21 about 1 MW to achieve good soft-start. R20 è ø è ø (21) R20 = Vlogic ´ R21 Vlogic - 2×VOFFE_min = 3.3 V ´ R21 3.3 V - 2 ´ VOFFE_min VOFFE_max = VSET - (Vlogic - VSET ) ´ VSET = R21 R21 = VSET - (3.3V - VSET ) ´ , VSET is calculated below. R20 R20 VOFFE_max ´ R20 + Vlogic ´ R21 VSET = Vlogic ´ R20 + R21 (22) = (23) VOFFE_max ´ R20 + 3.3 V ´ R21 R20 + R21 (24) R17 R17 = 3.3 V ´ , select R17 between 1 kW and 20 kW for good accuracy. R16 + R17 R16 + R17 (25) æ Vlogic ö æ 3.3V ö - 1÷÷ = R17 ´ ç - 1÷ R16 = R17 ´ çç V V è SET ø è SET ø (26) Setting the Start and End Temperature of the Compensation The resistance of a NTC termistor decreases nonlinearly with rising temperature. RNTC (T) = R T0 ´ æ 1 1ö - B×çç - ÷÷ T0 Tø è e (27) Where, RT0 is the resistance at an absolute temperature T0 in Kelvin (normally 25°C) T is the temperature in Kelvin (°C + 273.15 K/°C) B is a material constant 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 The NTC termistor manufacturer provides the above parameters. Typically a 22kΩ NTC is used. Table 9 provides a suggestion for NTCs. Table 9. Negative Termistor Selection RESISTANCE (25°C) B CONSTANT COMPONENT SUPPLIER COMMENT 22kΩ 3950 K Murata, NCP18XW223E ±3% 22kΩ 3800 K Vishay, NTCS0805E3223FHT ±1% 22kΩ 4554 K TDK, NTCG164LH223HT ±3% To linearize the resistance-temperature characteristic of the NTC termistor, a parallel resistor R18 is added. T is the temperature at which the NTC characteristic curve is linearized. Typically T is located in the middle of the set temperature range at which the VOFFE voltage should be adjusted. For example, if the temperature compensation should start at 0°C and stop at 25°C T = 12.5°C + 273.15 K/°C = 285.65 K. B - 2T R18 = RNTC (T) ´ B + 2T (28) The resulting overall resistance RNTC||R18 can be calculated as follows. R18 ´ RNTC (T) RNTC||R18 = R18 + RNTC (T) (29) 30 kW 250 kW 25 kW 200 kW 20 kW 150 kW 15 kW 100 kW 10 kW 50 kW 5 kW 0 kW -20ºC 0ºC 20ºC 40ºC 60ºC 80ºC 0 kW -20ºC 0ºC 20ºC 40ºC 60ºC 80ºC Figure 29. Resistance-Temperature Characteristics NTC (22 kΩ) and Linearized NTC Network at 12.5°C To achieve different slopes, different R18 values are required. To obtain the most linear slope, the calculated value has to be used. To achieve steeper slopes, higher values for R18 are necessary, smaller values produce shallower slopes. By adjusting the resistor R19, the start and end point of the compensation can be set. The voltage VTS of the resistor network at TS is calculated by the following equation: VTS = Vlogic ´ R19 R19 = 3.3 V ´ RNTC||R18 + R19 RNTC||R18 + R19 (30) Finally, the resulting output voltage, VOFFE, during the compensation period can be calculated as follows: VOFFE = 2VTS - (Vlogic - 2VTS ) ´ R21 R21 = 2VTS - (3.3V - 2VTS ) ´ R20 R20 (31) Figure 30 shows examples for VOFFE_min = –22V and VOFFE_max = –11V with different slopes and starting points of the temperature compensation. For further compensation characteristics, refer to the available TPS65166 support excel sheet. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 27 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com -10 V -10 V -11 V -11 V -12 V 6 kW 10 kW -13 V 7 kW -14 V 12 kW -14 V -15 V 15 kW -15 V -12 V -13 V -16 V 8 kW 9 kW -16 V 20 kW -17 V 25 kW -17 V -18 V 30 kW -18 V 10 kW 11 kW -19 V -19 V -20 V -20 V -21 V R18 = open -21 V R18 = 51 kW -22 V -22 V -23 V -10ºC 0ºC 10ºC 20ºC 30ºC 40ºC 50ºC -23 V -10ºC 0ºC 10ºC 20ºC 30ºC 40ºC 50ºC -10 V -10 V -11 V -11 V 5.5 kW -12 V -14 V 2.7 kW -16 V 5 kW -17 V 2.8 kW -15 V 4.5 kW -16 V 2.9 kW -14 V 4 kW -15 V 3 kW -13 V 3.5 kW -13 V 3.1 kW -12 V 2.5 kW -17 V 5.2 kW -18 V -18 V -19 V -19 V -20 V -20 V -21 V -21 V R18 = 20 kW R18 = 10 kW -22 V -22 V -23 V -10ºC 0ºC 10ºC 20ºC 30ºC 40ºC 50ºC -23 V -10ºC 0ºC 10ºC 20ºC 30ºC 40ºC 50ºC Figure 30. Temperature Compensation Examples for R18 = open, 51 kΩ, 20 kΩ, 10 kΩ Buck-Boost Converter Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the buck-boost converter supports the specific application requirements. To simplify the calculation, the fastest approach is to estimate converter efficiency by taking the efficiency numbers from the provided efficiency curves or to use a worst case assumption for the expected efficiency, e.g., 80%. The calculation must be performed for the minimum assumed input voltage where the peak switch current is the highest. The inductor and external Schottky diode have to be able to handle this current. - Vout 1. Converter Duty Cycle: D= Vin ´ h - Vout V ´ Dö æ 2. Maximum output current: Iout = ç Iswpeak - in ÷ ´ (1- D) 2fs×L ø è 3. Peak switch current: Iswpeak = Iout V - D + in 1- D 2fs ´ L (32) With, Iswpeak = Converter peak switch current (minimum switch current limit = 1.1A) fs = Converter switching frequency (typical 750 kHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency curves or 0.8 as an assumption) 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Inductor Selection (Buck-Boost Converter) The buck-boost converter is able to operate with 10µH to 47µH inductors, a 22µH inductor is typical. The main parameter for inductor selection is the saturation current of the inductor which should be higher than the peak switch current as calculated in the Design Procedure section with additional margin to cover for heavy load transients. The alternative more conservative approach is to choose an inductor with saturation current at least as high as the minimum switch current limit of 1.1A. Another important parameter is the inductor dc resistance. Usually the lower the dc resistance the higher the efficiency. The type and core material of the inductor influences the efficiency as well. The efficiency difference among inductors can vary up to 5%. Possible inductors are listed in Table 10. Table 10. Inductor Selection Buck-Boost Converter INDUCTOR VALUE COMPONENT SUPPLIER SIZE (LxWxH mm) Isat/DCR 22µH Sumida CDRH3D23/HP 4.0 × 4.0 × 2.5 0.8A/306mΩ 22µH Sumida CDRH4D22/HP 5.0 × 5.0 × 2.4 1.1A/214mΩ 22µH Sumida CDH3D13D/SHP 3.2 × 3.2 × 1.5 0.6A/753mΩ Rectifier Diode Selection (Buck-Boost Converter) To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the buck-boost converter. The average rectified forward current, Iavg, the Schottky diode needs to be rated for, is equal to the output current, Iout. Iavg = Iout (33) Usually a Schottky diode with a 500mA maximum average rectified forward current rating is sufficient for most applications. The Schottky rectifier can be selected with lower forward current capability depending on the output current Iout, but has to be able to dissipate the power. The dissipated power is the average rectified forward current times the diode forward voltage. The efficiency rises with lower forward voltage. PD = Iavg × Vforward (34) Table 11. Rectifier Diode Selection (Buck-Boost Converter) Vr/Iavg Vforward RθJA SIZE COMPONENT SUPPLIER 40V/0.5A 0.43V at 0.5A 206°C/W SOD-123 MBR0540, Vishay Semiconductor 40V/1A 0.42V at 0.5A 88°C/W SMA SS14, Fairchild Semiconductor Output Capacitor Selection (Buck-Boost Converter) For the best output voltage filtering, low ESR ceramic capacitors are recommended. One 22µF or two 10µF output capacitors with sufficient voltage ratings in parallel are adequate for most applications. Additional capacitors can be added to improve load transient regulation. See Table 12 for output capacitor selection. Table 12. Output Capacitor Selection (Buck-Boost Converter) CAPACITOR COMPONENT SUPPLIER 22µF/25V Murata, GRM32ER61E226KE15 10µF/25V Murata, GRM31CR61E106KA12 10µF/50V Taiyo Yuden, UMK325BJ106MM Positive Charge Pump Regulator (VONE) This output rail is required to power the scan driver and is generated with a charge pump doubler stage running from Vs and using the switch node of the boost converter. The external PNP transistor regulates the output voltage to the programmed voltage set by the feedback resistor divider. Power dissipation and average collector current of the transistor must be taken into consideration when choosing a suitable transistor. Also the power dissipation of the resistor R12 must be considered. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 29 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Setting the Output Voltage and Selecting the Feed-Forward Capacitor (Positive Charge Pump) To minimize noise a minimum current through the feedback divider of 500 µA is recommended. At startup the device is in short circuit mode with reduced current (typ. 50 µA) until the feedback voltage FB4 exceeds 100 mV, then the device switches to soft-start mode until the output voltage VONE is in regulation. Due to the high output current and low required voltage drop, high current Schottky diodes with low forward voltage are recommended for this regulator. æ R14 ö æ R14 ö Vout = VFB4 ´ ç 1+ = 1.24 V ´ ç 1+ ÷ ÷ è R15 ø è R15 ø (35) VFB4 1.24V R15 = = » 2.4 kW 500 mA 500 mA (36) æ V ö æ V ö R14 = R15 ´ ç out - 1÷ = R15 ´ ç out - 1÷ V 1.24 V è ø è FB4 ø (37) To minimize noise and leakage current sensitivity keep the lower feedback divider resistor R15 between 100Ω and 4.7kΩ. See typical application section for charge pump circuit. Across the upper feedback resistor R14, a bypass capacitor C17 is required. The capacitor is calculated as: C17 = 1 2 ´ p ´ 12 kHz ´ R14 (38) Short circuit Comparator 100 mV Short circuit Mode Current Limit & Softstart Control Logic Base2 55 mA 8 mA 1.24 V Error Amplifier FB4 Figure 31. Positive Chargepump Block Diagram PNP Transistor Selection (Positive Charge Pump) The maximum possible VONE output voltage is calculated as: VONE = 2 ´ Vs + VD1 - 2 ´ VD2 - IONE ´ R - VQ D (39) With: Vs = boost converter output voltage VD1 = Forward voltage of boost converter Schottky diode VD2 = Forward voltage of charge pump diode for a current of IONE / D IONE = VONE output current D = Duty cycle of boost converter (D = 1 – Vin / Vs) R = Series resistor (if applicable, e.g., 2Ω for typical application) VQ = Transistor saturation voltage As a general recommendation the VONE voltage level in use should be at least 0.5V lower than the calculated maximum VONE voltage. 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 The power dissipation of the transistor should be calculated for the maximum applied boost output voltage VS. If high voltage stress mode (HVS) is used the maximum VS voltage occurs during HVS mode.: I æ ö Power dissipation = ç 2 ´ Vs - VONE - 2 ´ VD2 - ONE ´ R ÷ ´ IONE D è ø (40) As an example for Vs = 18V and IONE = 150mA, the power dissipation is approximately 1W. Because of the 1µF collector capacitor C16 a wide range of transistors can be used. The most important transistor parameters are Collector-Emitter voltage which must be at least 2 x VS , average current rating of 1.2 x IONE and DC current gain hFE, which must be at least IONE / IBase2. IBase2 minimum value of 8mA should be used for calculation. See Table 13 for possible transistor selection. Table 13. Transistor Selection (Positive Charge Pump) TRANSISTOR PZT2907A KTA1552T KTA1718D KTA1666 Resistor R12 Function and Power Dissipation (Positive Charge Pump) R12 is used to limit the peak current flowing from collector capacitor C16 through R12, D3 and C15 into the boost switching node. High peak currents disturb the boost converter switching which results in high VS and VONE ripple. The power dissipation for the resistor R12 can be calculated by following formula: Presistor = R12 ´ IONE2 (41) Output Capacitor Selection (Positive Charge Pump) For the best output voltage filtering, low ESR ceramic output capacitors are recommended. Two 4.7 µF ceramic output capacitors with sufficient voltage rating are adequate for most applications. Additional capacitors can be added to improve the load transient regulation. See Table 14 for capacitor selection. Table 14. Output Capacitor Selection (Positive Charge Pump) CAPACITOR COMPONENT SUPPLIER 4.7µF/50V Murata, GRM31CR71H475KA12 4.7µF/50V Taiyo Yuden, UMK316BJ475KL-T Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 31 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Negative Shunt Regulator (Vss) Vss is a shunt regulator that regulates the non-addressed TFT pixels to the programmed voltage. The pulldown resistor R11 connected to VOFFE is required to provide accurate no load current regulation. A minimum current of 50µA through the feedback divider provides good accuracy. Be aware of the negative value of Vss for the calculations. Vout = VFB3 + (VFB3 - Vlogic ) ´ Vlogic - 0.75 ´ Vlogic R10 = R9 = 80 mA = Vlogic ´ R9 R9 R9 = 0.75 ´ Vlogic = 2.475V - 0.825 ´ R10 4 ´ R10 R10 0.825 V » 10 kW 80 mA (42) (43) Vout - 0.75 ´ Vlogic Vout - VFB3 V - 2.475 V ´ R10 = ´ R10 = out ´ R10 -0.25 ´ Vlogic -0.825 V VFB3 - Vlogic (44) Discharge Resistor at VSS Output If a discharge resistor Rdis at the VSS output is used to discharge the VSS node faster, the pull down resistor R11 connected to VOFFE must be calculated by following formula to achieve the programmed output voltage at VSS. A smaller resistor to the calculated one must be used. For example for VSS = -7.5V, VOFFE = -11V and Rdis = 12kΩ the calculated R11 = 4.98kΩ and the resistor values 4.7kΩ, 4.3kΩ, and 4.0kΩ can be used. R11 = Rdis ´ (R9 + R10) ´ (VOFFE - VSS ) VSS ´ (Rdis + R9 + R10) - Vlogic ´ Rdis (45) Base1 VSNS Error Amplifier 5mA max. ¾ Vref FB3 Figure 32. Negative Shunt Regulator Block Diagram Output Capacitor Selection (Negative Shunt Regulator) For the best output voltage filtering, low ESR ceramic output capacitors are recommended. One 1µF ceramic output capacitor with a sufficient voltage rating is suitable for most applications. See Table 15 for output capacitor selection. Table 15. Output Capacitor Selection (Negative Shunt Regulator) 32 CAPACITOR COMPONENT SUPPLIER 1µF/25V Murata, GRM21BR71E105KA99 1µF/50V Taiyo Yuden, UMK325BJ105KH Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Layout Considerations PCB layout is an important step in power supply design. • NC pins 5, 8, 22, and 29 should not be connected to GND, if so, the device is not P2P short protected any more. • The input capacitors should be placed as close as possible to the device. AVIN, VIN1, and VIN2 must be shorted. • The buffer capacitor C25 must be connected to VL+ and AGND/VL- by a single trace. • The line device, diode, output cap of the buck boost should be kept as short as possible. • For the boost converter the line C3 GND output capacitor GND and PGND1 should be kept short. • For the buck converter the line switch pin SW3, 4 to diode should be kept short. • All lower feedback resistors connected to GND should be placed close to the device. • Switching lines should not be next to feedback lines to avoid coupling. • Use short lines or make sure the lines do not affect other regulating parts for the charge pump switching connection to SW1,2 because this trace carrys switching waveforms. • The PowerPAD™ of the QFN package should be soldered to GND and as much as possible thermal vias should be used to lower the thermal resistance and keep the device cool. • A solid PCB ground plane structure is essential for good device performance. • Place red marked components and lines first and as close as possible to the device. Keep red marked lines short. Bold marked lines should be wide on the PCB, because these traces carry high currents. • Green marked components can be placed further away. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 33 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Figure 33. PCB Layout Guideline 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Typical Applications Figure 34. Typical Application With Vs= 15V, HVS = 18V, Vlogic = 3.3V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 35 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Figure 35. Typical Application With Vs = 18V, HVS = 19V, Vlogic = 3.3V 36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 Figure 36. Typical Application With Vs = 18V, HVS = 19V, Vlogic = 2.5V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 37 TPS65166 SLVS976 – SEPTEMBER 2009.......................................................................................................................................................................................... www.ti.com Recommended charge pump circuits. Maximum Output Current VONE = 28V - 3% VIN VS = 15V VS ³ 16V 10.8V 200mA 200mA 12.0V 180mA 200mA 13.2V 125mA 200mA Figure 37. Typical Application VONE High Output Current Maximum Output Current VONE = 28V - 3% VIN VS = 15V VS ³ 16V 10.8V 100mA 200mA 12.0V 75mA 200mA 13.2V 50mA 200mA Figure 38. Typical Application VONE Low Output Current 38 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS65166 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS65166RHAR ACTIVE QFN RHA Pins Package Eco Plan (2) Qty 40 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS65166RHAR Package Package Pins Type Drawing QFN RHA 40 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65166RHAR QFN RHA 40 2500 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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