LTC3615 Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter Description Features n n n n n n n n n n n n n n n n n n High Efficiency: Up to 94% Dual Outputs with 2 × 3A Output Current Capability Low Output Ripple Burst Mode® Operation: IQ = 130µA 2.25V to 5.5V Input Voltage Range ±1% Output Voltage Accuracy Output Voltages Down to 0.6V Programmable Slew Rate at Switch Pins Low Dropout Operation: 100% Duty Cycle Shutdown Current ≤1µA Adjustable Switching Frequency Up to 4MHz Internal or External Compensation Selectable Pulse-Skipping/Forced Continuous/ Burst Mode Operation with Adjustable Burst Clamp Optional Active Voltage Positioning (AVP) with Internal Compensation Selectable 0°/90°/180° Phase Shift Between Channels Fixed Internal and Programmable External Soft-Start Accurate Start-Up Tracking Capability DDR Memory Mode IOUT = ±1.5A Available in 4mm × 4mm QFN-24 and TSSOP-24 Packages n n n n The operating frequency is externally programmable up to 4MHz, allowing the use of small surface mount inductors. 0°, 90°, or 180° of phase shift between the two channels can be selected to minimize input current ripple and output voltage ripple in a single 6A output configuration. Programmable slew rate limiting reduces EMI, and external synchronization can be applied up to 4MHz. The internal synchronous switches increase efficiency and eliminate the need for external catch diodes, saving external components and board space. The LTC3615 is offered in leadless 24-pin 4mm × 4mm QFN and thermally enhanced 24-pin TSSOP packages. Applications n The LTC®3615 is a dual 3A synchronous step-down regulator using a current mode, constant-frequency architecture. The DC supply current is only 130µA (Burst Mode operation at no-load) while maintaining the output voltages, dropping to zero current in shutdown. The 2.25V to 5.5V input supply range makes the LTC3615 ideally suited for single Li-Ion applications. 100% duty cycle capability provides low dropout operation, which extends operating time in battery-operated systems. Point-of-Load Supplies Distributed Power Supplies Portable Computer Systems DDR Memory Termination Handheld Devices L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5994885, 6304066, 6498466, 6580258, 6611131. Typical Application Efficiency and Power Loss vs Load Current 100 VIN PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND PVIN2 SW1 0.47µH 422k VOUT1 1.8V/3A 47µF FB1 210k SW2 0.47µH 665k FB2 PGND 210k 3615 TA01a VOUT2 2.5V/3A 47µF 80 1 70 60 0.1 50 40 0.01 30 POWER LOSS (W) SVIN PVIN1 RUN1 TRACK/SS1 PGOOD1 LTC3615 ITH1 SRLIM RT /SYNC MODE EFFICIENCY (%) 100µF 10 90 20 0.001 VIN = 3.3V VIN = 4V 10 2.25MHz VIN = 5V VOUT = 2.5V 0 0.0001 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 3615 TA01b 3615f LTC3615 Absolute Maximum Ratings (Note 1) PVIN1, PVIN2 Voltages......................–0.3V to SVIN + 0.3V SVIN Voltage.................................................. –0.3V to 6V SW1 Voltage ..............................–0.3V to (PVIN1 + 0.3V) SW2 Voltage...............................–0.3V to (PVIN2 + 0.3V) PGOOD1, PGOOD2 Voltages......................... –0.3V to 6V All Other Pins............................... –0.3V to (SVIN + 0.3V) Operating Junction Temperature Range (Note 2)........................................ –40°C to 125°C Storage Temperature............................... –65°C to 150°C Lead Soldering Temperature (TSSOP)................... 300°C Reflow Peak Body Temperature (QFN)................... 260°C Pin Configuration TOP VIEW 22 ITH1 24 23 22 21 20 19 TRACK/SS2 4 21 TRACK/SS1 SGND 5 20 SVIN PVIN2 6 PVIN2 7 19 PVIN1 MODE 3 18 PVIN1 PHASE 4 16 PGOOD2 25 PGND 15 RT/SYNC 17 SW1 FB2 5 14 RUN1 16 SW1 ITH2 6 13 RUN2 13 PGOOD2 FE PACKAGE 24-LEAD PLASTIC TSSOP 7 8 9 10 11 12 SW2 14 SRLIM SW2 15 PGOOD1 RUN1 11 PVIN2 RUN2 10 RT /SYNC 12 17 SRLIM PVIN2 9 18 PGOOD1 FB1 2 SGND SW2 8 ITH1 1 TRACK/SS2 SW2 25 PGND SW1 ITH2 SW1 23 FB1 3 PVIN1 24 MODE 2 PVIN1 1 FB2 SVIN PHASE TRACK/SS1 TOP VIEW UF PACKAGE 24-LEAD (4mm s 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 33°C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB order information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3615EFE#PBF LTC3615EFE#TRPBF LTC3615FE 24-Lead Plastic TSSOP –40°C to 125°C LTC3615IFE#PBF LTC3615IFE#TRPBF LTC3615FE 24-Lead Plastic TSSOP –40°C to 125°C LTC3615EUF#PBF LTC3615EUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3615IUF#PBF LTC3615IUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3615f LTC3615 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, RSRLIM = 40.2k, unless otherwise specified (Notes 1, 2, 11). SYMBOL PARAMETER VIN Operating Voltage Range VUVLO Undervoltage Lockout Threshold CONDITIONS SVIN Ramping Down MIN l 2.25 l 1.7 TYP 5.5 Feedback Voltage Internal Reference (Note 3) VTRACK = SVIN, VSRLIM = 0V 0°C < TJ < 85°C –40°C < TJ < 125°C l UNITS V V SVIN Ramping Up VFB MAX 2.25 V 0.592 0.590 0.6 0.608 0.610 V V Feedback Voltage External Reference (Note 7) (Note 3) VTRACK = 0.3V, VSRLIM = SVIN 0.289 0.3 0.311 V (Note 3) VTRACK = 0.5V, VSRLIM = SVIN 0.489 0.5 0.511 V IFB Feedback Input Current VFBx = 0.6V l 0 ±30 nA ∆VLINEREG Line Regulation SVIN = PVINx = 2.25V to 5.5V (Note 4) l 0.2 %/ V ∆VLOADREG Load Regulation VITHx from 0.5V to 0.9V (Note 4) VITHx = SVIN, VFBx = 0.6V (Note 5) 0.2 2 % % IS Active Mode VFB1 = 0.5V, VMODE = SVIN, VRUN2 = 0V (Note 6) 1100 µA VFBx = 0.5V, VMODE = SVIN, VRUNx = SVIN (Note 6) 1900 µA Sleep Mode VFB1 = 0.7V, VRUN1 = SVIN, VRUN2 = 0V, VMODE = 0V, VITH1 = SVIN (Note 5) 95 130 µA VFBx = 0.7V, VRUN1 = SVIN, VRUN2 = 0V, VMODE = 0V (Note 4) 145 220 µA VFBx = 0.7V, VRUNx = SVIN, VMODE =0V, VITHx = SVIN (Note 5) 130 200 µA VFBx = 0.7V, VRUNx = SVIN, VMODE =0V, ITH = (Note 4) 240 360 µA Shutdown SVIN = PVIN = 5.5V, VRUNx = 0V 0.1 1 Top Switch On-Resistance PVINx = 3.3V (Note 10) 75 mΩ Bottom Switch On-Resistance PVINx = 3.3V (Note 10) 55 mΩ Top Switch Current Limit Sourcing (Note 8), VFB = 0.5V Duty Cycle <35% Duty Cycle = 100% Bottom Switch Current Limit Sinking (Note 8), VFB = 0.7V, Forced Continuous Mode ISW(LKG) Switch Leakage Current gm(EA) IEAO tSOFT-START RDS(ON) ILIM µA 4.5 3.6 6 7.5 A A –2.5 –3.5 –5 A SVIN = PVIN = 5.5V, VRUNx = 0V 0.01 1 µA Error Amplifier Transconductance –5µA < ITH < 5µA 240 µmho Error Amplifier Output Current (Note 4) ±30 µA Internal Soft-Start Time VFBx from 0.06V to 0.54V, TRACK/SSx = SVIN 0.65 1.1 RON(TRACK/SS_DIS) TRACK/SS Pull-Down Resistance at Start-Up 1.7 ms 200 Ω tTRACK/SS_DIS Soft-Start Discharge Time at Start-Up fOSC Internal Oscillator Frequency RRT/SYNC = 178k l 1.85 2.25 2.65 MHz VRT/SYNC = SVIN l 1.8 2.25 2.7 MHz fSYNC Synchronization Frequency tLOW , tHIGH > 30ns 4 MHz VRT/SYNC SYNC Level High SYNC Level Low 70 0.4 µs 1.2 V 0.3 V 3615f LTC3615 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, RSRLIM = 40.2k, unless otherwise specified (Notes 1, 2, 11). SYMBOL PARAMETER CONDITIONS jSW1–SW2 Output Phase Shift Between SW1 and SW2 VPHASE < 0.15 • SVIN 0 Deg 0.35 • SVIN < VPHASE < 0.65 • SVIN VPHASE > 0.85 • SVIN 90 Deg 180 Deg VSRLIM Voltage at SRLIM to Enable DDR Mode VMODE (Note 9) Internal Burst Mode Operation PGOOD MIN (Note 9) TYP MAX SVIN – 0.3 V 0.3 Pulse-Skipping Mode UNITS SVIN – 0.3 V V Forced Continuous Mode 1.1 SVIN • 0.58 V External Burst Mode Operation 0.5 0.85 V Power Good Voltage Windows TRACK/SSx = SVIN, Entering Window VFBx Ramping Up VFBx Ramping Down –3.5 3.5 TRACK/SSx = SVIN , Leaving Window VFBx Ramping Up VFBx Ramping Down tPGOOD Power Good Blanking Time Entering/Leaving Window RPGOOD Power Good Pull-Down On-Resistance I = 10mA VRUN Enable Pin Input High Input Low Pull-Down Resistance Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3615 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3615E is guaranteed to meet performance specifications over the 0°C to 85°C operating junction temperature range. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3615I is guaranteed to meet specifications over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedence. l l –6 6 % % 9 –9 11 –11 % % 70 105 140 µs 8 12 30 Ω 0.4 V V 1 4 MΩ Note 3: This parameter is tested in a feedback loop which servos VFB1,2 to the midpoint for the error amplifier (VITH1,2 = 0.75V). Note 4: External compensation on ITH pin. Note 5: Tying the ITH pin to SVIN enables internal compensation and AVP mode for the selected channel. Note 6: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 7: See description of the TRACK/SS pin in the Pin Functions section. Note 8: When sourcing current, the average output current is defined as flowing out of the SW pin. When sinking current, the average output current is defined as flowing into the SW pin. Sinking mode requires the use of forced continuous mode. Note 9: See description of the MODE pin in the Pin Functions section. Note 10: Guaranteed by design and correlation to wafer level measurements for QFN packages. Note 11: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. 3615f LTC3615 Typical Performance Characteristics 100 100 VOUT = 1.8V 100 VOUT = 1.2V 90 80 80 70 70 70 60 50 40 30 40 30 0 0.001 3615 G01 Efficiency vs Load Current (VMODE = 0.55 • SVIN) 100 90 100 90 80 70 70 EFFICIENCY (%) 80 60 50 40 30 20 60 50 40 30 0 0.001 80 75 70 65 IOUT = 3A IOUT = 2A IOUT = 1A IOUT = 0.3A IOUT = 0.2A 55 50 2.25 10 0.01 0.1 1 OUTPUT CURRENT (A) 3615 G04 2.75 3615 G05 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25 3615 G06 Line Regulation 0.20 0.15 0.10 0.1 0 EXTERNAL –0.1 COMPENSATION 0.05 0 –0.05 –0.10 –0.2 –0.15 –0.3 –0.4 10 3615 G03 VOUT = 1.8V 60 VIN = 2.25V VIN = 3.3V VIN = 5V VOUT ERROR (%) 0.3 0.01 0.1 1 OUTPUT CURRENT (A) 3615 G02 85 INTERNAL COMPENSATION (ITH = SVIN ) 0.2 VIN = 3.3V VIN = 4V VIN = 5V 90 VMODE = 1.5V 0.4 30 Efficiency vs Input Voltage (VMODE = 0V) Load Regulation 0.5 40 95 10 10 0.01 0.1 1 OUTPUT CURRENT (A) VOUT ERROR (%) 0 0.001 50 0 0.001 VOUT = 1.2V 20 VIN = 2.25V VIN = 3.3V VIN = 5V 10 60 Efficiency vs Load Current (VMODE = 0.55 • SVIN) VOUT = 1.8V VOUT = 2.5V 10 10 0.01 0.1 1 OUTPUT CURRENT (A) Efficiency vs Load Current (VMODE = 0V) 20 VIN = 2.5V VIN = 3.3V VIN = 5V 10 10 0.01 0.1 1 OUTPUT CURRENT (A) 50 EFFICIENCY (%) 0 0.001 60 20 VIN = 2.5V VIN = 3.3V VIN = 5V 10 EFFICIENCY (%) 80 20 EFFICIENCY (%) Efficiency vs Load Current (VMODE = 0V) 90 EFFICIENCY (%) EFFICIENCY (%) 90 Efficiency vs Load Current (VMODE = 0V) VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. 0 0.5 1 1.5 2 OUTPUT CURRENT (A) 2.5 3 3615 G07 –0.20 2.25 2.75 3.25 3.75 4.25 INPUT VOLTAGE (V) 4.75 5.25 3615 G08 3615f LTC3615 Typical Performance Characteristics Forced Continuous Mode Operation (FCM) Pulse-Skipping Mode Operation VOUT 20mV/DIV IL 200mA/DIV VOUT = 1.8V IOUT = 100mA VMODE = 1.5V 1µs/DIV VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. Burst Mode Operation VOUT 20mV/DIV VOUT 20mV/DIV IL 500mA/DIV IL 500mA/DIV VOUT = 1.8V IOUT = 75mA VMODE = 3.3V 3615 G09 Load Step Transient in FCM External Compensation 20µs/DIV 3615 G10 VOUT = 1.8V IOUT = 75mA VMODE = 0V VOUT 200mV/DIV VOUT 200mV/DIV IL 1A/DIV IL 1A/DIV IL 1A/DIV 3615 G12 VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 3.3V COMPENSATION FIGURE 1 VOUT 100mV/DIV 3615 G14 Internal Start-Up in Forced Continuous Mode RUN 1V/DIV VOUT 200mV/DIV VOUT 500mV/DIV IL 1A/DIV PGOOD 2V/DIV IL 1A/DIV IL 2A/DIV 0A VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 1.5V VITH = 3.3V OUTPUT CAPACITOR VALUE FIGURE 1 VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 0V COMPENSATION FIGURE 1 3615 G13 Load Step Transient in Forced Continuous Mode Sourcing and Sinking Current Load Step Transient in FCM with AVP Mode 3615 G11 Load Step Transient in Burst Mode Operation Load Step Transient in Pulse-Skipping Mode VOUT 200mV/DIV VOUT = 1.8V 50µs/DIV ILOAD = 100mA TO 3A VMODE = 1.5V COMPENSATION FIGURE 1 20µs/DIV 3615 G15 VOUT = 1.8V 50µs/DIV ILOAD = –1.5A TO 3A VMODE = 1.5V COMPENSATION FIGURE 1 3615 G16 VOUT = 1.8V IOUT = 3A VMODE = 1.5V 500µs/DIV 3615 G17 3615f LTC3615 Typical Performance Characteristics Reference Voltage vs Temperature Switch On-Resistance vs Input Voltage 0.10 0.606 0.09 0.604 0.08 MAIN SWITCH 0.07 0.602 RDS(ON) (Ω) REFERENCE VOLTAGE (V) VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. 0.600 0.598 0.06 0.05 SYNCHRONOUS SWITCH 0.04 0.03 0.02 0.596 0.01 0.594 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 0 2.25 3.25 3615 G18 Switch On-Resistance vs Temperature 4.0 100 90 3615 G19 Frequency vs RT/SYNC 3.2 70 2.8 60 2.4 50 5.25 3.6 MAIN SWITCH fOSC (MHz) RDS(ON) (µA) 80 4.25 VIN (V) SYNCHRONOUS SWITCH 40 2.0 1.6 30 1.2 20 0.8 10 0.4 0 100 200 300 400 500 600 700 800 900 1000 RT/SYNC (kΩ) 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3615 G20 3615 G22 Frequency vs Temperature Frequency vs Input Voltage 2.7 2.60 2.6 2.50 2.5 2.40 2.2 RT /SYNC = SVIN RT = 178k 2.1 fOSC (MHz) fOSC (MHz) 2.3 RT/SYNC = SVIN 2.30 2.4 2.20 2.10 RT/SYNC = 200k 2.00 1.90 2.0 1.80 1.9 1.70 1.8 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1.60 2.25 3615 G23 3.00 3.75 VIN (V) 4.50 5.25 3615 G24 3615f LTC3615 Typical Performance Characteristics No Load Supply Current vs Input Voltage Switch Leakage vs Temperature 1.8 VIN = 5.5V 1.2 1.0 MAIN SWITCH 0.8 0.6 SUPPLY CURRENT (µA) SWITCH LEAKAGE (µA) 1.4 SYNCHRONOUS SWITCH 0.2 180 180 140 140 MODE = 0V 160 RUNx = ITHx = SVIN 1.6 0.4 120 100 80 60 40 0 2.25 Slew Rate of Falling Edge at SW1/2 vs SRLIM Resistor 80 60 40 2.75 3.25 3.75 4.25 VIN (V) 4.75 5.25 3615 G26 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3615 G27 Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor VIN = 3.3V VOUT = 1.8V IOUT = 1A SRLIM = SGND OR SVIN 40.2k 100k 120 100 20 3615 G25 VIN = 3.3V VOUT = 1.8V IOUT = 1A MODE = 0V 160 RUNx = ITHx = SVIN 20 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 1V/DIV No Load Supply Current vs Temperature SUPPLY CURRENT (µA) 2.0 VIN = 3.3V, RT /SYNC = SVIN, unless otherwise noted. Sinking Current VOUT 20mV/DIV SRLIM = SGND OR SVIN SW 2V/DIV 40.2k OPEN 100k 1V/DIV IL 500mA/DIV OPEN VOUT = 1.2V IOUT = –1A VMODE = 1.5V 2ns/DIV 3615 G28 3615 G30 3615 G29 2ns/DIV Tracking Up/Down in Forced Continuous Mode, SRLIM Pin Tied to 0V Tracking Up/Down in Forced Continuous Mode, SRLIM Pin Tied to SVIN VOUT1 1V/DIV VOUT1 500mV/DIV VTRACK/SS 500mV/DIV VTRACK/SS 200mV/DIV PGOOD 2V/DIV PGOOD 2V/DIV 2ms/DIV VOUT = 0V TO 1.8V IOUT = 3A VTRACK/SS = 0V TO 0.7V VMODE = 1.5V VSRLIM = 0V 1µs/DIV 3615 G31 2ms/DIV VOUT = 0V TO 1.2V IOUT = 3A VTRACK/SS = 0V TO 0.4V VMODE = 1.5V VSRLIM = 3.3V 3615 G32 3615f LTC3615 Pin Functions (FE/UF) PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied to SGND, the phase between SW1 and SW2 will be 0°. Tying PHASE to SVIN will select 180° of phase shift. With the PHASE pin tied to half of the SVIN voltage, 90° of phase shift will be selected. VFB2 (Pin 2/Pin 5): Voltage Feedback Input Pin for Channel 2. See VFB1. ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of Channel 2. See ITH1. TRACK/SS2 (Pin 4 /Pin 7): Internal, External Soft-Start, External Reference Input for Channel 2. See TRACK/SS1. SGND (Pin 5/Pin 8): Signal Ground. All small-signal and compensation components should connect to this ground pin which, in turn, should be connected to PGND at one point. PVIN2 (Pins 6, 7/Pins 9, 10) Channel 2 Power Supply Input. See PVIN1. SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node. See SW1. RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See RUN1. RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forcing RUN1 above the input threshold enables the output SW1 of channel 1. Forcing both RUNx pins to ground shuts down the LTC3615. In shutdown, all functions are disabled and the LTC3615 draws <1µA of supply current. RT /SYNC (Pin 12/Pin 15): Oscillator Frequency. This pin provides three modes of setting the switching frequency. 1. Connecting a resistor from RT /SYNC to ground will set the switching frequency based on the resistor value. 2. Driving RT /SYNC with an external clock signal will synchronize the switcher to the applied frequency. The slope compensation is automatically adapted to the external clock frequency. 3. Tying this pin to SVIN enables the internal 2.25MHz oscillator frequency. PGOOD2 (Pin 13/Pin 16): Power Good Output for Channel 2. See PGOOD1. SRLIM (Pin 14 /Pin 17): Slew Rate Limit. Slew rate on the switch pins is programmed with the SRLIM pin: 1. Tying this pin to SGND selects maximum slew rate. 2. Minimum slew rate is selected when the pin is open. 3. Connecting a resistor from SRLIM to SGND allows the slew rate to be continuously adjusted. 4. If SRLIM is tied to SVIN the slew rate is set to maximum and DDR mode is enabled (see the Applications Information section). PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for Channel 1. The open-drain output will be pulled down to ground when the FB1 voltage of the channel is not within the power good voltage window. The PGOOD1 will also be pulled down if the channel is not enabled with the RUN1 pin or an undervoltage at SVIN is detected. In DDR mode (SRLIM = SVIN), the power good window moves in relation to the actual TRACK/SS pin voltage. SW1 (Pins 17, 16/Pins 19, 20): Channel 1 Switching Node. Connection to the external inductor. This pin connects to the drains of the internal synchronous power MOSFET switches. PVIN1 (Pins 18, 19/Pins 21, 22): Channel 1 Power Supply Inputs. These pins connect to the source of the internal power P-channel MOSFET of channel 1. PVIN1 and PVIN2 are independent of each other. They may connect to equal or lower supplies than SVIN. SVIN (Pin 20/Pin 23) Signal Input Supply. This pin powers the internal control circuitry and is monitored by the undervoltage lockout comparator. 3615f LTC3615 Pin Functions (FE/UF) TRACK/SS1 (Pin 21/Pin 24): Internal, External SoftStart, External Reference Input for Channel 1. The type of start-up behavior for channel 1 is programmable with the TRACK/SS1 pin: MODE (Pin 24/Pin 3): Mode Selection. 1. Internal soft-start with a fixed timing can be programmed by tying TRACK/SS1 to SVIN. 2. If this pin is held at slightly higher than half of SVIN, forced continuous mode will be selected. 2. External soft-start can be programmed with the timing set by a capacitor to ground and a resistor to SVIN. 3. Tracking the start-up behavior of another supply is programmable (see the Applications Information section). 4. The pin can be used as external reference input. ITH1 (Pin 22/Pin 1): Error Amplifier Compensation. Connection for external compensation from ITH to SGND. The current comparator’s threshold increases with this control voltage. Tying this pin to SVIN enables AVP mode with internal compensation. 1. Tying the MODE pin to SVIN or SGND enables pulseskipping mode or Burst Mode operation (with an internal Burst Mode clamp), respectively. 3. Connecting this pin to an external voltage will select Burst Mode operation with the burst clamp set to the pin voltage. PGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Power Ground. The exposed pad connects to the sources of the power N-channel MOSFETs. The PGND pin is common for both channels. The exposed pad must be soldered to the PCB. For electrical connection and rated thermal performance, refer to the Operation and Applications Information sections for more information. VFB1 (Pin 23/Pin 2): Voltage Feedback Input Pin for Channel 1. Receives the feedback voltage for channel 1 from the external resistive divider across the output. 3615f 10 LTC3615 FUNCTIONAL Block Diagram ITH1 PGOOD1 PGOOD WINDOWCOMPARATOR DELAY + ERROR AMPLIFIER + IDEAL DIODE TRACK/SS1 PMOS CURRENT SENSE – PMOS CURRENT COMPARATOR CONTROLLER LOGIC SOFT-START RUN1 PVIN1 GATE DRIVER SW1 CLK1 OR RUN2 RT /SYNC PHASE PLL OSCILLATOR AND PHASE SELECTOR SVIN SGND + SLOPE COMPENSATION – + MODE BURST COMPARATOR MODE – VREF INTERNAL/ EXTERNAL COMPENSATION ITH-VOLTAGE LIMIT – FB1 CHANNEL 1 + – CLK2 UNDERVOLTAGE LOCKOUT SHUTDOWN NMOS CURRENT SENSE 0A REVERSE CURRENT COMPARATOR SRLIM PGND DUPLICATE FOR CHANNEL 2 PVIN2 PGOOD2 SW2 FB2 TRACK/SS2 ITH2 3615f 11 LTC3615 Operation Main Control Loop MODE SELECTION The LTC3615 is a dual monolithic step-down DC/DC converter featuring current-mode, constant-frequency operation. Both channels are identical and share common clock and reference circuits to improve channel-to-channel matching. The MODE pin is used to select one of four different operating modes for both channels together (see Figures 1 and 3): During normal operation, the internal top power switch (P-channel MOSFET) of each channel is turned on at the beginning of its clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at which the current comparator shuts off is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signals derived from an external resistor divider on the VFBx pin with an internal 0.6V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. Typical voltage range for the ITH pin is from 0.45V to 1.05V with 0.45V corresponding to zero current. When the top power MOSFET shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the current limit is reached or the next clock cycle begins. The bottom current limit is typically set at –4A for forced continuous mode and 0A for Burst Mode operation and pulse-skipping mode. The operating frequency defaults to 2.25MHz when RT/SYNC is connected to SVIN, or can be set by an external resistor connected between the RT/SYNC pin and ground, or by a clock signal applied to the RT/SYNC pin. The switching frequency can be set from 400kHz to 4MHz (see the Applications Information section). Overvoltage and undervoltage comparators pull the PGOOD output low if the output voltage varies more than ±7.5% from the set point. SVIN SVIN – 0.3V SVIN • 0.58 1.1V 0.8V 0.5V 0.3V SGND PS PULSE-SKIPPING MODE ENABLE FC FORCED CONTINUOUS MODE ENABLE BM EXT Burst Mode ENABLE—EXTERNAL CLAMP, CONTROLLED BY VOLTAGE APPLIED AT MODE PIN BM Burst Mode ENABLE—INTERNAL CLAMP 3615 F01 Figure 1. Mode Selection Voltage Burst Mode Operation—Internal Clamp Connecting the MODE pin to the SGND pin enables Burst Mode operation with its peak current set internally. In Burst Mode operation the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During the intervals when the MOSFETs are not switching, the LTC3615 enters a sleep state where many of the internal circuits are disabled to save power. During Burst Mode operation, the ITH voltage is monitored by the burst comparator to determine when the sleep state is entered or exited again. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below the internal threshold, the LTC3615 enters the sleep state. In the sleep state, the power MOSFETs are held off and the load current is solely supplied by the output capacitor. When the output voltage drops, the top power MOSFET is switched back on and the internal circuits are reenabled. This process repeats at a rate that is dependent on the load current. 3615f 12 LTC3615 Operation Burst Mode Operation—External Clamp Forced Continuous Mode Operation Connecting the MODE pin to a voltage in the range of 0.5V to 0.8V enables Burst Mode operation with external clamp. During this mode of operation, the minimum voltage on the ITH pin is externally set by the voltage on the MODE pin. It is recommended to use Burst Mode operation with the internal clamp for ambient temperatures above 85°C. In forced continuous mode the inductor current is constantly cycled which creates a minimum output voltage ripple at all output current levels. Pulse-Skipping Mode Operation The forced continuous mode must be used if the output is required to sink current. Connecting the MODE pin, to a voltage in the range of 1.1V to SVIN • 0.58 will select the forced continuous mode operation. Pulse-skipping mode is similar to Burst Mode operation, but the LTC3615 does not disable power to the internal circuitry during sleep mode. This improves output voltage ripple but uses more quiescent current compromising light load efficiency. Dropout Operation As the input supply voltage approaches the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Connecting the MODE pin to SVIN enables pulse-skipping mode. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below 450mV, corresponding to 0A. At this point switching cycles will be skipped to keep the output voltage in regulation. VIN LTC3615 SVIN LTC3615 SVIN SW1 VIN VOUT1 RM1 MODE MODE 0V RM2 SGND 2a. Burst Mode Operation Internally Controlled VIN FB1 SGND 0V 2b. Burst Mode Operation Externally Controlled LTC3615 SVIN LTC3615 SVIN VIN RM1 MODE MODE RM2 0V 0V SGND SGND 3615 F02 2c. Pulse-Skipping Mode 2d. Forced Continuous Mode Figure 2. Modes of Operation 3615f 13 LTC3615 Operation Low Supply Operation The LTC3615 is designed to operate down to an input supply voltage of 2.25V. An important consideration at low input supply voltages is that the RDS(ON) of the P-channel and N-channel power switches increases by 50% compared to 5V. The user should calculate the power dissipation when the LTC3615 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in current mode constant-frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. The LTC3615 implements slope compensation by adding a compensation ramp to the inductor current signal. Short-Circuit Protection The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. If the output current increases, the error amplifier raises the ITH pin voltage until the average inductor current matches the new load current. In normal operation, the LTC3615 clamps the maximum ITH pin voltage at approximately 1.05V which corresponds to about 5A peak inductor current. When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. The LTC3615 uses two techniques to prevent current runaway from occurring: 1. If the output voltage drops below 50% of its nominal value, the clamp voltage at pin ITH is lowered, causing the maximum peak inductor current to lower gradually with the output voltage. When the output voltage reaches 0V, the clamp voltage at the ITH pin drops to 40% of the clamp voltage during normal operation. The short-circuit peak inductor current is determined by the minimum on-time of the LTC3615, the input voltage and the inductor value. This foldback behavior helps in limiting the peak inductor current when the output is shorted to ground. It is disabled during internal or external soft-start and tracking up/down operation (see the Applications Information section). 2. If the inductor current of the bottom MOSFET increases beyond 6A typical, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current reduces. 3615f 14 LTC3615 Applications Information Operating Frequency Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3615 is determined by an external resistor that is connected between pin RT /SYNC and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: is typically 60ns, therefore, the minimum duty cycle is equal to 60ns • 100% • fOSC (Hz) Tying the RT /SYNC pin to SVIN sets the default internal operating frequency to 2.25MHz ±20%. Frequency Synchronization The LTC3615’s internal oscillator can be synchronized to an external frequency by applying a square wave clock signal to the RT /SYNC pin. During synchronization, the top MOSFET turn-on of channel 1 is locked to the rising edge of the external frequency source. The synchronization frequency range is 400kHz to 4MHz. The internal slope compensation is automatically adapted to the external clock frequency. 4 • 1011ΩHz RT = fOSC In the signal path from the RT/SYNC clock input to the SW output, the LTC3615 is processing the external clock frequency through an internal PLL. Although frequencies as high as 4MHz are possible, the minimum on-time of the LTC3615 imposes a minimum limit on the operating duty cycle. The minimum on-time After detecting an external clock on the first rising edge of RT/SYNC the PLL starts up with the internal default of 2.25MHz. The internal PLL then requires a certain number VIN 3.3V 47µF 47µF 1µF SVIN (2s) PVIN1 (2s) PVIN2 (2s) SW1 0.47µH RUN1 RSS 4.7M CSS 10nF RC 15k CC 1000pF 10pF RT, 200k RSRLIM 40.2k FB1 TRACK/SS1 PGOOD1 ITH1 LTC3615 R2 29.4k MODE RT /SYNC (2s) SW2 R3 178k 0.47µH R5 665k SRLIM PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND R1 422k VOUT1 1.8V/3A 47µF VOUT2 2.5V/3A 47µF FB2 R4 210k PGND 3615 F03 Figure 3. Soft-Start and Compensation for Channel 1 Externally Programmed, Soft-Start and Compensation for Channel 2 Internally Programmed 3615f 15 LTC3615 Applications Information VIN LTC3615 SVIN RT/SYNC VIN fSW 2.25MHz 0.4V ROSC LTC3615 SVIN RT/SYNC SGND VIN fSW t1/ROSC 1.2V 0.3V LTC3615 SVIN RT/SYNC SGND VIN fSW 1/TP TP 15pF 1.2V 0.3V TP RT LTC3615 SVIN RT/SYNC SGND fSW 1/TP 3615 F04 Figure 4. Setting the Switching Frequency of periods to settle until the frequency at SW matches the frequency and phase of RT/SYNC. When the external clock signal is removed, the LTC3615 needs approximately 5µs to detect the absence of the external clock. During this time, the PLL will continue to provide clock cycles before it is switched back to the default frequency or selected frequency (set via the external RT resistor). A safe way of driving the RT/SYNC input is with an AC coupling to the clock generator via a 15pF capacitor. The AC coupling avoids complications if the external clock generator cannot provide a continuous clock signal at the time of start-up, operation and shut down of the LTC3615. In general, any abrupt clock frequency change of the regulator will have an effect on the SW pin timing and may cause equally sudden output voltage changes. This must be taken into account in particular if the external clock frequency is significantly different from the internal default of 2.25MHz. Phase Selection Channel 2 will operate in-phase, 180° out-of-phase (anti-phase) or shifted by 90° from channel 1 depending on the state of the PHASE pin—low, midrail and high, respectively. Antiphase generally reduces input voltage and current ripple. Crosstalk between switch nodes SW1, SW2 and components or sensitive lines connected to FBx, ITHx, RT/SYNC or SRLIM can cause unstable switching waveforms and unexpectedly large input and output voltage ripple. The situation improves if rising and falling edges of the switch nodes are timed carefully not to coincide. Depending on the duty cycle of the two channels, choose the phase difference between the channels to keep edges as far away from each other as possible. 16 For a duty cycle of less than 40% for one channel and more than 60% for the other channel, choose a phase shift of 0 or 180° (PHASE = SGND or SVIN). If both channels have a duty cycle of around 50%, select a phase difference of 90° (PHASE = one-half SVIN). Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ∆IL increases with higher VIN and decreases with higher inductance. V • 1 – OUT VIN(MAX ) Having a lower ripple current reduces the core losses in the inductor, the ESR losses in the output capacitors and the output voltage ripple. A reasonable starting point for selecting the ripple current is ∆IL = 0.3(IOUT(MAX)). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: VOUT VOUT L= • 1– VIN(MAX ) fSW • ∆IL(MAX ) V ∆IL = OUT fSW • L The inductor value will also have an effect on Burst Mode operation. The transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower DC load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. 3615f LTC3615 Applications Information Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire, and therefore, copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow a ferrite core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. Table 1 shows some typical surface mount inductors that work well in LTC3615 applications. Input Capacitor CIN Selection In continuous mode, the source current of the top P-channel MOSFET is a square wave of duty cycle VOUT /VIN. To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used for CIN. The maximum RMS capacitor current is given by: IRMS = IOUT(MAX ) • This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Table 1. Representative Surface Mount Inductors INDUCTANCE DCR MAX (µH) (mΩ) CURRENT (A) Vishay IHLP-2020BZ-01 0.33 7.6 25 DIMENSIONS (mm) HEIGHT (mm) 5.18 × 5.49 2 0.47 8.9 21 5.18 × 5.49 2 0.68 11.2 15 5.18 × 5.49 2 1 18.9 16 5.18 × 5.49 2 Toko DE3518C Series 0.22 8 24 4.3 × 4.7 2 6.7 × 7.25 3 Sumida CDMC6D28 Series 0.3 3.2 15.4 0.47 4.2 13.6 6.7 × 7.25 3 0.68 5.4 11.3 6.7 × 7.25 3 1 8.8 8.8 6.7 × 7.25 3 NEC/Tokin MPLC0730L Series 0.47 4.5 16.6 6.9 × 7.7 3.0 0.75 7.5 12.2 6.9 × 7.7 3.0 1.0 9.0 10.6 6.9 × 7.7 3.0 10 8.9 × 6.1 5 7.7 8.9 × 6.1 5 Coilcraft DO1813H Series 0.33 4 0.56 10 Coilcraft SLC7530 Series 0.27 0.1 14 7.5 × 6.7 3 0.35 0.1 11 7.5 × 6.7 3 0.4 0.1 8 7.5 × 6.7 3 V VOUT • IN – 1 VIN VOUT 3615f 17 LTC3615 Applications Information Output Capacitor COUT Selection The selection of COUT is typically driven by the required ESR to minimize voltage ripple and load step transients (low-ESR ceramic capacitors are discussed in the next section). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple ∆VOUT is determined by: 1 ∆VOUT ≤ ∆IL • ESR + 8 • fSW • COUT where fSW = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. Tantalum capacitors have the highest capacitance density, but can have higher ESR and must be surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can often be used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic Input and Output Capacitors Ceramic capacitors have the lowest ESR and can be cost effective, but also have the lowest capacitance density, high voltage and temperature coefficients, and exhibit audible piezoelectric effects. In addition, the high-Q of ceramic capacitors along with trace inductance can lead to significant ringing. Capacitors are tempting for switching regulator use because of their very low ESR. Great care must be taken when using only ceramic input and output capacitors. Ceramic caps are prone to temperature effects which require the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. When a ceramic capacitor is used at the input, and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, three to four cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about two to three times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: 2.5 • ∆IOUT COUT ≈ fSW • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. 3615f 18 LTC3615 Applications Information Output Voltage Programming Pulse-Skipping Mode The output voltages are set by external resistive dividers. For example, VOUT2 can be set according to the following equation: Pulse-skipping mode, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting the MODE pin to SVIN. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator. The lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulseskipping allows only a few switching cycles to skip while maintaining the output voltage in regulation. R5 VOUT2 = 0.6 V • 1 + R4 The resistive divider allows pin VFB to sense a fraction of the output voltage as shown in Figure 3. Burst Clamp Programming If the voltage on the MODE pin is less than 0.8V, Burst Mode operation is enabled. If the voltage on the MODE pin is less than 0.3V, the internal default burst clamp level is selected. The minimum voltage on the ITH pin is typically 525mV (internal clamp). If the voltage is between 0.45V and 0.8V, the voltage on the MODE pin (VBURST) is equal to the minimum voltage on the ITH pin (external clamp) and determines the burst clamp level IBURST (typically from 1A to 3.5A). When the ITH voltage falls below the internal (or external) clamp voltage, the sleep state is entered. As the output load current drops, the peak inductor current decreases to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops, sleep mode is enabled in which both power switches are shut off along with most of the circuitry to minimize power consumption. All circuitry is turned back on and the power switches resume operation when the output voltage drops out of regulation. The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep period between pulses and the output voltage ripple increase. It is recommend to use Burst Mode operation with internal clamp for temperatures above 85°C ambient. Internal and External Compensation The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC load current. When a load step occurs, like the one shown in Figure 5, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin allows the transient response to be optimized over a wide range of output capacitance. The ITH1 external components (15k and 100pF) shown in Figure 3 will provide an adequate compensation as well as a starting point for most applications. The values can be modified slightly to optimize transient response once the final PCB layout is complete and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system. The external compensation, forced continuous operation circuit in the Typical 3615f 19 LTC3615 Applications Information Applications section uses faster compensation to improve load step response. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. More output capacitance may be required depending on the duty cycle and load step requirements. If the ITH pin is tied to SVIN, the active voltage positioning (AVP) mode and the internal compensation is selected. In AVP mode, the load regulation performance is intentionally reduced, setting the output voltage at a point that is dependent on the load current. When the load current suddenly increases, the output voltage starts from a level slightly higher than nominal so the output voltage can droop more and stay within the specified voltage range. When the load current suddenly decreases, the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. This behavior is demonstrated in Figure 6. The benefit is a lower peak-to-peak output voltage deviation for a given load step without having to increase the output filter capacitance. Alternatively, the output voltage filter capacitance can be reduced while maintaining the same peak-to-peak transient response. For this operation mode, the loop gain is reduced and no external compensation is required. Programmable Switch Pin Slew Rate As switching frequencies rise, it is desirable to minimize the transition time required when switching to minimize power losses and blanking time for the switch to settle. However, fast slewing of the switch node results in relatively high external radiated EMI and high on-chip supply transients, which can cause problems for some applications. VOUT 100mV/DIV VOUT 200mV/DIV 3A IL 1A/DIV IL 1A/DIV 100mA 3615 F05 50µs/DIV VOUT = 1.8V ILOAD = 100mA TO 3A VMODE = 1.5V COMPENSATION AND OUTPUT CAPACITOR VALUES OF FIGURE 3 Figure 5. Load Step Transient in FCM with External Compensation 50µs/DIV VOUT = 1.8V ILOAD = 100mA TO 3A VMODE = 1.5V VIN = VITH = 3.3V OUTPUT CAPACITOR VALUE FIGURE 3 3615 F06 Figure 6. Load Step Transient in FCM in AVP Mode 3615f 20 LTC3615 Applications Information The LTC3615 allows the user to control the slew rate of the switching node SW by using the SRLIM pin. Tying this pin to ground selects the fastest slew rate. The slowest slew rate is selected when the pin is open. Connecting a resistor (between 10k to 100k) from SRLIM pin to ground adjusts the slew rate between the maximum and minimum values. The reduced dV/dt of the switch node results in a significant reduction of the supply and ground ringing, as well as lower radiated EMI. See Figure 7a and the Typical Performance Characteristics section for examples. pin to SGND and discharging the external capacitor CSS (see Figure 3). Reducing the slew rate causes a trade-off between efficiency and low EMI (see Figure 7b). The RUNx pins provide a means to shut down each channel of the LTC3615. Pulling both pins below 0.3V places the LTC3615 in a low quiescent current shutdown state (IQ < 1µA). 2. If a longer soft-start period is desired, it can be set externally with a resistor and capacitor on the TRACK/SSx pins as shown in Figure 3. The voltage applied at the TRACK/SSx pins sets the value of the internal reference at VFB until TRACK/SSx is pulled above 0.6V. The external soft-start duration can be calculated by using the following equation: SVIN tSS = RSS • CSS • In SVIN – 0.6 V 3. The TRACK/SSx pin can be used to track the output voltage of another supply. After enabling the LTC3615 by bringing either one or both RUNx pins above the threshold, the enabled channels enter a soft-start-up state. The type of soft-start behavior is set by the TRACK/SSx pins. The soft-start cycle begins with an initial discharge pulse pulling down the TRACK/SSx Regardless of either the internal or external soft-start state, the MODE pin is ignored during start-up and the regulator defaults to pulse-skipping mode. In addition, the PGOODx pin is kept low, and the frequency foldback function is disabled. Particular attention should be used with very high switching frequencies. Using the slowest slew rate (SRLIM open) can reduce the minimum duty cycle capability. Soft-Start 1. Tying this pin to SVIN selects the internal soft-start circuit. This circuit ramps the output voltage to the final value within 1ms. 92 91 SRLIM = SGND OR SVIN 90 EFFICIENCY (%) VIN = 3.3V VOUT = 1.8V IOUT = 1A The initial discharge is adequate to discharge capacitors up to 33nF. If a larger capacitor is required, connect the external soft-start resistor RSS to the RUN pin to fully discharge the capacitor. 40.2k 100k 1V/DIV OPEN VOUT = 1.8V IOUT = 1A FCM GND OR SVIN 89 88 40.2k 20k OPEN 87 86 85 84 83 2ns/DIV 3615 F07a (7a) Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor 82 2.25 3.06 3.88 VIN (V) 4.69 5.50 3615 07b (7b) Efficiency vs SRLIM Resistor Programming Figure 7. Slew Rate and the SRLIM Resistor 3615f 21 LTC3615 Applications Information Through the TRACK/SS pin, the output voltage can be set up to either coincidental or ratiometric tracking, as shown in Figures 8 and 9. Output Voltage Tracking Input If SRLIM is low, once VTRACK/SS reaches or exceeds 0.6V the run state is entered, and the MODE selection, power good and current foldback circuits are enabled. To implement the coincidental tracking waveform in Figure 8, connect an extra resistive divider to the output of the master channel and connect its midpoint to the TRACK/SS pin for the slave channel. The ratio of this divider should be selected the same as that of the slave channel’s feedback divider (Figure 10). In the run state, the TRACK/SS pin can be used to track down/up the output voltage of another supply. If the VTRACK/SS again drops below 0.6V, the LTC3615 enters the down-tracking state and the VOUT is referenced to the TRACK/SS voltage. If VTRACK/SS reaches 0.1V value the switching frequency is reduced by 4x to ensure that the minimum duty cycle limit does not prevent the output from following the TRACK/SS pin. The run state will resume if the VTRACK/SS again exceeds 0.6V and the VOUT is referenced to the internal reference. In this tracking mode, the master channel’s output must be set higher than slave channel’s output. To implement the ratiometric start-up in Figure 9, no extra divider is needed; simply connect the TRACK/SS pin to the other channel’s VFB pin (Figure 12). VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 TIME VOUT2 3615 F08 3615 F09 TIME Figure 8. Coincident Start-Up Tracking Figure 9. Ratiometric Start-Up Tracking VOUT1 VOUT1 R3 R1 R1 LTC3615 R2 FB1 R4 VOUT1 LTC3615 R1 FB1 R2 R3 TRACK/SS2 VOUT2 R2 TRACK/SS2 VOUT2 R5 TRACK/SS2 VOUT2 R4 FB2 R3 FB2 R6 FB2 R5 3615 F10 Figure 10. Set for Coincidentally Tracking (R3 = R5, R4 = R6) LTC3615 FB1 R4 3615 F11 Figure 11. Alternative Set-Up for Coincident Start-Up Tracking (R1 = R3, R2 = R3 = R5) 3615 F12 Figure 12. Set-Up for Ratiometric Tracking 3615f 22 LTC3615 Applications Information External Reference Input (DDR Mode) If SRLIM is tied to SVIN, the TRACK/SS pin can be used as an external reference input between 0.3V and 0.5V, if desired (see Figure 13). In DDR mode, the maximum slew rate is selected. If VTRACK/SS is within 0.3V and 0.5V, the PGOOD function is enabled. If VTRACK/SS is less than 0.3V, the output current foldback is disabled and the PGOOD pin is always pulled down. VFB PIN 0.6V VOLTAGE 0V 0.6V TRACK/SS PIN VOLTAGE 0.1V 0V RUN PIN VOLTAGE SVIN PIN VOLTAGE VIN 0V VIN 0V TIME SHUTDOWN SOFT-START STATE STATE tSS > 1ms RUN STATE REDUCED SWITCHING FREQUENCY DOWNTRACKING STATE RUN STATE 3615 F13 UPTRACKING STATE Figure 13. Tracking if VSRLIM Is Low 0.45V VFB PIN 0.3V VOLTAGE 0V EXTERNAL VOLTAGE REFERENCE 0.45V 0.45V TRACK/SS 0.3V PIN VOLTAGE 0.1V 0V RUN PIN VOLTAGE SVIN PIN VOLTAGE VIN 0V VIN 0V TIME SHUTDOWN SOFT-START STATE STATE tSS > 1ms RUN STATE REDUCED SWITCHING FREQUENCY DOWNTRACKING STATE RUN STATE 3615 F14 UPTRACKING STATE Figure 14. Tracking if VSRLIM Is Tied to SVIN 3615f 23 LTC3615 Applications Information DDR Application The LTC3615 can be used in DDR memory power supply applications by tying the SRLIM pin to SVIN. In DDR mode, the maximum slew rate is selected. The output can both source and sink current. Current sinking is typically limited to 1.5A, for 1MHz frequency and 1µH inductance, but can be lower at higher frequencies and low output voltages. If higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. See the Typical Performance Characteristics curves for more information. In addition, in DDR mode, lower external reference voltages and tracking output voltages between channels are possible. See the Output Voltage Tracking Input section. Single, Low Ripple 6A Output Application The LT3615 can generate a single, low ripple 6A output if the outputs of the two switching regulators are tied together and share a single output capacitor (see Figure 15 on back of data sheet). In order to evenly share the current between the two regulators, it is needed to connect pins FB1 to FB2, ITH1 to ITH2 and to select forced continuous mode at the MODE pin. To achieve lowest ripple, 90°, or better, 180°, antiphase is selected by connecting the PHASE pin to midrail or SVIN. There are several advantages to this 2-phase buck regulator. Ripple currents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive capacitors. Although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. This may be important when there are tight height restrictions on the circuit. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of little consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN due to gate charge, and it is typically larger than the DC bias current. Both the DC bias and gate charge losses are proportional to VIN , thus, their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC), as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. To obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% of the total loss. 3615f 24 LTC3615 Applications Information Thermal Considerations In most applications, the LTC3615 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3615 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160°C, all four power switches will be turned off and the SW node will become high impedance. To prevent the LTC3615 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. To determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator, and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TRISE where TA is the ambient temperature. As an example, consider this case: the LTC3615 is in dropout at an input voltage of 3.3V with a load current for each channel of 2A at an ambient temperature of 70°C. Assuming a 20°C rise in junction temperature, to 90°C, results in an RDS(ON) of 0.086mΩ (see the graph in the Typical Performance Characteristics section). Therefore, the power dissipated by the part is: PD = (I12 + I22) • RDS(ON) = 0.69W For the QFN package, the θJA is 37°C/W. Therefore, the junction temperature of the regulator operating at 70°C ambient temperature is approximately: TJ = 0.69W • 37°C/W + 70°C = 95°C Note that for very low input voltage, the junction temperature will be higher due to increased switch resistance RDS(ON). It is not recommended to use full load current at high ambient temperature and low input voltage. To maximize the thermal performance of the LTC3615, the Exposed Pad should be soldered to a ground plane. See the PC Board Layout Checklist. Design Example As a design example, consider using the LTC3615 in an application with the following specifications: VIN = 3.3V to 5.5V VOUT1 = 2.5V VOUT2 = 1.2V IOUT1(MAX) = 1A IOUT2(MAX) = 3A IOUT(MIN) = 100mA f = 2.25MHz Because efficiency is important at both high and low load current, Burst Mode operation will be selected by connecting the MODE pin to SGND. First, calculate the timing resistor: R RT / SYNC = 4E11 Ω • Hz = 178 k 2.25MHz Next, calculate the inductor values for about 1A ripple current at maximum VIN : 2.5V L1 = 2.25MHz • 1A 1.2V L2 = 2.25MHz • 1A 2.5V • 1– = 0.66µH 5.5V 1.2V • 1– = 0.42µH 5.5V Using a standard value of 0.56µH and 0.47µH inductors results in maximum ripple currents of: 2.5V ∆I L1 = 2.25MHz • 0.56µH 2.5V • 1– = 1.08 A 5.5V 1.2V ∆ I L2 = 2.25MHz • 0.47µH 1.2V • 1– = 0.89 A 5.5V 3615f 25 LTC3615 Applications Information COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, 47µF ceramic capacitors will be used with X5R or X7R dielectric. CIN should be sized for a maximum current rating of: IOUT1 I OUT 2 + = 2A RMS 2 2 Decoupling the PVIN with two 47µF capacitors is adequate for most applications. IRMS(MAX ) = Finally, it is possible to define the soft-start up time choosing the proper value for the capacitor and the resistor connected to TRACK/SS pin. If one sets minimum TSS = 5ms and a resistor of 4.7M, the following equation can be solved with the maximum SVIN = 5.5V: CSS = 5ms = 9.2nF 5.5V 4.7M • In 5.5V – 0.6 V The standard value of 10nF and 4.7M guarantees the minimum soft-start time of 5ms. In Figure 3, channel 1 shows the schematic for this design example. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3615: 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the SGND pin at one point which is then connected to the PGND node at the exposed pad close to the LTC3615 2. Connect the (+) terminal of the input capacitors, CIN, as close as possible to the PVINx pins, and the (–) terminal as close as possible to the exposed pad PGND. This capacitor provides the AC current into the internal power MOSFETs. 3. Keep the switching nodes, SWx, away from all sensitive small signal nodes FBx, ITHx, RTSYNC, SRLIM. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to PGND (exposed pad) for best performance. 5. Connect the VFBx pins directly to the feedback resistors. The resistor divider must be connected between VOUTx and SGND. 3615f 26 LTC3615 Typical Applications External Compensation, Forced Continuous Operation, In-Phase Switching, Slew Rate Limit, Common PGOOD Output VIN 3.3V 47µF 47µF 1µF SVIN RUN (2s) PVIN1 (2s) PVIN2 (2s) SW1 RUN1 0.47µH R1 412k TRACK/SS1 RC1 43k CC1 220pF R6 226k 10pF RT 178k R5 40.2k R7 174k 100k PGOOD1 ITH1 LTC3615 RC2 43k 10pF 47µF R2 205k RT /SYNC SRLIM (2s) SW2 MODE FB2 0.47µH R3 665k 47µF VOUT2 2.5V/3A R4 210k PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND PGOOD FB1 MODE VOUT1 1.8V/3A PGND 3615 TA02 CC2 220pF VOUT1 Waveform VOUT2 Waveform VOUT1 100mV/DIV VOUT2 100mV/DIV IOUT1 1A/DIV IOUT2 1A/DIV 20µs/DIV 3615 TA02b 20µs/DIV 3615 TA02c 3615f 27 LTC3615 Typical Applications DDR Memory Termination VIN 3.3V CIN1 47µF CIN2 47µF CIN3 1µF SVIN (2s) PVIN1 (2s) PVIN2 RUN1 TRACK/SS1 (2s) SW1 L1 0.47µH PGOOD1 R10 15k C2 1000pF ITH1 C1 10pF RT /SYNC SRLIM LTC3615 R3 150k R2 60.4k R4 49.9k L2 0.47µH R9 226k (2s) SW2 PHASE R5 49.9k RUN2 FB2 TRACK/SS2 COUT1 47µF VTT 0.9V 3A/–1.5A COUT2 47µF R6 49.9k PGOOD2 R7 15k R1 121k FB1 MODE R8 174k VDDQ 1.8V/3A ITH2 SGND PGND C3 10pF 3615 TA03a C4 1000pF Ratiometric Start-Up VDD 500mV/ DIV VTT 500µs/DIV 3615 TA03b 3615f 28 LTC3615 Typical Applications Master and Slave for Coincident Tracking Outputs Using a 2MHz External Clock RF1 24Ω CF1 1µF VIN 3.3V C1 47µF C2 47µF 4.7M SVIN (2s) PVIN1 (2s) PVIN2 (2s) SW1 RUN1 L1 0.47µH R1 715k TRACK/SS1 CSYNC 15pF PGOOD1 2MHz CLOCK RT 200k R5 100k RC1 15k 10nF R2 357k PGOOD1 RT /SYNC ITH1 CC2 10pF R9 226k (2s) SW2 TRACK/SS2 R7 100k ITH2 CC4 10pF R5 294k FB2 CO12 22µF R4 453k C7 22pF CO21 47µF CO22 22µF VOUT2 1.2V/3A R6 294k PGOOD2 RC2 15k CO11 47µF L2 0.47µH PHASE RUN2 PGOOD2 R3 453k SRLIM MODE R8 174k VOUT1 1.8V/3A FB1 LTC3615 CC1 1000pF C3 22pF SGND PGND CC3 470pF 3615 TA04a Coincident Start-Up Coincident Tracking Up/Down VOUT1 VOUT2 500mV/ DIV 2ms/DIV 3615 TA04b VOUT1 500mV/ DIV VOUT2 200ms/DIV 3615 TA04c 3615f 29 LTC3615 Package Description FE Package 24-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation AA 7.70 – 7.90* (.303 – .311) 3.25 (.128) 3.25 (.128) 24 23 22 21 20 19 18 17 16 15 14 13 6.60 p0.10 2.74 (.108) 4.50 p0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 p0.05 1.05 p0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0o – 8o 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE24 (AA) TSSOP 0208 REV Ø 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3615f 30 LTC3615 Package Description UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ± 0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3615f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC3615 Typical Application VIN 3.3V 47µF 1µF SVIN (2s) (2s) PVIN1 PVIN2 RUN1 (2s) SW1 TRACK/SS1 VSW1 L1 0.47µH R1 102k PGOOD1 ITH1 LTC3615 RT /SYNC 20pF RC 7.5k CC 2000pF R9 174k R8 226k FB1 L2 0.47µH SRLIM (2s) SW2 MODE FB2 VOUT 1.2V/6A 47µF R2 102k 2V/DIV, 1A/DIV VSW2 IL1 IL2 IL1 + IL2 MODE = FCM 200ns/DIV 3615 F16 Figure 16. Reduced Ripple Current (Waveform IL1 + IL2) and Ripple Voltage (Not Shown) Through 180° Phase Shift Between SW1 and SW2 PHASE RUN2 TRACK/SS2 PGOOD2 ITH2 SGND PGND 3615 F15 100 VOUT = 1.2V 90 MODE = FCM Figure 15. Single, Low Ripple 6A Output EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.01 VIN = 2.5V VIN = 3.3V VIN = 5V 0.1 1 OUTPUT CURRENT (A) 10 3615 F17 Figure 17. Efficiency vs Load Current for VOUT = 1.2V and IOUT Up to 6A Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3633 15V, Dual 3A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.60V to 15V, VOUT(MIN) = 0.6V, IQ = 500µA, ISD < 13µA, 4mm × 5mm QFN-28 and TSSOP-28E Packages LTC3546 5.5V, Dual 3A/1A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 160µA, ISD < 1µA, 4mm × 5mm QFN-28 Package LTC3417A-2 5.5V, Dual 1.5A/1A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 125µA, ISD < 1µA, TSSOP-16E and 3mm × 5mm DFN-16 Packages LTC3612 5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 3mm × 4mm QFN-20 and TSSOP-20E Packages LTC3614 5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 3mm × 4mm QFN-20 and TSSOP-20E Packages LTC3616 5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 3mm × 5mm QFN-24 Package 3615f 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0410 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010