LINER LTC4352CMS

LTC4352
Low Voltage Ideal Diode
Controller with Monitoring
FEATURES
DESCRIPTION
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The LTC®4352 creates a near-ideal diode using an external
N-channel MOSFET. It replaces a high power Schottky
diode and the associated heat sink, saving power and
board area. The ideal diode function permits low loss
power ORing and supply holdup applications.
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Low Loss Replacement for Power Diode
Controls N-Channel MOSFET
0V to 18V Supply ORing or Holdup
0.5μs Turn-On and Turn-Off Time
Undervoltage and Overvoltage Protection
Open MOSFET Detect
Status and Fault Outputs
Hot Swappable
Reverse Current Enable Input
12-Pin MSOP and DFN (3mm × 3mm) Packages
The controller operates with supplies from 2.9V to 18V.
For lower voltages, an external supply is needed at the
VCC pin. Power passage is disabled during undervoltage
or overvoltage conditions. The controller also features an
open MOSFET detect circuit that flags excessive voltage
drop across the pass transistor in the on state. A REV pin
enables reverse current, overriding the diode behavior
when desired.
APPLICATIONS
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The LTC4352 regulates the forward voltage drop across
the MOSFET to ensure smooth current transfer in diode-OR
applications. A fast turn-on reduces the load voltage droop
during supply switch-over. If the input supply fails or is
shorted, a fast turn-off minimizes reverse currents.
Redundant Power Supplies
Supply Holdup
Telecom Infrastructure
Computer Systems and Servers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2.9V to 18V Ideal Diode
Power Dissipation vs Load Current
4.0
Si7336ADP
CPO SOURCE VIN
UV
OUT
FAULT
GND
4352 TA01
*OPTIONAL
MOSFET ON
STATUS
LTC4352
OV
REV
GATE
STATUS
VCC
FAULT
POWER DISSIPATION (W)
0.1μF*
0.1μF
3.5
TO LOAD
2.9V TO 18V
3.0
DIODE (SBG1025L)
2.5
2.0
POWER
SAVED
1.5
1.0
0.5
0
MOSFET (Si7336ADP)
0
2
4
6
LOAD CURRENT (A)
8
10
4352 TA01b
4352f
1
LTC4352
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
VIN, SOURCE Voltages ............................... –0.3V to 24V
VCC Voltage .................................................. –0.3V to 7V
OUT Voltage .................................................. –2V to 24V
CPO, GATE Voltages (Note 3) ..................... –0.3V to 30V
CPO D.C. Current ...................................................10mA
UV, OV, REV Voltages.................................. –0.3V to 24V
FAULT, STATUS Voltages............................ –0.3V to 24V
FAULT, STATUS Currents..........................................5mA
Operating Ambient Temperature Range
LTC4352C ................................................ 0°C to 70°C
LTC4352I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package ...................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VIN
1
12 SOURCE
VCC
2
11 GATE
UV
3
OV
4
9 GND
STATUS
5
8 OUT
FAULT
6
7 REV
13
VIN
VCC
UV
OV
STATUS
FAULT
10 CPO
1
2
3
4
5
6
12
11
10
9
8
7
SOURCE
GATE
CPO
GND
OUT
REV
MS PACKAGE
12-LEAD PLASTIC MSOP
DD PACKAGE
12-PIN (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 164°C/W
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4352CDD#PBF
LTC4352CDD#TRPBF
LDPJ
12-Pin (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC4352IDD#PBF
LTC4352IDD#TRPBF
LDPJ
12-Pin (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4352CMS#PBF
LTC4352CMS#TRPBF
4352
12-Lead Plastic MSOP
0°C to 70°C
LTC4352IMS#PBF
LTC4352IMS#TRPBF
4352
12-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4352f
2
LTC4352
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VSOURCE = VIN, VOUT = VIN, VCC Open, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supplies
VIN
Input Operating Range
With External 2.9V to 4.7V VCC Supply
With External 4.7V to 6V VCC Supply
l
l
l
2.9
0
0
18
VCC
18
V
V
V
6
V
4.1
4.7
V
VCC(EXT)
VCC External Supply Range
l
2.9
VCC(INT)
VCC Internal Regulator Voltage
l
3.5
IIN
VIN Supply Current
VIN = 0V, VCC = 5V, VOUT = 18V
l
l
1.4
–10
3
–13
mA
μA
1.25
2.5
mA
ICC
External VCC Supply Current
VCC = 5V, VIN = 0V
l
VCC(UVLO)
VCC Undervoltage Lockout Threshold
VCC Rising
l
2.45
2.57
2.7
V
ΔVCC(HYST)
VCC Undervoltage Lockout Hysteresis
l
50
70
90
mV
VFWD(REG)
Forward Regulation Voltage (VIN − VOUT )
l
10
25
40
mV
ΔVGATE
MOSFET Gate Drive (VGATE – VSOURCE)
VFWD = 0.1V, I = 0 and –1μA
l
5
6.1
7.5
V
tON(GATE)
GATE Turn-On Delay
CGATE = 10nF, VFWD = 0.2V
l
0.25
0.5
μs
tOFF(GATE)
GATE Turn-Off Delay
CGATE = 10nF, VFWD = −0.2V
l
0.2
0.5
μs
VUV,OV(TH)
UV, OV Threshold Voltage
VUV Falling, VOV Rising
l
490
500
510
mV
ΔVUV,OV(HYST)
UV, OV Threshold Hysteresis
l
2.5
5
8.5
mV
VREV(TH)
REV Threshold Voltage
l
0.8
1.0
1.2
V
IUV,OV
UV, OV Current
V = 0.5V
l
0
±1
μA
IREV
REV Current
VREV = 1V
l
7
10
13
μA
IOUT
OUT Current
VOUT = 0V, 12V
l
–13
200
μA
ISOURCE
SOURCE Current
VSOURCE = 0V
l
–85
–130
μA
ICPO(UP)
CPO Pull-Up Current
VCPO = VIN = 2.9V
VCPO = VIN = 18V
l
l
–60
–50
–90
–75
–115
–100
μA
μA
IGATE
GATE Fast Pull-Up Current
GATE Fast Pull-Down Current
GATE Off Pull-Down Current
VFWD = 0.2V, ΔVGATE = 0V, VCPO = 17V
VFWD = –0.2V, ΔVGATE = 5V
VUV = 0V, ΔVGATE = 2.5V
l
60
–1.5
1.5
100
145
A
A
μA
IFLT,STAT(IN)
STATUS, FAULT Leakage Current
V = 18V
l
0
±1
μA
IFLT,STAT(UP)
STATUS, FAULT Pull-Up Current
V = 0V
l
–10
–12
μA
VOL
STATUS, FAULT Output Low Voltage
I = 1.25mA
l
0.2
0.4
V
VOH
STATUS, FAULT Output High Voltage
I = –1μA
l
ΔVGATE(ST)
MOSFET On Detect Threshold
STATUS Pulls Low, VFWD = 50mV
l
0.3
0.7
1.1
V
VFWD(FLT)
Open MOSFET Threshold (VIN – VOUT )
FAULT Pulls Low
l
200
250
300
mV
Ideal Diode Control
Input/Output Pins
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating for extended periods may affect device reliability and
lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
–8
VCC – 1 VCC – 0.5
V
Note 3: Internal clamps limit the GATE and CPO pins to a minimum of 5V
above, and a diode below SOURCE. Driving these pins to voltages beyond
the clamp may damage the device.
4352f
3
LTC4352
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, VSOURCE = VIN, VOUT = VIN,
VCC Open, unless otherwise noted.
VIN Current vs Voltage with
External VCC
VIN Current vs Voltage
300
1.6
VCC Current vs Voltage
1.50
VCC = 5V
250
1.2
VIN = 0V
1.25
200
0.8
ICC (mA)
IIN (μA)
IIN (mA)
1.00
150
100
0.50
50
0.4
0.25
0
–50
0
3
6
9
VIN (V)
15
12
18
3
0
5
4
VIN (V)
OUT Current vs Voltage
250
6
0
2
1
4352 G02
CPO Voltage vs Current
7
3
VCC (V)
4
5
6
4352 G03
GATE Voltage vs Current
7
VOUT = VIN – 0.1V
VIN = 18V
6
VIN = 18V
5
VCPO –VSOURCE (V)
200
IOUT (μA)
2
1
4352 G01
300
150
100
50
0
–50
0
0
3
6
9
15
12
VOUT (V)
18
VGATE –VSOURCE (V)
0
0.75
4
VIN = 2.9V
3
2
5
4
VIN = 2.9V
3
2
1
1
0
0
–1
0
–40
–20
4352 G04
–100
–60
–80
ICPO (μA)
–120
–1
0
–40
–20
4352 G05
STATUS, FAULT Output Low
Voltage vs Current
–60
–80
IGATE (μA)
–100
–120
4352 G06
STATUS, FAULT Output High
Voltage vs Current
4.0
1
3.5
3.0
2.5
0.6
VOH (V)
VOL (V)
0.8
0.4
2.0
1.5
1.0
0.2
0.5
0
0
0
1
2
3
CURRENT (mA)
4
5
4352 G07
0
–2
–4
–6
–8
CURRENT (μA)
–10
–12
4352 G08
4352f
4
LTC4352
PIN FUNCTIONS
VIN (Pin 1): Voltage Sense and Supply Input. Connect this
pin to the power input side of the MOSFET. The low voltage
supply VCC is generated from VIN. The voltage sensed at
this pin is used to control the MOSFET gate.
VCC (Pin 2): Low Voltage Supply. Connect a 0.1μF capacitor
from this pin to ground. When VIN ≥ 2.9V, this pin provides
decoupling for an internal regulator that generates a 4.1V
supply. For applications where VIN < 2.9V, connect an external supply voltage in the range 2.9V to 6V to this pin.
UV (Pin 3): Undervoltage Comparator Input. Connect this
pin to an external resistive divider from VIN. If the voltage at this pin falls below 0.5V, an undervoltage fault is
detected and the MOSFET is turned off. The comparator
has a built-in hysteresis of 5mV. Tie to VCC if unused.
OV (Pin 4): Overvoltage Comparator Input. Connect this
pin to an external resistive divider from VIN. If the voltage at this pin rises above 0.5V, an overvoltage fault is
detected and the MOSFET is turned off. The comparator
has a built-in hysteresis of 5mV. Tie to GND if unused.
STATUS (Pin 5): MOSFET Status Output. This pin is pulled
low by an open-drain output when the external MOSFET
is on. An internal 10μA current source pulls this pin up to
a diode below VCC. It may be pulled above VCC using an
external pull-up. Tie to GND or leave open if unused.
FAULT (Pin 6): Fault Output. This pin is pulled low by an
open-drain output when a fault occurs. This fault could
either be an undervoltage fault, an overvoltage fault, or
an open MOSFET fault. An internal 10μA current source
pulls this pin up to a diode below VCC. It may be pulled
above VCC using an external pull-up. Tie to GND or leave
open if unused.
REV (Pin 7): Reverse Current Enable Input. Connect
this pin to GND for normal diode operation that blocks
reverse current. Driving this pin above 1V fully turns on
the MOSFET gate to allow reverse current. An internal
10μA current source pulls this pin to GND.
OUT (Pin 8): Output Voltage Sense Input. Connect this pin
to the output side of the MOSFET. The voltage sensed at
this pin is used to control the MOSFET gate.
GND (Pin 9): Device Ground.
CPO (Pin 10): Charge Pump Output. Connect a capacitor
from this pin to the SOURCE pin. The value of this capacitor is approximately 10x the gate capacitance (CISS) of the
MOSFET switch. The charge stored on this capacitor is
used to pull-up the gate during a fast turn-on. Leave this
pin open if fast turn-on is not needed.
GATE (Pin 11): MOSFET Gate Drive Output. Connect this
pin to the gate of the external N-channel MOSFET switch.
An internal clamp limits the gate voltage to 6.1V above,
and a diode below SOURCE. During fast turn-on a 1.5A
pull-up charges GATE to CPO. During fast turn-off a 1.5A
pull-down discharges GATE to SOURCE.
SOURCE (Pin 12): MOSFET Gate Drive Return. Connect
this pin to the source of the external N-channel MOSFET
switch.
EXPOSED PAD (Pin 13, DD Package Only): Exposed Pad
may be left open or connected to device ground.
4352f
5
LTC4352
FUNCTIONAL DIAGRAM
VCC
VIN
CPO
2
1
10
CHARGE
PUMP
VCC
100μA
4.1V
+
LDO
+
GATE OFF
–
–
ENABLE
REVERSE
CURRENT
+
VIN
–
–
25mV
DISABLE
LDO
VCC LOW
+
–
2.57V
CP5
12 SOURCE
1V
+
–
+
+
SOURCE
CP2
REV
5
STATUS
6
FAULT
M1
–
VCC
OPEN
MOSFET
DETECT
0.5V
–
+
7
CP6
–
UV FAULT
OUT
10μA
0.7V
UV 3
8
10μA
VCC
CP3
GATE
OV 4
+
–
+
CP4
11 GATE
AMP
10μA
OV FAULT
M2
CP1
Z
*DD PACKAGE ONLY
9
13
GND
EXPOSED PAD*
4352 FD
4352f
6
LTC4352
OPERATION
The LTC4352 controls either single or back-to-back
N-channel MOSFETs in order to emulate an ideal diode. Dual
MOSFETs eliminate current flow from the input to the output
in an input undervoltage or overvoltage condition.
limit the GATE to SOURCE voltage to 6.1V, and the CPO
to SOURCE voltage to 6.7V. The same clamps also limit
the CPO and GATE pins to a diode voltage below the
SOURCE pin.
When enabled, an amplifier (AMP) monitors the voltage
between the VIN and OUT pins, and drives the GATE pin.
The amplifier controls the gate of the external MOSFET
to servo its forward voltage drop (VIN – OUT) to 25mV.
The gate voltage rises to enhance the MOSFET if the load
current causes more than 25mV of drop. For large output
currents the MOSFET gate is driven fully on and the voltage
drop is equal to ILOAD • RDS(ON).
OV, UV, and VCC comparators, CP1 to CP3, control power
passage. The MOSFET is held off whenever the OV pin
is above 0.5V, the UV pin is below 0.5V, or the VCC pin is
below 2.57V. There is a 40μs delay from all three conditions becoming good to GATE being allowed to turn on.
Overvoltage causes a fast turn-off, while undervoltage
activates a 100μA pull-down on GATE after a 7μs delay.
In the case of an input supply short-circuit, when the
MOSFET is conducting, a large reverse current starts
flowing from the load towards the input. The AMP detects
this failure condition as soon as it appears, and turns off
the MOSFET by pulling down the GATE pin. The REV pin
can be used to allow reverse current, overriding the diode
behavior.
The AMP quickly pulls-up the GATE pin whenever it senses
a large forward voltage drop. An external capacitor between
the CPO and SOURCE pins is needed for fast gate pull-up.
This capacitor is charged up, at device power-up, by the
internal charge-pump. This stored charge is used for the
fast gate pull-up.
Open-drain pull-down, M1, pulls the STATUS pin low
when the GATE to SOURCE voltage exceeds 0.7V, to
indicate that power is passing through the MOSFET. The
FAULT output, M2, pulls low during an undervoltage or
overvoltage fault condition. It also pulls low when GATE
is fully on and the forward voltage drop exceeds 250mV,
indicating the MOSFET has too much current or has failed
open circuit.
LDO is a low dropout regulator that generates a 4.1V
supply at the VCC pin from the VIN input. When a supply
below 2.9V is being ORed, an external supply in the 2.9V
to 6V range is required at the VCC pin. Comparator CP4
will disable LDO when VIN is below VCC.
The GATE pin sources current from the CPO pin, and sinks
current to the SOURCE and GND pins. Internal clamps
4352f
7
LTC4352
APPLICATIONS INFORMATION
supply voltage it turns off the MOSFET, thereby matching
the function and performance of an ideal diode.
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the
point of load. Diodes with storage capacitors also hold
up supply voltages when an input voltage sags or has a
brownout. The disadvantage of these approaches is the
diode’s significant forward voltage drop and the resulting
power loss. Additionally, diodes provide no information
concerning the status of the sourcing supply. Separate
control must therefore be added to ensure that a supply
that is out of range is not allowed to affect the load.
Power Supply Configuration
The LTC4352 can operate with supplies down to 0V. This
requires powering the VCC pin with an always present
external supply in the 2.9V to 6V range. If not always
present, a series 470Ω resistor or Schottky diode limits
device power dissipation and backfeeding of low VCC
supply when VIN is high. For a 2.9V to 4.7V VCC supply,
VIN should be lower than VCC. A 0.1μF bypass capacitor
should also be connected between the VCC and GND pins,
close to the device. Figure 2 illustrates this.
The LTC4352 solves these problems by using an external
N-channel MOSFET as the pass element (see Figure 1). The
MOSFET is turned on when power is being passed, allowing
for a low voltage drop from the supply to the load. When
the input source voltage drops below the output common
If VIN operates above 2.9V then the external supply at
VCC is not needed. The 0.1μF capacitor is still required
for bypassing.
Q1
Si7336ADP
TO LOAD
12V
C2
R4
2.7k
R5
2.7k
0.1μF
CPO SOURCE VIN
C1
0.1μF
GATE
OUT
D1
MOSFET
ON
D2
STATUS
VCC
UV
LTC4352
FAULT
FAULT
OV
REV
D1: GREEN LED LN1351C
D2: RED LED LN1261CAL
GND
4352 F01
Figure 1. 12V Ideal Diode with Status and Fault Indicators
TO LOAD
2.9V TO 18V
VIN
VCC
GATE
LTC4352
0.1μF
GND
OUT
TO LOAD
0V TO VCC
2.9V TO 4.7V
VIN
VCC
0.1μF
GATE
OUT
LTC4352
GND
TO LOAD
0V TO 18V
4.7V TO 6V
VIN
VCC
0.1μF
GATE
OUT
LTC4352
GND
4352 F02
Figure 2. Power Supply Configurations
4352f
8
LTC4352
APPLICATIONS INFORMATION
CPO and GATE Start-Up
In single MOSFET applications, CPO is initially pulled up
to a diode below the SOURCE pin (Figure 3). In back-toback MOSFET applications, CPO starts off at 0V, since
SOURCE is near ground (Figure 4). CPO starts ramping
up 10μs after VCC clears its undervoltage lockout level.
Another 40μs later, GATE will also start ramping up with
CPO if UV, OV and VIN – OUT conditions allow it to. The
ramp rate is decided by the CPO pull-up current into the
combined CPO and GATE pin capacitances. An internal
clamp limits the CPO voltage to 6.7V above SOURCE, while
the final GATE voltage is determined by the forward drop
servo amplifier.
MOSFET Selection
The LTC4352 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFET are
its threshold voltage, the maximum drain-source voltage
BVDSS, and the on-resistance RDS(ON).
The gate drive for the MOSFET is guaranteed to be between
5V and 7.5V. This allows the use of logic level threshold
VIN = 5V
C2 = 0.1μF
N-channel MOSFETs. The maximum allowable drainsource voltage, BVDSS, must be higher than the supply
voltages as the full supply voltage can appear across the
MOSFET when the input falls to 0V.
The FAULT pin pulls low to signal an open MOSFET fault
whenever the forward voltage drop across the enhanced
MOSFET exceeds 250mV. The RDS(ON) should be small
enough to conduct the maximum load current while not
triggering such a fault (when using FAULT), and to stay
within the MOSFET’s power rating at the maximum load
current.
CPO Capacitor Selection
The recommended value of the capacitor between the
CPO and SOURCE pins is approximately 10x the input
capacitance, CISS, of the MOSFET. A larger capacitor takes
a correspondingly longer time to charge up by the internal
charge pump. A smaller capacitor suffers more voltage
drop during a fast gate turn-on event as it shares charge
with the MOSFET gate capacitance.
VIN = 5V
C2 = 0.1μF
CPO
GATE
CPO
GATE
OUT
VOLTAGE
(5V/DIV)
VOLTAGE
(5V/DIV)
OUT
VIN, SOURCE
VIN
VCC
VCC
TIME (2.5ms/DIV)
4352 FO3
Figure 3. Start-up Waveform for Single MOSFET Application
TIME (2.5ms/DIV)
4352 FO4
Figure 4. Start-up Waveform for Back-to-Back MOSFET Application
4352f
9
LTC4352
APPLICATIONS INFORMATION
Undervoltage and Overvoltage Protection
Inrush Control
Unlike a regular diode, the LTC4352 can prevent out of
range input voltages from affecting the load voltage. This
requires back-to-back MOSFETs, and resistive dividers
from the input to the UV and OV pins. For an example,
see Figure 5.
The LTC4352 can be used for inrush control in applications
where the input supply is hot-plugged. See Figure 6. The
CPO capacitor is omitted, since fast turn-on with stored
charge is not desired here. Undervoltage holds the gate
off till the short pin makes contact. 40μs after the UV level
is satisfied, the MOSFET gate ramps up due to the CPO
pull-up current. A RC network on the gate further slows
down the output dV/dt, while allowing fast turn-off during
reverse current or overvoltage conditions. Resistor RG
prevents high frequency oscillations in Q2. A dedicated
hot swap controller may be needed if overcurrent protection is also desired.
MOSFET Q2 is required to block conduction through the
body diode of Q1 when its gate is held off. The resistive
dividers set up the input voltage range where the ideal
diode control is allowed to operate. Outside this range,
the gate is held off and the FAULT pin pulls low.
When using a CPO capacitor in circuit with back-to-back
MOSFETs, there will be a large inrush current to the
load capacitance due to the fast gate turn-on after UV,
OV levels are met. Without the capacitor, the inrush will
depend on the CPO pull-up current charging up the gate
capacitance.
Q2
Si7336ADP
Q1
Si7336ADP
TO LOAD
12V
Q2
Si7336ADP
Z1
Q1
Si7336ADP
RG
10Ω
R6
10k
TO LOAD
5V
CG
0.1μF
0.15μF
105k
R3
C2
31.6k
1%
R3
1k
1%
R2
VIN CPO
SOURCE
OV
3.09k
1%
GATE
OUT
5.11k
N/C
GND
4352 F06
VCC
R1
GND
CPO
LTC4352
R2
OV
STATUS
LTC4352
SOURCE GATE OUT
UV
FAULT
UV
VIN
C1
0.1 μF
REV
GND
BACKPLANE
Z1: DIODES INC. SMAJ12A
CONNECTORS
PLUG-IN CARD
4352 F05
Figure 5. 5V Ideal Diode with UV and OV Protection
Figure 6. Inrush and Ideal Diode Control on a Hot Swap Card
4352f
10
LTC4352
APPLICATIONS INFORMATION
External CPO Supply
Design Example
The internal charge pump takes milliseconds to charge
up the CPO pin capacitor especially during device power
up. This time can be shortened by connecting an external
supply to the CPO pin. A series resistor is needed to limit
the current into the internal clamp between the CPO and
SOURCE pins. The CPO supply should also be higher than
the main input supply to meet the gate drive requirements
of the MOSFET. Figure 7 shows such a 5V ideal diode application, where a 12V supply is connected to the CPO pin
through a 1k resistor. The 1k limits the current into the CPO
pin to 5.3mA, when the SOURCE pin is grounded.
The following design example demonstrates the calculations involved for selecting components in a 12V system
with 10A maximum load current (see Figure 1).
First, calculate the RDS(ON) of the MOSFET to achieve the
desired forward drop at full load. Assuming a VFWD of
50mV (which is comfortably below the 200mV minimum
open MOSFET fault threshold):
RDS (ON) ≤
VFWD 50mV
=
= 5mΩ
ILOAD 10A
The Si7336ADP offers a good solution, in a SO-8 sized
package, with a maximum RDS(ON) of 4mΩ and BVDSS
of 30V. The maximum power dissipation in the MOSFET
is:
Input Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current can cause transients that
exceed the 24V Absolute Maximum Rating of the VIN and
OUT pins. In ORing applications using a single MOSFET, one
surge suppressor connected from OUT to ground clamps all
the inputs. In the absence of a surge suppressor, an output
capacitance of 10μF is sufficient in most applications to
prevent the transient from exceeding 24V. Back-to-back
MOSFET applications, depending on voltage levels, may
require a surge suppressor on each supply input.
P = I2LOAD • RDS(ON) = (10A)2 • 4mΩ = 0.4W
With a maximum steady-state thermal resistance, θJA,
of 65°C/W, 0.4W causes a modest 26°C rise in junction
temperature of the Si7336ADP above the ambient.
The input capacitance, CISS, of the Si7336ADP is about
6500pF. Slightly exceeding the 10x recommendation, a
0.1μF capacitor is selected for C2.
Q1
Si7336ADP
TO LOAD
5V
VIN
12V
R7
1k
GATE
OUT
SOURCE
LTC4352
C2
0.1μF
CPO
GND
4352 F07
Figure 7. 5V Ideal Diode with External 12V Powering CPO for
Faster Start-up and Refresh
4352f
11
LTC4352
APPLICATIONS INFORMATION
LEDs, D1 and D2, require around 3mA for good luminous
intensity. Accounting for a 2V diode drop and 0.5V VOL,
R1 and R2 are set to 2.7k.
PCB Layout Considerations
Connect the VIN and OUT pin traces as close as possible to
the MOSFET’s terminals. Keep the traces to the MOSFET
wide and short to minimize resistive losses. The PCB
It is also important to put C1, the bypass capacitor for
the VCC pin, as close as possible between VCC and GND.
Also place C2 near the CPO and SOURCE pins. Surge
suppressors, when used, should be mounted close to the
LTC4352 using short lead lengths.
Q1
SO-8
CURRENT FLOW
CURRENT FLOW
S
D
S
D
W
S
D
G
D
TO LOAD
8
OUT
7
9
GND
10
11
VIA TO GROUND PLANE
GATE
TRACK WIDTH W:
0.03˝ PER AMPERE
ON 1OZ CU FOIL
W
SOURCE 12
FROM INPUT
SUPPLY
traces associated with the power path through the MOSFET
should have low resistance. See Figure 8.
C1
MSOP-12
6
5
4
3
VCC
2
1
VIN
LTC4352
VIA TO GROUND PLANE
4352 F08
DRAWING IS NOT TO SCALE!
Figure 8. Recommended PCB Layout for Power MOSFET
4352f
12
LTC4352
TYPICAL APPLICATIONS
Plug-in Card Supply Holdup Using Ideal Diode at Input
Q1
Si7336ADP
HOT SWAP
CONTROLLER
12V
SOURCE VIN
GATE
OUT
TO LOAD
+
CHOLDUP
LTC4352
GND
GND
GND
4352 TA02
BACKPLANE
CONNECTORS
PLUG-IN CARD
4352f
13
LTC4352
PACKAGE DESCRIPTION
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
R = 0.115
TYP
7
0.40 ± 0.10
12
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
2.38 ±0.05
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
2.38 ±0.10
1.65 ± 0.10
6
0.200 REF
0.25 ± 0.05
1
0.23 ± 0.05
0.45 BSC
0.75 ±0.05
0.45 BSC
2.25 REF
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DD12) DFN 0106 REV A
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4352f
14
LTC4352
PACKAGE DESCRIPTION
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
12 11 10 9 8 7
0.254
(.010)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0° – 6° TYP
0.406 ± 0.076
(.016 ± .003)
REF
GAUGE PLANE
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.53 ± 0.152
(.021 ± .006)
0.65
(.0256)
BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
0.86
(.034)
REF
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS12) 1107 REV Ø
4352f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4352
TYPICAL APPLICATION
0V to 18V Ideal Diode-OR
Si7336ADP
VIN1
0V TO 18V
TO LOAD
0.1μF
5V
CPO SOURCE VIN
GATE
0.1μF
OUT
STATUS
VCC
UV
LTC4352
FAULT
OV
REV
GND
Si7336ADP
VIN2
0V TO 18V
0.1μF
5V
CPO SOURCE VIN
GATE OUT
STATUS
VCC
0.1μF
UV
LTC4352
FAULT
OV
REV
GND
4352 TA03
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®
ThinSOT and PowerPath are trademarks of Linear Technology Corporation.
4352f
16 Linear Technology Corporation
LT 0708 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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