CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features ■ True dual-ported memory cells which enable simultaneous access of the same memory location ■ Fully asynchronous operation ■ Automatic power down ■ Expandable data bus to 32 bits, 36 bits or more using Master and Slave chip select when using more than one device ■ 4, 8 or 16K × 16 organization ■ (CY7C024AV/024BV [1]/ 025AV/026AV) ■ On chip arbitration logic ■ 4 or 8K × 18 organization (CY7C0241AV/0251AV) ■ Semaphores included to permit software handshaking between ports ■ 16K × 18 organization (CY7C036AV) ■ INT flag for port-to-port communication ■ 0.35 micron CMOS for optimum speed and power ■ Separate upper byte and lower byte control ■ High speed access: 20 and 25 ns ■ Pin select for Master or Slave (M/S) ■ Low operating power ❐ Active: ICC = 115 mA (typical) ❐ Standby: ISB3 = 10 A (typical) ■ Commercial and industrial temperature ranges ■ Available in 100-pin Pb-free TQFP and 100-pin TQFP Logic Block Diagram R/WL UBL R/WR UBR CEL CER LBL LBR OEL OER [2] IO8/9L–IO15/17L [3] IO0L–IO7/8L 8/9 8/9 12/13/14 IO Control A0L–A11/1213L Address Decode [4] 12/13/14 [4] [2] 8/9 8/9 IO Control [3] IO0L–IO7/8R Address Decode True Dual-Ported RAM Array IO8/9L–IO15/17R 12/13/14 [4] A0R–A11/12/13R [4] 12/13/14 A0L–A11/12/13L CEL OEL R/WL SEML [5] A0R–A11/12/13R CER OER R/WR SEMR Interrupt Semaphore Arbitration [5] BUSYL INTL UBL LBL M/S BUSYR INTR UBR LBR Notes 1. CY7C024AV and CY7C024BV are functionally identical. 2. IO8–IO15 for x16 devices; IO9–IO17 for x18 devices. 3. IO0–IO7 for x16 devices; IO0–IO8 for x18 devices. 4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices. 5. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06052 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 30, 2011 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations A7L A6L A9L A8L UBL LBL NC [6] A11L A10L OEL VCC R/WL SEML CEL IO 1L IO 0L IO 4L IO 3L IO 2L GND IO 9L IO 8L IO 7L IO 6L IO 5L Figure 1. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CY7C024AV/024BV (4K × 16) CY7C025AV (8K × 16) NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO 7R IO 8R IO 9R IO 10R IO 11R IO 12R IO 13R IO 14R GND IO 15R ŒR VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R NC NC NC NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A7R A6R A5R IO 10L IO 11L IO 12L IO 13L GND IO 14L IO 15L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R\WR GND SEMR CER UBR LBR NC[7] A11R A10R A9R A8R NC NC NC NC Notes 6. A12L on the CY7C025AV. 7. A12R on the CY7C025AV. Document #: 38-06052 Rev. *M Page 2 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations (continued) A7L A6L A9L A8L UBL LBL NC [8] A11L A10L OEL VCC R/WL SEML CEL IO 1L IO 0L IO 4L IO 3L IO 2L GND IO 10L IO 9L IO 7L IO 6L IO 5L Figure 2. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R IO 8R IO 17R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C0241AV (4K × 18) CY7C0251AV (8K × 18) NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO9L IO8L IO7L IO6L IO5L IO4L IO3L IO2L GND IO 7R IO 9R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 IO 10R IO 11R IO 12R IO 13R IO 14R IO 15R GND IO1L IO 16R OER IO0L OEL R/WR GND VCC SEMR R/WL CER SEML UBR CEL LBR UBL NC [9] LBL A11R A13L A10R A12L A9R A11L A8R A10L A7R A9L A6R A8L A5R A7L NC NC IO 8L IO 17L IO 11L IO 12L IO 13L IO 14L GND IO 15L IO 16L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R NC NC NC A9R A8R A7R A6R UBR LBR A13R A12R A11R A10R IO15R OER R/WR GND SEMR CER IO13R IO14R GND CY7C026AV (16K × 16) IO7R IO8R IO9R IO10R IO11R IO12R NC NC NC NC IO10L IO11L IO12L IO13L GND IO14L IO15L VCC GND IO0R IO1R IO2R VCC IO3R IO4R IO5R IO6R NC NC NC NC Notes 8. A12L on the CY7C0251AV. 9. A12R on the CY7C0251AVC. Document #: 38-06052 Rev. *M Page 3 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations (continued) A7L A6L A9L A8L A11L A10L UBL LBL A12L OEL VCC R/WL SEML CEL IO 1L IO 0L IO 4L IO 3L IO 2L GND IO 10L IO 9L IO 7L IO 6L IO 5L Figure 3. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCC GND IO 0R IO 1R IO 2R VCC IO 3R IO 4R IO 5R IO 6R IO 8R IO 17R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C036AV (16K × 18) NC NC NC A13L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A13R NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO 7R IO 9R IO 10R IO 11R IO 12R IO 13R IO 14R IO 15R GND IO 16R OER R/WR GND SEMR CER UBR LBR A12R A11R A10R A9R A8R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A7R A6R A5R NC NC IO 8L IO 17L IO 11L IO 12L IO 13L IO 14L GND IO 15L IO 16L Selection Guide CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV -20 CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV -25 Unit Maximum Access Time 20 25 ns Typical Operating Current 120 115 mA Typical Standby Current for ISB1 (Both ports TTL Level) 35 30 mA Typical Standby Current for ISB3 (Both ports CMOS Level) 10 10 A Parameter Document #: 38-06052 Rev. *M Page 4 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read and Write Enable OEL OER Output Enable A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K) IO0L–IO17L IO0R–IO17R Data Bus Input and Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (IO8–IO15 for x16 devices; IO9–IO17 for x18 devices) LBL LBR Lower Byte Select (IO0–IO7 for x16 devices; IO0–IO8 for x18 devices) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Architecture The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, IO and address lines, and control signals (CE, OE, RW). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be used for port to port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). They also have an automatic power down feature controlled by CE. Each port has its own output enable control (OE), which enables data to be read from the device. Functional Description The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and 16K ×16/18 dual port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. There are two ports permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16 or18-bit dual port static RAMs or multiple devices can be combined to function as a 32 or 36-bit or wider master and slave dual port static RAM. An M/S pin is provided for implementing 32 or 36-bit or wider memory applications. It does not need separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual port video and graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being Document #: 38-06052 Rev. *M accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic has eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C024AV/024BV/025AV/026AV and CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin Quad Flat Pack (TQFP) and 100-pin TQFP. Write Operation Data must be set up for a duration of tSD before the rising edge of RW to guarantee a valid write. A write operation is controlled by either the RW pin (see Figure 8 on page 12) or the CE pin (see Figure 9 on page 12). Required inputs for non-contention operations are summarized in Table 1 on page 7. If a location is being written to by one port and the opposite port tries to read that location, there must be a port to port flowthrough delay before the data is read on the output; otherwise the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wants to access a semaphore flag, then the SEM pin and OE must be asserted. Interrupts The upper two memory locations are for message passing. The highest memory location (FFF for the CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV, Page 5 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 3FFF for the CY7C026AV/36AV) is the mailbox for the right port and the second highest memory location (FFE for the CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2 on page 7. Busy The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin helps to expand the word width by configuring the device as a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin enables the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Document #: 38-06052 Rev. *M Semaphore Operation The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV provide eight semaphore latches, which are separate from the dual port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource. Otherwise (reads a one), it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and RW are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only IO0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 on page 7 shows sample semaphore operations. When reading a semaphore, all 16 and 18 data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one of them. But there is no guarantee which side controls the semaphore. Page 6 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Table 1. Non-Contending Read/Write Inputs Outputs IO9–IO17 Operation CE R/W OE UB LB SEM IO0–IO8 H X X X X H X X X H H H High Z High Z Deselected: Power Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write DIN0 into Semaphore Flag X X H H L Data In Data In Write DIN0 into Semaphore Flag High Z High Z Deselected: Power Down L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[10] Left Port Function R/WL CEL Right Port OEL A0L–13L INTL R/WR CER OER A0R–13R INTR X X X X X L[12] Set Right INTR Flag L L X FFF[13] Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H[11] X X L[11] L L X 1FFE (or 1/3FFE) X L 1FFE[13] H[12] X X X X X Set Left INTL Flag Reset Left INTL Flag X X X L Table 3. Semaphore Operation Example Function No action IO0–IO17 Left IO0–IO17 Right 1 1 Status Semaphore-free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Notes 10. See Functional Description on page 5 for specific highest memory locations by device. 11. If BUSYR=L, then no change. 12. If BUSYL=L, then no change. 13. See Functional Description on page 5 for specific addresses by device. Document #: 38-06052 Rev. *M Page 7 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV DC Input Voltage[15] ............................... –0.5V to VCC + 0.5V Maximum Ratings Output Current into Outputs (LOW) ............................. 20 mA Exceeding maximum ratings[14] may shorten the useful life of the device. User guidelines are not tested. Static Discharge Voltage.......................................... > 2001V Storage Temperature ................................. –65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied ............................................ –55°C to +125°C Operating Range Range Supply Voltage to Ground Potential............... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State ......................... –0.5V to VCC + 0.5V Ambient Temperature VCC Commercial 0°C to +70°C 3.3V 300 mV Industrial[16] –40°C to +85°C 3.3V 300 mV Electrical Characteristics Over the Operating Range CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Parameter Description -20 Min Typ Max Output HIGH Voltage (VCC=3.3V) VOL Output LOW Voltage VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage –0.3[17] 0.8 IOZ Output Leakage Current –10 10 –10 IIX Input Leakage Current 10 –10 ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Com’l. Standby Current (Both Ports TTL Level) CEL & CER VIH, f = fMAX Com’l. Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Com’l. ISB2 ISB3 ISB4 2.4 Min VOH ISB1 Typ V 0.4 120 175 Ind.[16] V 0.8 V 10 A 10 A 115 165 mA 135 185 mA 40 mA 35 45 30 40 50 mA 75 110 65 95 mA 75 105 mA 10 500 A 10 500 A 60 80 mA 70 90 mA [16] Ind.[16] Standby Current (Both Ports CMOS Level) Com’l. CEL & CER VCC0.2V, f = 0 Ind.[16] 10 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX[18] 70 Ind. V 2.0 –10 Com’l. Max 2.4 0.4 Ind. Unit -25 500 95 [16] Capacitance Parameter[19] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max Unit 10 pF 10 pF Notes 14. The voltage on any input or IO pin cannot exceed the power pin during power up. 15. Pulse width < 20 ns. 16. Industrial parts are available in CY7C026AV and CY7C036AV only. 17. VIL > –1.5V for pulse width less than 10ns. 18. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 19. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06052 Rev. *M Page 8 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Figure 4. AC Test Loads and Waveforms 3.3V 3.3V R1 = 590 C = 30 pF RTH = 250 OUTPUT OUTPUT R1 = 590 OUTPUT C = 30pF R2 = 435 C = 5 pF R2 = 435 VTH = 1.4V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 10% GND 90% 3 ns 90% 10% 3 ns Switching Characteristics Over the Operating Range [20] Parameter Description CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV -20 Min -25 Max Min Unit Max Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold From Address Change tACE[21] CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE[22, 23, 24] OE Low to Low Z tHZOE[22, 23, 24] OE HIGH to High Z tLZCE[22, 23, 24] CE LOW to Low Z tHZCE[22, 23, 24] CE HIGH to High Z tPU[24] CE LOW to Power Up tPD[24] CE HIGH to Power Down 20 25 ns tABE[21] Byte Enable Access Time 20 25 ns 20 25 20 3 ns 25 3 20 ns 25 12 3 13 3 12 3 15 12 ns ns ns 3 0 ns ns ns 15 0 ns ns Write Cycle tWC Write Cycle Time tSCE[21] CE LOW to Write End 15 20 ns tAW Address Valid to Write End 15 20 ns tHA Address Hold From Write End 0 0 ns tSA[21] Address Setup to Write Start 0 0 ns 20 25 ns Notes 20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 21. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 22. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 23. Test conditions used are Load 3. 24. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12. Document #: 38-06052 Rev. *M Page 9 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Characteristics Over the Operating Range (continued)[20] Parameter CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Description -20 Min Unit -25 Max Min Max tPWE Write Pulse Width 15 20 tSD Data Setup to Write End 15 15 ns tHD Data Hold From Write End 0 0 ns tHZWE[23, 24] R/W LOW to High Z tLZWE[23, 24] R/W HIGH to Low Z tWDD[25] tDDD[25] Write Pulse to Data Delay 45 50 ns Write Data Valid to Read Data Valid 30 35 ns tBLA BUSY LOW from Address Match 20 20 ns tBHA BUSY HIGH from Address Mismatch 20 20 ns tBLC BUSY LOW from CE LOW 20 20 ns Busy ns 12 15 3 ns 0 ns Timing[26] tBHC BUSY HIGH from CE HIGH tPS Port Setup for Priority tWB R/W HIGH after BUSY (Slave) 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 15 17 ns tBDD[27] BUSY HIGH to Data Valid 17 17 5 ns 5 ns 20 25 ns Interrupt Timing[26] tINS INT Set Time 20 20 ns tINR INT Reset Time 20 20 ns Semaphore Timing tSOP SEM Flag Update Pulse (OE or SEM) 10 12 ns tSWRD SEM Flag Write to Read Time 5 5 ns tSPS SEM Flag Contention Window 5 5 ns tSAA SEM Address Access Time Data Retention Mode The CY7C024AV/024BV/025AV/026AV and CY7C0241AV/0251AV/036AV are designed for battery backup. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 2. CE must be kept between VCC – 0.2V and 70 percent of VCC during the power up and power down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0V). 20 25 ns Timing Data Retention Mode VCC 3.0V VCC 2.0V 3.0V VCC to VCC – 0.2V CE Parameter ICCDR1 Test Conditions[28] at VCCDR = 2V tRC V IH Max Unit 50 A Notes 25. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12. 26. Test conditions used are Load 2. 27. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual). 28. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested. Document #: 38-06052 Rev. *M Page 10 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms Figure 5. Read Cycle No. 1 (Either Port Address Access)[29, 30, 31] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)[29, 32, 33] tACE CE and LB or UB tDOE OE tHZCE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Figure 7. Read Cycle No. 3 (Either Port)[29, 31, 32, 33] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 29. R/W is HIGH for read cycles. 30. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 31. OE = VIL. 32. Address valid prior to or coincident with CE transition LOW. 33. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document #: 38-06052 Rev. *M Page 11 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Figure 8. Write Cycle No. 1: R/W Controlled Timing[34, 35, 36, 37] tWC ADDRESS tHZOE [40] OE tAW CE [38, 39] tPWE[37] tSA tHA R/W tHZWE[40] DATA OUT tLZWE NOTE 41 NOTE 41 tSD tHD DATA IN Figure 9. Write Cycle No. 2: CE Controlled Timing[34, 35, 36, 42] tWC ADDRESS tAW CE [38, 39] tSA tSCE tHA R/W tSD tHD DATA IN Notes 34. R/W or CE must be HIGH during all address transitions. 35. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 36. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to enable the IO drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 38. To access RAM, CE = VIL, SEM = VIH. 39. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 40. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested. 41. During this period, the IO pins are in the output state, and input signals must not be applied. 42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06052 Rev. *M Page 12 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Figure 10. Semaphore Read After Write Timing, Either Side[43] tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD IO 0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 11. Timing Diagram of Semaphore Contention[44, 45, 46] A0L –A2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes 43. CE = HIGH for the duration of the above timing (both write and read cycle). 44. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH. 45. Semaphores are reset (available to both ports) at cycle start. 46. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable. Document #: 38-06052 Rev. *M Page 13 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH)[47] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Figure 13. Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note 47. CEL = CER = LOW. Document #: 38-06052 Rev. *M Page 14 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Figure 14. Busy Timing Diagram No.1 (CE Arbitration)[48] CELValid First ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Figure 15. Busy Timing Diagram No.2 (Address Arbitration)[48] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note 48. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. Document #: 38-06052 Rev. *M Page 15 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Figure 16. Interrupt Timing Diagram Left Side Sets INTR : ADDRESSL tWC WRITE 1FFF (OR 1/3FFF) tHA[49] CE L R/W L INT R tINS [50] Right Side Clears INT R : tRC READ 7FFF (OR 1/3FFF) ADDRESSR CE R tINR [50] R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE 1FFE (OR 1/3FFE) tHA[49] CE R R/W R INT L [50] tINS Left Side Clears INT L: tRC READ 7FFE OR 1/3FFE) ADDRESSR CE L tINR[50] R/W L OE L INT L Notes 49. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 50. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document #: 38-06052 Rev. *M Page 16 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Package Diagram Ordering Code Package Type Operating Range 15 CY7C024BV-15AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial 20 CY7C024AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C024AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial CY7C024AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C024AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial 25 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Package Name Ordering Code CY7C025AV-20AXC 51-85048 Package Type 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial CY7C025AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C025AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial 16K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) 20 25 Package Name Ordering Code Package Type Operating Range CY7C026AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Commercial Commercial CY7C026AV-25AC 51-85048 100-Pin Thin Quad Flat Pack CY7C026AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack CY7C026AV-25AI 51-85048 100-Pin Thin Quad Flat Pack CY7C026AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial Ordering Code Definitions CY 7C 02 X XX - XX X X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free (RoHS Compliant) Package Type: A = 100-pin TQFP Speed Grade: XX = 15 ns or 20 ns or 25 ns XX = AV/BV - 3.3 V Depth: X = 4 or 5 or 6 4 = 4K; 5 = 8K; 6 = 16K 02 = Width: × 16 7C = Dual Port SRAM CY = Cypress Device Document #: 38-06052 Rev. *M Page 17 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Package Diagram Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048 *E Document #: 38-06052 Rev. *M Page 18 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Document History Page Document Title: CY7C024AV/024BV/025AV/026AV, CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Document Number: 38-06052 ECN No. Orig. of Change ** 110204 SZV 11/11/01 Change from Spec number: 38-00838 to 38-06052 *A 122302 RBI 12/27/02 Power up requirements added to Maximum Ratings Information Rev. Submission Date Description of Change *B 128958 JFU 9/03/03 Added CY7C025AV-25AI to Ordering Information *C 237622 YDT See ECN Removed cross information from features section *D 241968 WWZ See ECN Added CY7C024AV-25AI to Ordering Information *E 276451 SPN See ECN Corrected x18 for 026AV to x16 *F 279452 RUY See ECN Added Pb-free packaging information Corrected pin A113L to A13L on CY7C026AV pin list Added minimum VIL of 0.3V and note 16 *G 373580 RUY See ECN Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Information *H 380476 PCX See ECN Added to Part Ordering information: CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI, CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI *I 2543577 NXR/AESA 07/25/08 Updated note number 33 on page 12 from “R/W must be HIGH during all address transitions” to “R/W or CE must be HIGH during all address transitions” *J 2623540 VKN/PYRS 12/17/08 Added CY7C024BV part *K 2896038 RAME 03/19/10 Removed inactive parts from ordering information table Updated package diagram *L 3110406 ADMU 12/14/2010 Added Ordering Code Definitions. *M 3210221 ADMU 03/30/2011 Updated Package Diagram from *D to *E Part CY7C025AV-25AC from Ordering Information table. Document #: 38-06052 Rev. *M Page 19 of 20 [+] Feedback CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. 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Document #: 38-06052 Rev. *M Revised March 30, 2011 Page 20 of 20 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback