M64894FP/GP Serial Input PLL Frequency Synthesizer for TV/VCR REJ03F0166-0200 Rev.2.00 Jun 14, 2006 Description The M64894 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using I2C BUS control. It contains the prescaler with operating up to 1.3 GHz. 4 band drivers and tuning amplifier for direct tuning. Built-in 4 band drivers. Features • • • • • • • • • 4 integrated PNP band drivers (IO = 40 mA, Vsat = 0.2 V Typ@VCC1 to 13.2 V) Built-in high-withstanding voltage tuning Amplifier Low power dissipation (ICC = 20 mA, VCC = 5 V) Built-in prescaler with input amplifier (Fmax = 1.3 GHz) I2C bus control (Read and write mode) X’tal 4 MHz is used to realize 3 type of tuning steps (Division ratio 1/512, 1/640, 1/1024) Built-in 5-level A/D converter Programmable chip address 16-pin small SOP/SSOP package Function • • • • • • • • • 2-modulus prescaler (1/32 and 1/33) Built-in 4 MHz crystal oscillator and reference divider Programmable divider (10-bit M counter, 5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op.Amp for direct tuning I2C bus receiver 5-level A/D converter Application TV, VCR tuners Recommended Operating Condition • Supply voltage range VCC1 = 4.5 to 5.5 V VCC2 = VCC1 to 13.2 V VCC3 = 28 to 35 V • Rated supply voltage VCC1 = 5 V VCC2 = 12 V VCC3 = 33 V Rev.2.00 Jun 14, 2006 page 1 of 12 M64894FP/GP Block Diagram ADS 15 Xin 16 SDA 14 SCL 13 ADC 12 Vin 9 Vtu 10 5-level ADC 2 OSC VCC3 11 I C Bus Receiver Divider 10 10-bit M Counter Lock Detector AMP Phase Comparator Charge Pump 1/32, 1/33 5 5-bit S Counter 4 1/8 Power-on Reset Bias Band Switch Driver AMP 1 fin 2 GND Rev.2.00 Jun 14, 2006 page 2 of 12 3 VCC1 4 VCC2 5 BS4 6 BS3 7 BS2 8 BS1 M64894FP/GP Pin Arrangement M64894FP/GP fin 1 16 Xin GND 2 15 ADS VCC1 3 14 SDA VCC2 4 13 SCL BS4 5 12 ADC BS3 6 11 VCC3 BS2 7 10 Vtu BS1 8 9 Vin (Top view) Outline: PRSP0016DA-A (16P2S-A) [FP] PRSP0016JA-A (16P2Z-A) [GP] Pin Description Pin No. 1 2 3 4 Symbol fin GND VCC1 VCC2 Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V. Power supply voltage terminal. 5.0 V ± 0.5 V Power supply for band switching, VCC1 to 13.2 V This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fREF), the “source” current state becomes active. If it is behind, the “sink” current becomes active. If the phases are the same, the high impedance state becomes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35 V 5 6 7 8 BS4 BS3 BS2 BS1 9 Vin Filter input (Charge pump output) 10 11 12 Vtu VCC3 ADC/ftest Tuning output Power supply voltage 3 13 14 SCL SDA Clock input Data input 15 16 ADS Xin AD converter input/ Test port Address switching input This is connected to the crystal oscillator Rev.2.00 Jun 14, 2006 page 3 of 12 PNP open collector method is used. When the band switching data is “H”, the output is ON. When it is “L”, the output is OFF. A/D conversion of the input voltage. In control byte data input, the programmable freq. Divider output and reference freq. output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. In lead mode, it outputs lock detector output and power down flag and a state of 5 level A/D converter. Chip address sets it up with the input condition of terminal. 4.0 MHz crystal oscillator is connected. M64894FP/GP Absolute Maximum Ratings (Ta = −20°C to +75°C, unless otherwise noted) Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Output voltage Symbol VCC1 VCC2 VCC3 VI VO Voltage applied when the band output is OFF Band output current VBSOFF ON the time when the band output is ON tBSON Power dissipation Operating temperature Pd Topr Storage temperature Tstg IBSON Ratings 6.0 14.4 36.0 6.0 6.0 14.4 Unit V V V V V V 50.0 10 mA s 450 (470) –20 to +75 –40 to +125 mW °C °C Condition Pin3 Pin4 Pin11 Not to exceed VCC1 fREF output Per 1 band output circuit 50mA per 1 band output circuit 3circuit are pn at same time Ta = +75°C Recommended Operation Conditions (Ta = −20°C to +75°C, unless otherwise noted) Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbol VCC1 VCC2 VCC3 fopr1 fopr2 IBDL Rev.2.00 Jun 14, 2006 page 4 of 12 Ratings 4.5 to 5.5 VCC1 to 13.2 28 to 35 4.0 80 to 1,300 0 to 40 Unit V V V MHz MHz mA Conditions Pin3 Pin4 Pin11 Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time are max. It is prohibited to have 3 or more circuits turned on at the same time. M64894FP/GP Electrical Characteristics (Ta = −20°C to +75°C, VCC1 = 5.0 V, VCC2 = 12 V, VCC3 = 33 V, unless otherwise noted) Min. Limits Typ. Max. Unit “H” input voltage VIH 13 to 14 3.0 — VCC1 + 0.3 V “L” input voltage VIL 13 to 14 — — 1.5 V “H” input current IIH — — 10 µA VCC1 = 5.5V, Vi = 4.0V “L” input current IIL VOL 13 to 14 13, 14 14 — — –4/–14 — –10/30 0.4 µA µA VCC1 = 5.5V, Vi = 0.4V VCC1 = 5.5V, IO = 3mA IOLK1 VTOH 14 5 to 8 5 to 8 10 — 11.6 — 32.5 — 11.8 — — 10 — –10 — µA V µA V VCC1 = 5.5V, VO = 5.5V VCC2 = 12V, IO = –40mA VCC2 = 12V band SW is OFF VCC3 = 33V Output voltage “L” VTOL 10 — 0.2 0.4 V VCC3 = 33V “H” output current “L” output current IOH 9 — 270 370 µA VCC1 = 5.0V, VO = 2.5V IOL 9 9 3 4 4 — — — — — 70 — 20 — 6.0 110 50 30 0.3 8.0 µA nA mA mA mA VCC1 = 5.0V, VO = 2.5V VCC1 = 5.5V, VO = 2.5V VCC1 = 5.5V VCC2 = 12V VCC2 = 12V Item Input pin SDA output Band SW Tuning output Charge pump “H” output voltage “L” output voltage Output voltage Leak current Output voltage “H” Leak current Supply current 1 4 circuits: OFF Supply current 1circuits: ON, 2 Output: OPEN Test Pin Symbol VLO VBS ICPLK ICC1 ICC2A ICC2B Test Conditions 4 — 46.0 48.0 mA VCC2 = 12V IO = –40mA ICC2C Output current 40mA Supply current 3 ICC3 11 — 3.0 4.0 mA VCC3 = 12V Output ON Note: Typical values are measured at VCC1 = 5.0 V, VCC2 = 12 V, VCC3 = 33 V, Ta = +25°C. Rev.2.00 Jun 14, 2006 page 5 of 12 M64894FP/GP Switching Characteristics (Ta = −20°C to +75°C, VCC1 = 5.0 V, VCC2 = 12 V, VCC3 = 33 V, unless otherwise noted) Min. Limits Typ. Max. Unit Prescaler operating frequency fopr 1 80 — 1300 MHz Operating input voltage Vin 1 −24 −27 −30 −27 −18 0 4.7 4 4.7 4 4.7 0 250 — — 4 — — — — — — — — — — — — — — — — 4 4 4 4 4 100 — — — — — — — 1000 300 — dBm Item Clock pulse frequency Bus free time Data hold time SCL low hold time SCL high hold time Set up time Data hold time Data set up time Rise time Fall time Set up time Test Pin Symbol tSCL tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tr tf tSUSTO Rev.2.00 Jun 14, 2006 page 6 of 12 13 14 13 13 13 13, 14 13, 14 13, 14 13, 14 13, 14 13, 14 kHz µs µs µs µs µs s ns ns ns µs Test Conditions VCC1 = 4.5 to 5.5V Vin = Vinmin to Vinmax VCC1 = 4.5 to 80 to 100MHz 5.5V 100 to 200MHz 200 to 800MHz 800 to 1000MHz 1000 to 1300MHz VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V VCC1 = 4.5 to 5.5V M64894FP/GP Method of Setting Data The input information to consist of 2 or data of 4 bytes to lead to chip address is received in I2C bus receiver. It shows a definition of bus protocol admitted in the following. 1_STA CA CB 2_STA CA D1 3_STA CA CB 4_STA CA D1 STA : Start condition STO : Stop condition CA : Chip address CB : Control data byte BB : Band SW data byte D1 : Divider data byte D2 : Divider data byte BB D2 BB D2 STO STO D1 CB D2 BB STO STO The information of 5 bytes necessary for circuit operation is chip address and control data, band SW data of 2 bytes and divider byte of 2 bytes. After the chip address input, 2 or data of 4 bytes are received. Function bit is contained the first and the third data byte to distinguish between divider data and control data, band data, and “0” goes ahead of divider data, and “1” goes ahead of control data, band SW data. SDA SCL S STA 1-7 8 9 1-7 Address CA 0 ACK 8 1-7 9 Data ACK 8 Data 9 ACK P STO Write Mode Format Address byte Byte MSB 1 1 0 0 0 MA1 MA0 0 LSB A Divider byte 1 Divider byte 2 Control byte1 Band SW byte 0 N7 1 X N14 N6 CP X N13 N5 T2 X N12 N4 T1 X N11 N3 T0 BS4 N10 N2 RSa BS3 N9 N1 RSb BS2 N8 N0 OS BS1 A A A A 1 A0 LSB A A Read Mode Format Byte Address byte Status byte 1 MSB 1 POR Rev.2.00 Jun 14, 2006 page 7 of 12 1 FL 0 X 0 X 0 X MA1 A2 MA0 A1 M64894FP/GP Data Cording Example Write Mode Format Example Byte Address Byte Divider byte 1 Divider byte 2 MSB 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 LSB 1 1 1 Control byte 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 1 1 1 1 1 LSB 1 1 1 Band SW byte 0 0 0 0 1 Note: fVCO = N 8 fREF = 16544 8 (4MHz/1024) = 517MHz Condition in Data Setting ADS input VCC1 Dividing ratio N = 16544 C.P.current 270µA fREF division ratio 1/1024 BS4 output ON Read Mode Format Example Byte Address byte Status byte 1 input Status byte 1 output MSB 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 Condition in Data Setting FL “1” output at locked ADC input at open Test Mode Data Set Up Method Test Mode Bit Set Up X MA1, MA0 : Random, 0 or 1. normal “0” : Programmable address bit Address Input Voltage MA1 0 to 0.1 ± VCC1 0 Always valid 0 0.4 ± VCC1 to 0.6*VCC1 1 0.9 ± VCC1 to VCC1 1 Note: N14 to N0: How to set dividing ratio of the programmable the divider MA0 0 1 0 1 Dividing ratio N = N14 (214 = 16384) + +N0 (20 = 1) Therefore, the range of division N is 1,024 to 32,768 Example) fVCO = fREF • 8 • N = 3.90625 • 8 • N = 31.25 • N (kHz) CP: Setting Up The Charge Pump Current of The Phase Comparator CP 0 1 Rev.2.00 Jun 14, 2006 page 8 of 12 Charge pump current 70 µA 270 µA Mode Test Normal M64894FP/GP T2, T1, T0: Setting Up for The Test Mode T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge Pump Normal operation High impedance Sink Source High impedance High impedance Pin 12 Condition ADC input ADC input ADC input ADC input fREF output f1/N output Mode Normal operation Test mode Test mode Test mode Test mode Test mode RSa, RSb: Set Up for The Reference Frequency Division Ratio RSa 1 0 X RSb 1 1 0 Division Ratio 1/512 1/1024 1/640 OS 0 Tuning Voltage Output ON Mode Normal 1 OFF Test OS: Set Up The Tuning Amplifier POR : Power on reset flag. “1” output at reset FL : Lock detector flag. “1” output at locked, “0” output at unlocked A2, A1, A0: 5 Level A/D Converter Output Data ADC Input Voltage A2 0.6 ± VCC1 to VCC1 1 0.45 ± VCC1 to 0.6 ± VCC1 0 0.3 ± VCC1 to 0.45 ± VCC1 0 0.15 ± VCC1 to 0.3 ± VCC1 0 0 to 0.15 ± VCC1 0 Note: The voltage accuracy allowance range: 0.03 ± VCC1 (V) Power On Reset Operation (Initial state the power is turned ON) BS4 to BS1 Charge pump Tuning amplifier Charge pump current Frequency division ratio : OFF : High impedance : OFF : 270 µA : 1/1024 Rev.2.00 Jun 14, 2006 page 9 of 12 A1 0 1 1 0 0 A0 0 1 0 1 0 M64894FP/GP Timing Diagram Start condition SDA tLOW tBUF tR tHDSTA tF SCL tHDSTA tHDDAT tHIGH Stop condition tSUDAT tSUSTO tSUSTA Start condition Crystal Oscillator Connection Diagram 16 18 pF 4 MHz Rev.2.00 Jun 14, 2006 page 10 of 12 Crystal oscillator characteristics Actual resistance: less than 300 Ω Load capacitance: 20 pF Stop condition M64894FP/GP Application Example Built-in PLL Tuner +5 V VCC1 to 12 V UHF VHF + 10 1000 p 3 5 SW M64894FP/GP 18 VCC2 15 ADS +B 4 47 k BS4 11 BS4 5 47 k BS3 12 1 TEST BS3 47 k BS2 13 BS2 7 47 k 3 DATA M5943x series 14 IF IF 6 BS1 14 4-Band Tuner BS1 8 MCU fIN 17 4 CLK GND 16 13 Lo 1.5 n 1000 p 15 2 EN 0.1 10 VT 9 56 k 56 k PD 20 LD/f1/N 12 ADC 16 10 9 XOUT 7 XIN 6 18 p AGC 1 2.2 n AFT 100 p GND 8 11 4 MHz +33 V Note: Filter constant is for reference. Add a capacitor to stabilize the circuit. Rev.2.00 Jun 14, 2006 page 11 of 12 BT Units R: Ω C: F AGC M64894FP/GP Package Dimensions JEITA Package Code P-SOP16-4.4x10-1.27 RENESAS Code PRSP0016DA-A Previous Code 16P2S-A 9 E HE 16 MASS[Typ.] 0.15g *1 F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 A2 8 Index mark A1 c D A L *2 *3 e Detail F bp y Reference Dimension in Millimeters Symbol D E A2 A1 A bp c HE e y L JEITA Package Code P-SSOP16-4.4x5-0.65 RENESAS Code PRSP0016JA-A MASS[Typ.] 0.08g E 9 F *1 HE 16 Previous Code 16P2Z-A Min Nom Max 9.8 10.0 10.2 4.2 4.4 4.6 1.5 0.05 1.9 0.35 0.4 0.5 0.13 0.15 0.2 0° 10° 5.9 6.2 6.5 1.07 1.27 1.47 0.1 0.2 0.4 0.6 A2 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. A1 8 Index mark c *2 D A L Reference Symbol *3 b p e y Detail F D E A2 A A1 bp c HE e y L Rev.2.00 Jun 14, 2006 page 12 of 12 Dimension in Millimeters Min 4.8 4.2 Nom Max 5.0 5.2 4.4 4.6 1.5 1.9 0.05 0.17 0.22 0.32 0.13 0.15 0.2 0° 10° 5.9 6.2 6.5 0.5 0.65 0.8 0.10 0.2 0.4 0.6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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