ONSEMI NCP2830

NCP2830
1W Constant Filterless
Class-D Audio Amplifier
+
−
C1
4.7 mF
6.3 V
C2
4.7 mF
6.3 V
1 mF
Audio Inputs
1 mF
C7
C8
2.2 mF,
6.3 V
C2N
VB_OUT
VB_IN
C5
10 mF,
6.3 V
OUTM
RES2
17
16
INP 1
15 VB_OUT
INM 2
14 C1P
AGND 3
13 C2P
AVDD 4
12 PVDD
WM 5
11 RES1
6
7
8
9
10
(TOP VIEW)
20−Pin 3 x 3 x 0.50 mm QFN
Exposed pad must be soldered to
PCB Ground Plane
NCP2830
ORDERING INFORMATION
OUTM
INM
INP
C6
10 mF,
6.3 V
18
C1N
C1N C2P
PVDD
AVDD
WM
GS
SD
Digital Control
C4
19
PGND_CP
2.2 mF, C3
6.3 V
C1P
Battery
20
GS
Cellular Phones and Digital Cameras
Personal Digital Assistant and Portable Media Player
Audio Accessories
GPS
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
C2N
•
•
•
•
XXXX
A
L
Y
W
G
Typical Applications
XXXX
ALYWG
G
UQFN20
MU SUFFIX
CASE 523AL
VB_IN
1 W to 8 W load for VDD from 2.7 V up to 5.5 V
High quality audio (THD+N = 0.04%)
Low noise: SNR up to 100 dB
Very Fast Turn On Time: 200 ms
Overall system efficiency optimization: up to 89%
Superior PSRR (−88 dB): Direct Connection to Battery
Very Low Quiescent Current 7 mA
Optimized PWM Output Stage: Filterless Capability
Selectable gain of 2 V/V or 4 V/V
Fully Differential Capability:
Thin QFN 3x3 mm, 20 pins
This Device uses Halogen−Free Molding Compound
This is a Pb−Free Device
20
1
SD
•
•
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAM
PGND_D
Features
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OUTP
NCP2830 is a cost effective mono audio power amplifier designed
for portable communication device applications such as mobile
phones. Due to its integrated charge pump structure, this part is
capable of delivering 1 W of continuous average power to an 8.0 W
Bridge Tied Load no matter the voltage provided by a lithium/Ion
battery.
NCP2830 is a preferred solution for long playback audio with
minimum space required.
Added to a fast start−up time of 200 ms and a −88dB PSRR, the
NCP2830 audio power amplifier is specifically designed to provide
high quality and level output power from low supply voltage,
requiring very few external components.
PGND_D PGND_CP
AGND
RES1
RES2
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
OUTP
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 0
1
Publication Order Number:
NCP2830/D
NCP2830
2.2 mF,
6.3 V
PVDD
C1P
2.2 mF,
6.3 V
C1N
C2P
C2N
VB_IN
Lithium/
Ion
Battery
VB_OUT
AVDD
Charge Pump
Stepup
2x10 mF,
6.3 V
0603
2 x 4.7 mF,
0603
I/O from Microcontroller
I/O from Microcontroller
I/O from Microcontroller
WM
GS
Shutdown
and Biasing
SD
INM
OUTM
1 mF
Filterless
Class D Audio
Amplifier
INP
OUTP
1 mF
AGND
PGND_D
RES1
PGND_CP
Figure 2. Simplified Block Diagram
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2
RES2
NCP2830
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
20
VB_IN
I
This pin must be externally connection in a star configuration with Pin n°15. The Cout filtering
(10 mF/6.3 V/0603) capacitor must be connected as close as possible to the connection point.
Description
3
AGND
P
Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of
track length. Thus, a star connection is required.
9
PGND_C
P
P
Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of
track length. Thus, a star connection is required.
17
PGND_D
P
Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of
track length. Thus, a star connection is required.
4, 12
AVDD
PVDD
P
These pins are dedicated to the signal connection for the battery input. They must be connected to the
power source (ie lithium/Ion battery) in a star mode. It must be decoupled by a low ESR ceramic
capacitor. (4.7 mF/6.3 V/0603). The use of a 4 or more layers board is advised. In that case, a dedicated
plane for this battery voltage is mandatory.
1
INP
I
Positive audio input of the fully differential filterless Class D Audio Amplifier
2
INM
I
Negative audio input of the fully differential filterless Class D Audio Amplifier
16
OUTM
O
Negative audio output of the fully differential filterless Class D Audio Amplifier
18
OUTP
O
Positive audio output of the fully differential filterless Class D Audio Amplifier
5
WM
I
Wire Mode pin: When a low level is applied to this pin, the device operates in Normal mode (VB = 5 V
typ.). In case of a high level, it switches to a Wire Mode (VB = VDD)
6
SD
I
Shutdown input. The device enters in shutdown mode when a low level is applied on this pin.
7
GS
I
Gain Select Input. When a low level is applied to this pin, an internal 2 V/V gain is setup. In case of a
high level, it switches to an internal 4 V/V gain.
8
C2N
P
One side of the external charge pump capacitor is connected to this pin, associated with C2P. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2 mF/6.3 V/0603
recommended).
10
C1N
P
One side of the external charge pump capacitor is connected to this pin, associated with C1P. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2mF/6.3V/0603
recommended).
13
C2P
P
One side of the external charge pump capacitor is connected to this pin, associated with C2N. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2 mF/6.3 V/0603
recommended).
14
C1P
P
One side of the external charge pump capacitor is connected to this pin, associated with C1N. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2 mF/6.3 V/0603
recommended).
15
VB_OUT
O
This pin must be externally connection in a star configuration with Pin n°20. The Cout filtering
(10 mF/6.3 V/0603) capacitor must be connected as close as possible to the connection point. This VB
input is dedicated to supply the internal power stages. Thus, it must be connected to Cout with the
lowest impedance connection.
11
RES1
I
Reserved for production. Must be connected to GND plane in final application
19
RES2
I
Reserved for production. Must be connected to GND plane in final application
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NCP2830
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
− 0.3 to + 7.0
V
VDG
IDG
−0.3 to VDD + 0.3
1
V
mA
Human Body Model (HBM) ESD Rating are (Note 3)
ESD HBM
2000
V
Machine Model (MM) ESD Rating are (Note 3)
ESD MM
200
V
ILU
(Note 4)
mA
RqJC
29 (Note 7)
°C/W
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
Maximum Junction Temperature (Note 6)
TJMAX
+150
°C
Storage Temperature Range
TSTG
−65 to +150
°C
Moisture Sensitivity (Note 5)
MSL
Level 1
AVDD, PVDD Pins: Power Supply Voltage (Note 2)
Digital Input WM; SD; GS Pin:
Input Voltage
Input Current
Latch up Current Maximum Rating
QFN 3 x 3 mm Package (Note 7) Thermal Resistance Junction−to−Case
Operating Ambient Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25 °C.
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) $200 V per JEDEC standard: JESD22−A115 for all pins.
4. Latch up Current Maximum Rating:
$100 mA for all pins, except digital pins per JEDEC standard: JESD78 class II.
$10mA for Digital Pins per JEDEC standard: JESD78 class II
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
6. The thermal shutdown set to 150°C (typical) avoids irreversible damage on the device due to power dissipation.
7. The RqCA is dependent of the PCB heat dissipation. The maximum power dissipation (PD) is dependent by the min input voltage, the max
output current and external components selected.
R qCA
125 * T A
PD
* R qJC
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NCP2830
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 3.6 V (Note 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7
−
5.5
V
GLOBAL SYSTEM
VDD
Operating System Voltage
ISD
Shutdown Current
VSD = low, VGS = Low, VWM = Low
−
0.01
−
mA
ISD
Shutdown Current
VSD = low, VGS = Low, VWM = Low, Vp
= 5.5 V (Note 9)
−
−
1.5
mA
IQ
Quiescent Current
2X Mode, No load
−
9.5
11
mA
IQ
Quiescent Current
1.5X Mode, No load
−
7
8
mA
IQ
Quiescent Current
Wire Mode, No load
−
3
4.5
mA
RSD
Resistance from SD to GND
−
350
−
kW
RWM
Resistance from WM to GND
−
350
−
kW
RGS
Resistance from GS to GND
−
350
−
kW
VIH
Digital Pins High Voltage
1.2
−
−
V
VIL
Digital Pins Low Voltage
−
−
0.4
V
550
650
750
kHz
BOOST SECTION
FSW1
Charge Pump Switching Frequency
VB
Output Regulated Voltage
No Load, VINM=VINP=0, VWM= Low, 2X
Mode
4.75
5
5.25
V
VB
Output Regulated Voltage
No Load, VINM = VINP = 0, VWM = Low,
1.5X Mode
4.75
5
5.25
V
VB−Ripple
Output Voltage Ripple
No Load, VINM = VINP = 0, VWM = Low,
2X Mode or 1.5X Mode
−
7
−
mV
TPrecharge
Precharge time
C5 = C6 = 10 mF
−
1.6
−
ms
VTR1
Transition Voltage between 2X Mode
and 1.5X Mode
−
3.8
−
V
VTR2
Transition Voltage between 2X Mode
and Wire Mode
−
4.65
−
V
275
325
375
kHz
CLASS D SECTION
FSW2
Class D Switching frequency
RINL
Audio Input resistance
VGS = Low (Note 10)
−
15
−
kW
RINH
Audio Input resistance
VGS = High (Note 10)
−
7.5
−
kW
ZSD
Shutdown impedance
VSD = Low
−
20
−
kW
GHI
Gain High
VGS = High, RL = 8 W
1.85
2
2.15
V/V
GLO
Gain Low
VGS = Low, RL = 8 W
3.7
4
4.3
V/V
VOS
Output Offset Voltage
VINM = VINP = 0
−
1
−
mV
Tstart
Turn ON time
VB = VDD, VSD = High
−
200
−
ms
TOFF
Turn Off time
−
1
−
ms
VN
Output Noise Voltage
No Filter
−
56
−
mVRMS
VN
Output Noise Voltage
A−Weighting filter
−
37
−
mVRMS
THD+N
Total harmonic distortion + Noise
Pout = 0.25 W, f = 1 kHz, RL = 8 W
−
0.04
−
%
THD+N
Total harmonic distortion + Noise
Pout = 1 W, f = 1 kHz, RL = 8 W
−
0.2
−
%
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at
TJ = TA = 25°C.
9. The maximum value is measured at 85°C
10. Guaranteed by design
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NCP2830
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 3.6 V (Note 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−
−88
−
dB
CLASS D SECTION
PSRR
Power Supply Rejection Ratio
Vin = AC Grounded, f = 217 Hz, VWM =
VGS = Low, VRIPPLE = 200 mVPP
CMRR
Common mode rejection ratio
Vic = 1 VPP
f = 1 kHz
dB
VGS = Low
VGS = High
−
−
−70
−60
−
−
VDD = 5 V; Pout = 1 W
VDD = 2.7 V; Pout = 0.5 W
−
−
89
80
−
−
1
1.2
−
h
Efficiency
RL = 8 W
POUT
Output Power
THD+N < 10%, f = 1 kHz, VWM = Low
%
W
8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at
TJ = TA = 25°C.
9. The maximum value is measured at 85°C
10. Guaranteed by design
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
12
10
(nA)
IQ (mA)
8
6
4
2
0
2.7
−40°C
25°C
85°C
3.2
3.7
4.2
VDD (V)
4.7
5.2
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
2.5
3.0
Figure 3. IQ vs VDD
3.5
4.0
VP (V)
4.5
5.0
5.5
3.0
2.5
Figure 4. ISD vs VDD
100
90
80
70
h (%)
60
50
Pout = 0.25 W
40
0.5 W
30
1W
20
1.5 W
10
2W
0
5.5
100
100
10
10
VP = 2.7 V
1
3V
3.6 V
4.0
VDD (V)
3.5
VP = 2.7 V
1
3V
3.6 V
4.2 V
4.2 V
0.1
4.5
Figure 6. Boost efficiency vs Output Power
THD (%)
THD (%)
Figure 5. VB Output Ripple
5.0
0.1
4.5 V
4.5 V
5V
5V
0.01
10
5.5 V
100
1000
10000
0.01
10
Pout (mW)
5.5 V
100
1000
10000
Pout (mW)
Figure 7. THD vs Pout RL = 8 W, WM = Low
Figure 8. THD vs Pout RL = 8 W, WM = High
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
0
PSRR
VPP = 200 mVPP
−20
RL = 8 W
−30
−10
−20
−40
−50
−60
−70
−80
−50
−60
−70
−80
−90
−100
−100
100
1000
10000
FREQUENCY (Hz)
−110
10
100000
VDD =
3.6 V
−10
−20
−30
PSRR (dB)
−40
−50
−60
−70
100000
−60
−70
−80
−90
−100
−100
1000
10000
−110
10
100000
VDD =
4.2 V
−50
−90
100
PSRR
VPP = 200 mVPP
RL = 8 W
−40
−80
−110
10
10000
0
PSRR
VPP = 200 mVPP
RL = 8 W
100
1000
10000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. PSRR vs Frequency
Figure 12. PSRR vs Frequency
100000
0
−20
−40
RMS VALUE (dB)
PSRR (dB)
−30
1000
Figure 10. PSRR vs Frequency
0
−20
100
FREQUENCY (Hz)
Figure 9. PSRR vs Frequency
−10
VDD =
3.3 V
−40
−90
−110
10
PSRR
VPP = 200 mVPP
RL = 8 W
−30
PSRR (dB)
PSRR (dB)
0
VDD =
2.7 V
−10
−60
−80
−100
−120
−140
−160
−180
−200
10
Figure 13. Outputs Behavior During GSM
Burst
100
1000
10000
FREQUENCY (Hz)
100000
Figure 14. FFT of Switching Signal During
GSM Burst
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NCP2830
TYPICAL OPERATING CHARACTERISTICS
7.E−05
120
No Filter
6.E−05
A Weighting
3.E−05
60
40
2.E−05
20
1.E−05
0.E+00
10
VDD =
3.6 V
100
1000
10000
0
10
100000
Pout = 1 W
VDD = 3.6 V
100
1000
10000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Noise vs Frequency
Figure 16. SNR vs Frequency
10
10
VDD = 3 V
WM = High
Low Volume
THD+N (%)
1.0
THD+N (%)
A Weighting
80
SNR (dB)
NOISE VRMS
5.E−05
4.E−05
No Filter
100
Pout =
10 mW
0.1
Pout = 250 mW
RL = 8 W
100000
VDD = 2.7 V
VDD = 3.6 V
VDD = 5 V
1.0
0.1
Pout =
50 mW
0.01
10
100
1000
10000
100000
0.01
10
10000
Figure 17. THD+N vs Frequency
Figure 18. THD+N vs Frequency
100000
0
VDD = 3 V
VDD = 3.3 V
−10
VDD = 2.7 V
VDD = 3.6 V
−20
VDD = 3.6 V
VDD = 4.2 V
VDD = 5 V
−30
VDD = 5 V
CMRR (dB)
THD+N (%)
1000
FREQUENCY (Hz)
10
1.0
100
FREQUENCY (Hz)
0.1
Vi = 1 VDD
G = 6dB
−40
−50
−60
−70
−80
−90
0.01
10
100
1000
10000
100000
−100
10
100
1000
10000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. THD+N vs Frequency
Figure 20. CMRR vs Frequency
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100000
NCP2830
TYPICAL OPERATING CHARACTERISTICS
0
100
Vi = 1 VDD
G = 12dB
90
−20
80
−30
70
−40
60
VDD =
3.6 V
−50
50
(%)
CMRR (dB)
−10
−60
40
−70
30
−80
20
−90
10
−100
10
100
1000
10000
FREQUENCY (Hz)
0
100000
Vp=2.7V
Vp=3V
Vp=4.2V
Vp=4.5V
Vp=5V
Vp=5.5V
0
Figure 21. CMRR vs Frequency
400
800
1200
Pout (mW)
1600
Figure 22. Global System Efficiency
VB
VSD
OUTP
Figure 23. Turn ON Sequence
OUTP FILTERED
VB
SD TIED to VDD
IVDD
Figure 24. Turn ON Sequence
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2000
NCP2830
DETAIL OPERATING DESCRIPTION
2.2mF
2.2mF
C3
C4
0
PGND_CP
VB_out
PVDD
PVDD
C1
4.7mF
0
SWITCHES
Mode
0
10mF
MATRIX
FSW2
VB_in
WM
WM
OUT
C6
VBOUT
CHARGE PUMP
VBIN
+
+
−
−
Vref
C5
10mF
0
0
0
VB_in
0
Vref
FSW1
AVDD
FSW2
ANALOG
C2
4.7mF
Mode
SD
0
FSW1
VB_out
AGND
0
GS
INM
7.5k
7.5k
INP
0
+
PWM
Modulator
−
7.5k
0
OUTM
15k
0
VB_out
7.5k
GS
OUTP
15k
RES2 RES1 PGND_D
0
0
Figure 25. Functional Block Diagram
Detailed Descriptions
The NCP2830 consists of two parts: a DC−DC converter
and a mono class D amplifier. These two parts are strongly
matched in order to obtain the best operation of the global
system.
reference. An error amplifier and a voltage to current
conversion allow injecting in the Capacitors C3 and C4 the
necessary current to maintain 5 V in output. This linear
regulation reduces the output voltage ripple (7 mV typ) and
allows a noise free operation.
DC−DC CONVERTER
Turn ON/OFF sequence
The DC−DC converter is based on a charge pump
technique. The switching frequency is synchronized with
the class D amplifier (FSW2 = 2 x FSW1) in order to avoid
mixing frequency. The regulation is based on a voltage
regulation. The output voltage is permanently monitored
through a resistor ladder and compared to an internal
The turn ON and turn OFF sequence has been adapted to
an audio applications environment. When the battery
voltage is connected to the VDD pins, the output capacitance
is precharged to the VDD voltage. When VSD is High, the
charge pump is activated and the output voltage rises up to
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NCP2830
30 kHz Built−in Low Pass Filter
5 V. Internally, the class D amplifier starts to operate when
VB equals 4.5 V.
When VSD is low, the charge pump is deactivated and the
VB voltage is maintain to the VDD value. During this
shutdown mode, it is not possible to sink current through the
VB pin. Figure 26 depicts the turn ON/OFF sequence.
This filter allows directly connecting a DAC or a CODEC
to the NCP2830 input without risk of output noise increase
due to a mixing frequency with the DAC/CODEC output
frequency. Consequently, the best operation with DACs or
CODECs is guarantee without need of additional external
components.
Audio
OUTP
OUTM
Input Capacitors Cin
Due to its fully differential architecture the NCP2830 does
not require input capacitors if the differential source is
biased from 0.5 V to VDD − 0.8 V. However, it is possible to
use input capacitors when the differential source is not
biased or in single ended configuration. In this case it is
necessary to take into account the corner frequency which
can influence the low frequency response of the NCP2830.
The following equation will help to choose the adequate
input capacitors.
VDD
VDD
0
SD
0
5V
4.5 V
0.9 x VDD
VDD
VD
fC +
0
TPrecharge Tstart
Toff
1
2p @ Z in @ C in
(eq. 1)
With Zin the input impedance of the NCP2830.
Figure 26. Turn ON/OFF Sequence
Overcurrent Protection
In order to maximize the global efficiency, the system
permanently monitors the battery voltage and changes its
operating mode:
• When VDD is less than 3.8 V (typ) the system operates
in 2X mode.
• Between 3.8 V and 4.65 V the system operates in 1.5X
mode.
• If VDD is greater than 4.65 V the system switches
automatically to Wire Mode operation (VB = VDD)
This protection allows detecting an over current in the
H−Bridge. When the current is higher than 2 A the H−Bridge
is put in high impedance. When the short circuit is removed
or the current is lower, the NCP2830 go back to normal
operation. This protection allows avoiding overcurrent due
to a bad assembly (Output shorted together, to VB or to
ground).
WM pin
Use very low ESR ceramic capacitors (X5R/X7R) will
help to reduce the output resistance of the charge pump and
thus improve the system efficiency.
DESIGN PROCEDURE
Components Selection
This external pin allows controlling the activation of the
boost whatever the battery voltage is. For example, if no
power is required, there is no need to boost the supply
voltage of the class D amplifier. In that case, disabling the
boost by a high logic on WM pin, allows supplying directly
the class D by the battery voltage (VB = VDD) and
optimizing the efficiency.
Input Capacitor (C1 and C2)
NCP2830 is aimed to be connected on the battery line. For
such a device, it is mandatory to get as low ripple as possible
so as to avoid conducted emission on the battery line. As
stated above, the noise generated by turn−on and turn−off
transients is optimized by a controlled switching speed.
Placing two 4.7 mF/6.3 V (0603 size) input capacitors as
close as possible to PDD and AVDD pin will also help to
avoid any disturbance for other sensitive parts also
connected on the battery line.
CLASS D AMPLIFIER
The NCP2830 is based on a mono class D audio amplifier.
This structure is composed by a preamplifier stage, a PWM
stage and a H−Bridge stage.
Gain selection
The preamplifier stage consists in applying a gain to the
input signal selectable by a dedicated digital pin GS.
The gain setting is given by the following truth table:
GS
Gain Av V/V
Input Impedance kW
0
2
15
1
4
7.5
Flying Capacitors (C3 and C4)
As stated above, the value of these capacitors has a direct
impact on the load regulation and output resistance of the
charge pump. The converter must provide a regulated DC
voltage with a sine wave AC current, the frequency of which
is twice the audio signal frequency. Selecting a 2.2 mF/6.3 V
(0603 size) will help regarding the load regulation and the
device’s ability to provide sufficient current drive.
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12
NCP2830
Output Capacitors (C5 and C6)
Optional Output Filters
The value and ESR of this capacitor are directly linked to
the ripple of the regulated output voltage. As the charge
pump must provide up to 450 mA to the internal audio
amplifier, two 10 mF/6.3 V capacitors (0603 size) should
allow the converter to give its maximum output power
capability.
If the traces between the amplifier and the speaker are
short, there’s no need for an output filter.
In case of applications where short output traces are not
possible, it is necessary to protect the application as much as
possible from EMI pollution. The use of small 0603 Chip
Ferrite beads is a good alternative.
Layout Recommendations
As all switching devices, special care must be observed in
routing power supplies and ground.
VDD pins must be decoupled by C1 and C2 placed as close
as possible to the NCP2830 in order to reduce parasitic
inductance.
GND pins must be connected to a ground plane. In order
to reduce parasitic elements, it is better to connect all the
ground pins to the same Ground plane.
Figure 28. Optional EMI Filter
Thermal Considerations
For thermal dissipation, it is recommended to connect the
exposed pad of the NCP2830 to a plan connected to the
ground as depicted Figure 27.
Demo Board Available:
The NCP2830EVB/D evaluation board that configures the
device in typical application.
Figure 27. Recommended PCB Layout
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NCP2830
TYPICAL APPLICATION
2.2 mF, 6.3 V
C3
Battery
C1P
+
−
C2P
2.2 mF, 6.3 V
C2N
PVDD
AVDD
C1
4.7 mF
6.3 V
C1N
C4
VB_OUT
VB_IN
C2
4.7 mF
6.3 V
WM
Digital Control
10 mF, 6.3 V
C5
10 mF,
6.3 V
C6
NCP2830
GS
SD
OUTM
INM
Audio Inputs
INP
OUTP
AGND PGND_D RES1 PGND_CP RES2
Figure 29. Fully Differential Configuration
2.2 mF,
6.3 V
C3
Battery
C1P
+
−
C2P
2.2 mF,
6.3 V
C2N
PVDD
AVDD
C1
4.7 mF
6.3 V
C1N
C4
VB_IN
C2
4.7 mF
6.3 V
WM
Digital Control
10 mF,
6.3 V
VB_OUT
C5
10 mF,
6.3 V
C6
NCP2830
GS
SD
Audio Inputs
1 mF
C7
1 mF
C8
OUTM
INM
INP
OUTP
AGND PGND_D RES1 PGND_CP RES2
Figure 30. Single−Ended Configuration
ORDERING INFORMATION
Device
Package
Shipping†
NCP2830MUTXG
UQFN20 3x3 mm
(Pb–Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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14
NCP2830
PACKAGE DIMENSIONS
UQFN20 3x3, 0.4P
CASE 523AL−01
ISSUE O
D
A B
ÍÍÍ
ÍÍÍ
ÍÍÍ
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉ
ÉÉ
0.15 C
2X
EXPOSED Cu
TOP VIEW
0.15 C
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
2X
L
L
A3
A1
DETAIL B
A
0.08 C
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
ALTERNATE
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
3.00 BSC
1.70
1.90
3.00 BSC
1.70
1.90
0.40 BSC
0.20
0.40
0.00
0.15
A1
NOTE 4
C
SIDE VIEW
SOLDERING FOOTPRINT*
SEATING
PLANE
20X
0.52
D2
DETAIL A
6
1
11
E2
2X
3.30
2X
1.86
1
20X
L
e
16
20X
BOTTOM VIEW
b
0.10 C A
0.05 C
20X
0.40
PITCH
B
NOTE 3
0.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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15
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP2830/D