NUS6189MN Low Profile Overvoltage Protection IC with Integrated MOSFET This device represents a new level of safety and integration by combining an overvoltage protection circuit (OVP) with a 30 V P−channel power MOSFET, a low VCE(SAT) transistor, and low RDS(on) power MOSFET or charging. The OVP is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such events, the IC quickly disconnects the input supply from the load, thus protecting it. The integration of the additional transistor and power MOSFET reduces layout space and promotes better charging performance. The IC is optimized for applications that use an external AC−DC adapter or a car accessory charger to power a portable product or recharge its internal batteries. Features • • • • • • • • • • • Overvoltage Turn−Off Time of Less Than 1.0 ms Accurate Voltage Threshold of 6.85 V, Nominal Undervoltage Lockout Protection; 2.8 V, Nominal High Accuracy Undervoltage Threshold of 2.0% −30 V Integrated P−Channel Power MOSFET Low RDS(on) = 50 mW @ −4.5 V High Performance −12 V P−Channel Power MOSFET Single−Low Vce(sat) Transistors as Charging Power Mux Compact 3.0 x 4.0 mm QFN Package Maximum Solder Reflow Temperature @ 260°C This is a Pb−Free Device Benefits • • • • http://onsemi.com MARKING DIAGRAM NUS 6189 ALYWG G 1 QFN22 CASE 485AT NUS6189 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device NUS6189MNTWG Package Shipping† QFN22 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Provide Battery Protection Integrated Solution Offers Cost and Space Savings Integrated Solution Improves System Reliability Optimized for Commercial PMUs from Top Suppliers Applications • Portable Computers and PDAs • Cell Phones and Handheld Products • Digital Cameras © Semiconductor Components Industries, LLC, 2008 October, 2008 − Rev. 0 Publication Order Number: NUS6189MN/D Gate1 GND Control Batt Batt NUS6189MN 22 Source1 18 1 17 Batt Batt Batt VIN Base VCC Collector OVPOUT Collector Collector Collector Batt OVPOUT 6 12 OVPOUT OVPOUT Collector Gate2 11 Emitter 7 Source2 (Top View) Figure 1. Pinout Adapter Input Source2 12 MOSFET2 VIN 14 3 BJT Base Collector OVP 15 VCHG Emitter 10 VCC OVPOUT 9, 11, 13 8 4,5,6,7 CHG CTL VSense Source1 1 VSense 18 MOSFET1 2,16,17,21,22 Blocks Integrated in NUS6189 GND 19 Gate1 Bat FET Batt Vbat Batt Battery Figure 2. Typical Charging Solution for Qualcomm QSC60xx http://onsemi.com 2 Qualcomm QSC60xx NUS6189MN FUNCTIONAL PIN DESCRIPTIONS Pin Function Description 1 Source 1 2, 16, 17, 21, 22 Batt These pins are the drain of MOSFET2 and connect to the battery and the Vbat pin of the PMIC. 3 Base The base of the internal bipolar transistor is connected to this pin. It connects to the Charge Control pin of the PMIC. 4, 5, 6, 7 Collector The collector of the internal bipolar transistor connects to these pins and should be connected to the more positive side of the current sense resistor as well as the more positive Vsense pin of the PMIC. 8 Emitter This pin is connected to the emitter of the bipolar transistor. It should be connected externally to the OVPOUT pins. 9, 11, 13 OVPOUT 10 Gate2 12 Source 2 14 VCC This pin is the VCC pin of the OVP chip. It needs to be connected to pins 12 and 15. 15 VIN This pin senses the output voltage of the charger. If the voltage on this input rises above the overvoltage threshold (VTH), the OVPOUT pin will be driven to within 1.0 V of VIN, thus disconnecting the FET. The nominal threshold level is 6.85 V. This pin needs to be connected to pins 12 and 14. 18 Gate1 19 Gnd 20 Control This pin is the source of MOSFET1 and connects to the more negative Vsense pin of the PMIC and to the more negative side of the current sense resistor. These pins are the output of the OVP circuit. Internally they connect to the drain of MOSFET2. These pins connect externally to the Vcharge pin of the PMIC. This pin is the gate of MOSFET2. It is not normally connected to external circuitry. The source of the OVP FET is connected to this pin. This pin needs to be connected to pins 14 & 15. This pin is the gate of MOSFET1. It connects to the Bat FET pin of the PMIC. This is the ground reference pin for the OVP chip. This logic signal is used to control the state of OVPOUT and turn−on/off the P−channel MOSFET. A logic level high results in the OVPOUT signal being driven to within 1.0 V of VCC which turns off MOSFET2. If this pin is not used, it should be connected to ground. http://onsemi.com 3 NUS6189MN MAXIMUM RATINGS Rating Symbol Value Unit VIN to Ground VIN -0.3 to 30 V Gate2 Voltage to Ground VG2 -0.3 to 30 V VCNTRL -0.3 to 13 V Vshunt 12 V PD 1.2 W qJ-A 137 145 98 103 77 82 °C/W TCmax 125 °C Operating Ambient Temperature (PD = 0.5 W, Note 1) TAmb 109 °C Operating Junction Temperature (All Dice) TJmax 150 °C Thermal Resistance Junction−to−Case (Note 4) YJC 30 °C/W Storage Temperature Range Tstg -65 to 150 °C Continuous Input Current (TA = 50°C, Notes 1 & 3) Imax 2.6 A Gate-to-Source Voltage MOSFET1 VGS1 ±8.0 V Drain-to-Source Voltage MOSFET1 VDS1 −12 V Drain-to-Source Voltage MOSFET2 VDS2 −30 V Collector-Emitter Voltage BJT VCEO −20 V Collector-Base Voltage BJT VCBO −20 V Emitter-Base Voltage BJT VEBO −7.0 V Control Pin to Ground Shunt Voltage (OVPOUT to Batt) Maximum Power Dissipation (TA = 50°C, Notes 1 & 3) Thermal Resistance, Junction-to-Air (Note 1) Average q for chip, minimum copper Maximum q for power device, minimum copper Average q, for chip (Note 2) Maximum q for power device (Note 1) Average q for chip (Note 1) Maximum q for power device (Note 1) Operating Case Temperature (Note 4) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface−mounted on FR4 board using 0.25 inch sq pad size (Cu area = 0.37 in sq [1 oz] including traces). 3. VIN = 6.0 V, all power devices fully enhanced. 4. Surface−mounted on FR4 board using 400 mm sq pad size, 4 oz Cu, PD < 800 mW. http://onsemi.com 4 NUS6189MN ELECTRICAL CHARACTERISTICS (TJ = 25°C, CNTRL ≤ 1.5 V, VCC = 6.0 V, unless otherwise specified) Symbol Min Typ Max Unit Vth 6.65 6.85 7.08 V Vhyst 50 150 200 mV RIN 70 150 – kW Control Voltage High (Output On) VcntrlHI 1.50 – – V Control Voltage Low (Output Off) VcntrlLO – – 0.50 V Control Current High (Vih = 5.0 V) Iih – 95 200 mA Control Current Low (Vil = 0.5 V) Iil – 10 − mA Gate2 Voltage High (VIN = 8.0 V; ISource = 10 mA) Gate2 Voltage High (VIN = 8.0 V; ISource = 0.25 mA) Gate2 Voltage High (VIN = 8.0 V; ISource = 0 mA) Voh VIN – 1.0 VIN – 0.25 VIN – 0.1 – – – – – – V Gate2 Voltage Low (VIN = 6.0 V; ISink = 0 mA, Control = 0 V) Vol – – 0.10 V ISink 10 33 50 mA Turn on Delay − Input (VIN stepped down from 8 to 6 V; measured at 50% point of OVPOUT, Note 5) ton_IN – – 10 ms Turn off Delay − Input (VIN stepped up from 6.0 to 8.0 V; CL = 12 nF Output > VIN − 1.0 V) toff_IN – 0.5 1.0 ms Turn on Delay − Control (Control signal stepped down from 2.0 to 0.5 V; measured to 50% point of OVPOUT, Note 5) ton_CT – – 10 ms Turn off Delay − Control (Control signal stepped up from 0.5 to 2.0 V; CL = 12 nF Output > VIN −1.0 V) toff_CT – 1.0 2.0 ms VIN Operating Voltage Range (Note 5) VIN 3.0 4.8 25 V Input Bias Current IBias – 0.75 1.0 mA Undervoltage Lockout (VIN Decreasing) VLock 2.5 2.8 3.0 V VOVP – – – 33 66 90 54 100 135 mV – − − 50 52 90 90 100 135 – – -0.1 – -1.0 -100 mA ICES – – -0.1 mA hfe 180 – – – VCE(sat) – – -0.10 -0.069 -0.12 -0.09 V Characteristic OVP THRESHOLD Input Threshold (VIN Increasing) Input Hysteresis (VIN Decreasing) Input Impedance (VIN = Vth) CONTROL INPUT OVP GATE DRIVE VOLTAGE Gate2 Sink Current (VIN < VTh, OVPOUT = 1.0 V, Note 5) TIMING TOTAL DEVICE OVP FET (MOSFET2) (TJ = 25°C, VCC = 6.0 V, unless otherwise specified) Voltage Drop (VIN to OVPOUT, VGS = -4.5 V) ILoad = 0.6 A ILoad = 1.0 A ILoad = 1.0 A, TJ = 150°C (Note 5) On Resistance ILoad = 0.6 A ILoad = 1.0 A ILoad = 1.0 A, TJ = 150°C (Note 5) RDS(on) Off State Leakage Current TJ = 125°C ILeak mW CHARGING BJT (TJ = 25°C, unless otherwise specified) Collector-Emitter Cutoff Current (VCES = -20 V, Note 5) DC Current Gain (IB = -2.0 mA, VCE = -2.0 V, Note 6) Collector-Emitter Saturation Voltage IC = -1.0 A, IB = -0.01 A IC = -1.0 A, IB = -0.1 A http://onsemi.com 5 NUS6189MN ELECTRICAL CHARACTERISTICS (TJ = 25°C, CNTRL ≤ 1.5 V, VCC = 6.0 V, unless otherwise specified) Characteristic Symbol Min Typ Max Unit Input Capacitance (VEB = -0.5 V, f = 1.0 MHz, Note 5) Cibo – 240 400 pF Output Capacitance (VCB = -3.0 V, f = 1.0 MHz, Note 5) Cobo – 50 100 pF VDS – – – 32 44 62 40 50 70 mV – − − 32 44 62 40 50 70 CHARGING FET (MOSFET1) (TJ = 25°C, unless otherwise specified) Voltage Drop Across FET VGS = -4.5 V, ILoad = 1.0 A VGS = -2.5 V, ILoad = 1.0 A VGS = -4.5 V, ILoad = 1.0 A, TJ = 150°C (Note 5) On Resistance VGS = -4.5 V, ILoad = 1.0 A VGS = -2.5 V, ILoad = 1.0 A VGS = -4.5 V, ILoad = 1.0 A, TJ = 150°C, (Note 5) RDS(on) mV Off State Leakage Current (Note 5) TJ = 125°C ILeak – – −0.1 – −1.0 −10 mA Input Capacitance CISS – 1330 – pF Output Capacitance COSS – 200 – pF Reverse Transfer Capacitance CRSS – 115 – pF Total Gate Charge (Note 5) QG(TOT) – 13 15.7 nC Threshold Gate Charge QG(TH) – 1.5 – nC Gate-to-Source Charge QGS – 2.2 – nC Gate-to-Drain Charge QGD – 2.9 – nC Gate Resistance RG – 14.4 – W Forward Transconductance (VDS = -6 V, ID = 1.0 A) gfs – 0.9 – S VGS(th) −0.45 −0.67 −1.1 V VGS(th)/TJ – 2.7 – mV/ °C Gate Threshold Voltage (VGS = VDS, ID = -250 mA) Negative Threshold Temperature Coefficient 5. Guaranteed by design. 6. Pulsed Condition: Pulse Width = 300 us, Duty Cycle < 2%. http://onsemi.com 6 NUS6189MN TYPICAL CHARACTERISTICS − 12V, P−CHANNEL MOSFETS (MOSFET1 − CHARGING) −1.7 − −8.0 V 5 6 −1.5 V 4 VGS = −1.4 V 3 2 1 TJ = 25°C 0 1 2 3 4 5 1 0.5 1.0 1.5 2.0 Figure 4. Transfer Characteristics 0.04 TJ = 25°C 0.03 TJ = −55°C 1 2 3 4 5 6 −ID, DRAIN CURRENT (A) 0.05 TJ = 25°C VGS = −2.5 V 0.04 VGS = −4.5 V 0.03 0.02 1 2 3 4 5 6 −ID, DRAIN CURRENT (A) Figure 5. On−Resistance vs. Drain Current Figure 6. On−Resistance vs. Drain Current and Gate Voltage 10,000 ID = −3 A VGS = −4.5 V VGS = 0 V TJ = 150°C −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C 2 Figure 3. On−Region Characteristics TJ = 100°C 1.4 TJ = 100°C 3 −VGS, GATE−TO−SOURCE VOLTAGE (V) VGS = 4.5 V 1.6 TJ = 25°C 4 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.05 0.02 VDS ≥ −10 V 5 0 6 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −1.6 V −ID, DRAIN CURRENT (A) −ID, DRAIN CURRENT (A) 6 1.2 1,000 1.0 0.8 0.6 −50 −25 0 25 50 75 100 125 150 TJ = 100°C 100 2 4 6 8 10 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. On−Resistance Variation with Temperature Figure 8. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 7 12 NUS6189MN VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 2400 Ciss 2000 1600 Ciss 1200 Crss 800 Coss 400 0 −4 −2 0 2 4 6 10 8 12 6 VGS 3 Qgs 2 0 tf tr 10 td(on) 1 10 4 ID = −3 A TJ = 25°C 0 2 4 6 8 10 12 2 0 14 Qg, TOTAL GATE CHARGE (nC) Figure 10. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = 0 V TJ = 25°C 1 TJ = −55°C TJ = 150°C 0.1 0.01 100 6 Qgd 1 −IS, SOURCE CURRENT (A) td(off) 100 0 0.2 0.4 0.6 0.8 1.0 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current 100 −ID, DRAIN CURRENT (A) t, TIME (ns) 8 10 VDD = −12 V ID = −3.0 A VGS = −4.5 V 10 QT 4 Figure 9. Capacitance Variation 1 VDS 5 −VGS −VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) 1,000 12 Single Pulse TC = 25°C 10 Mounted on 2″ sq. FR4 board (0.5″ sq. 2 oz. Cu single sided) with MOSFET die operating. 100 ms 1 ms 10 ms 1 RDS(on) Limit Thermal Limit Package Limit 0.1 0.01 0.1 1 dc 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 2800 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS − 12V, P−CHANNEL MOSFETS (MOSFET1 − CHARGING) 100 NUS6189MN TYPICAL CHARACTERISTICS − 12V, P−CHANNEL MOSFETS (MOSFET1 − CHARGING) RqJA, EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 Single Pulse 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 t, TIME (s) Figure 14. FET Thermal Response http://onsemi.com 9 1E+00 1E+01 1E+02 1E+03 NUS6189MN TYPICAL CHARACTERISTICS − SINGLE PNP TRANSISTOR (BJT − CHARGING) 0.35 VCE(sat) = 150°C IC/IB = 10 VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) 0.25 0.2 25°C 0.15 −55°C 0.1 0.05 0 0.001 0.01 0.1 1.0 0.25 −55°C 0.15 0.1 0.05 10 0 0.001 0.01 25°C (5.0 V) 25°C (2.0 V) −55°C (5.0 V) −55°C (2.0 V) 1.0 VBE(on), BASE EMITTER TURN−ON VOLTAGE (V) VBE(sat), BASE EMITTER SATURATION VOLTAGE (V) 150°C (2.0 V) 0.9 1.0 0.9 −55°C 0.8 25°C 0.7 0.6 0.5 150°C 0.4 0.001 0.01 0.1 1.0 10 IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 17. DC Current Gain vs. Collector Current Figure 18. Base Emitter Saturation Voltage vs. Collector Current 1.0 VCE = −2.0 V −55°C 0.8 0.7 25°C 0.6 0.5 150°C 0.4 0.3 0.2 0.1 10 IC/IB = 10 1.0 0.3 10 VCE, COLLECTOR−EMITTER VOLTAGE (V) hFE, DC CURRENT GAIN 1.1 0.1 1.0 Figure 16. Collector Emitter Saturation Voltage vs. Collector Current 150°C (5.0 V) 0.01 0.1 IC, COLLECTOR CURRENT (A) Figure 15. Collector Emitter Saturation Voltage vs. Collector Current 0.001 25°C 0.2 IC, COLLECTOR CURRENT (A) 800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 VCE(sat) = 150°C IC/IB = 100 0.3 0.001 0.01 0.1 1.0 10 10 mA 0.8 VCE (V) IC = 500 mA 100 mA 300 mA 0.6 0.4 0.2 0 0.01 IC, COLLECTOR CURRENT (A) 0.1 1.0 10 IB, BASE CURRENT (mA) Figure 19. Base Emitter Turn−On Voltage vs. Collector Current Figure 20. Saturation Region http://onsemi.com 10 100 NUS6189MN TYPICAL CHARACTERISTICS − SINGLE PNP TRANSISTOR (BJT − CHARGING) Cobo, OUTPUT CAPACITANCE (pF) 170 Cibo (pF) 325 300 275 250 225 200 175 150 125 0 1.0 2.0 3.0 4.0 5.0 Cobo (pF) 150 130 110 90 70 50 6.0 0 2.0 4.0 6.0 8.0 10 12 VEB, EMITTER BASE VOLTAGE (V) VCB, COLLECTOR BASE VOLTAGE (V) Figure 21. Input Capacitance Figure 22. Output Capacitance 10 1 ms 1.0 IC (A) Cibo, INPUT CAPACITANCE (pF) 350 10 ms 100 ms 0.1 1s Thermal Limit 0.01 0.01 0.1 1.0 10 VCE (Vdc) Figure 23. Safe Operating Area http://onsemi.com 11 100 14 16 NUS6189MN TYPICAL PERFORMANCE CURVES − OVERVOLTAGE PROTECTION IC (TA= 25°C, unless otherwise specified) 7.05 1.0 7.00 0.9 I supply (mA) 6.90 6.85 0.8 0.7 6.80 0.6 6.75 6.70 −40 −25 −10 5 20 35 50 65 80 95 0.5 −40 −25 −10 5 20 Figure 24. Typical Vth Threshold Variation vs. Temperature 90 80 70 60 50 40 30 20 10 10 50 65 80 95 Figure 25. Typical Supply Current vs. Temperature Icc ) Iin, VCC + 6 V 100 0 35 Temperature (°C) Ambient Temperature (°C) IDpk, AMPS (A) Voltage (V) 6.95 100 1000 10000 PULSE WIDTH (ms) Figure 26. Typical Maximum Drain Peak Current vs Pulse Width (Non−repetitive Single Pulse, VGS = 10 V, TA = 255C) http://onsemi.com 12 NUS6189MN TYPICAL PERFORMANCE CURVES − 30V, P−CHANNEL MOSFET (MOSFET2 − OVP) −ID, DRAIN CURRENT (AMPS) 12 −4.5 V −4.2 V −10V 11 10 9 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) (TA= 25°C, unless otherwise specified) −4 V −8 V −6 V 8 7 −3.8 V −5.5 V −5 V 6 −3.6 V 5 4 3 −3.4 V −3.2 V 2 1 0 −3 V TJ = 25°C 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C ID = −3.7 A 0.2 0.1 0 2 7 8 9 10 10 −IS, SOURCE CURRENT (AMPS) −IDSS, LEAKAGE CURRENT (nA) 6 Figure 28. On−Resistance vs. Gate−to−Source Voltage VGS = 0 V TJ = 150°C 10000 1000 TJ = 100°C 100 5 5 −VGS, GATE VOLTAGE (VOLTS) Figure 27. On−Region Characteristics 100000 4 3 25 10 15 20 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 VGS = 0 V TJ = 150°C 1 TJ = 100°C TJ = 25°C 0.1 0.3 TJ = −55°C 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 30. Diode Forward Voltage vs. Current Figure 29. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 13 1.1 NUS6189MN PACKAGE DIMENSIONS QFN22, 3x4, 0.5P CASE 485AT−01 ISSUE B D PIN 1 REFERENCE 2X L A B ÈÈÈ ÈÈÈ ÈÈÈ ÈÈÈ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. L1 DETAIL A OPTIONAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu 0.15 C 2X MOLD CMPD DETAIL B 0.15 C L A3 ÉÉÉ ÇÇÇ ÇÇÇ A1 OPTIONAL CONSTRUCTIONS TOP VIEW DETAIL B 0.10 C A 25X 0.08 C NOTE 4 A3 SIDE VIEW C A1 SEATING PLANE SOLDERING FOOTPRINT* G1 D3 22X D4 7 DETAIL A 3.30 1.55 L 0.50 PITCH 12 G G E3 E2 K 0.925 PACKAGE OUTLINE 1 E4 22X b 1 1.47 1.21 1.47 1.47 1.58 4.30 0.10 C A B 0.05 C 16X MILLIMETERS DIM MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.025 0.05 A3 0.20 REF b 0.20 0.25 0.30 D 3.00 BSC D2 1.45 1.50 1.55 D3 0.52 0.57 0.62 D4 1.02 1.07 1.12 E 4.00 BSC E2 1.05 1.10 1.15 E3 1.30 1.35 1.40 E4 1.40 1.45 1.50 e 0.50 BSC −−− K 0.25 −−− 0.35 L 0.30 0.325 L1 −−− −−− 0.15 G 1.35 1.40 1.50 G1 0.95 1.05 1.15 G2 0.855 0.885 0.915 NOTE 3 18 e G2 D2 22X BOTTOM VIEW 0.39 0.52 22X 0.30 1.14 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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