TFDU5103 VISHAY Vishay Semiconductors Fast Infrared Transceiver Module (MIR, 1.152 Mbit/s) for 2.7 V to 5.5 V Operation Description The TFDU5103 is a low-power infrared transceiver module compliant to the latest IrDA physical layer standard for fast infrared data communication, supporting IrDA speeds up to 1.152 Mbit/s (MIR), and carrier based remote control modes up to 2 MHz. The transceiver module consists of a PIN photodiode, an infrared emitter (IRED), and a low-power CMOS control IC to provide a total front-end solution in a single package. Vishay MIR transceivers are available in different package options, including this BabyFace package (TFDU5103). This wide selection provides flexibility for a variety of applications and space constraints. The transceivers are capable of directly interfacing with a wide variety of I/O devices which perform the modulation/ demodulation function, including National Semiconductor’s PC87338, PC87108 and PC87109, SMC’s FDC37C669, FDC37N769 and CAM35C44, and Hitachi’s SH3. At a minimum, a VCC bypass capacitor is the only external component required implementing a complete solution. TFDU5103 has a tri-state output and is floating in shutdown mode with a weak pull-up. Features • Supply voltage 2.7 V to 5.5 V, Operating idle current (receive mode) < 3 mA, Shutdown current < 5 µA over full temperature range • Surface Mount Package, top and side view, L 9.7 mm x W 4.7 mm x H 4.0 mm • Operating Temperature - 25 °C to 85 °C • Storage Temperature - 40 °C to 100 °C • Transmitter Wavelength typ. 886 nm, supporting IrDA® and Remote Control 18102 • IrDA® compliant, link distance (MIR) > 1 m, ± 15 °, window losses are allowed to still be inside the IrDA® spec. • Remote Control Range > 8 m, 22 m • ESD > 4000 V (HBM), Latchup > 200 mA • EMI immunity > 550 V/m for GSM frequency and other mobile telephone bands / (700 MHz to 2000 MHz, no external shield) • Split power supply, LED can be driven by a separate power supply not loading the regulated supply. U.S. Pat. No. 6,157,476 • Tri-state-Receiver Output, floating in shut down with a weak pull-up • Eye safety class 1 (IEC60825-1, ed. 2001), limited LED on-time, LED current is controlled, no single fault to be considered Applications • Notebook Computers, Desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs • Digital Still and Video Cameras • Printers, Fax Machines, Photocopiers, Screen Projectors • Telecommunication Products Parts Table Part Description Qty / Reel TFDU5103-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU5103-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs Document Number 82618 Rev. 1.2, 24-Jun-04 www.vishay.com 1 TFDU5103 VISHAY Vishay Semiconductors Block Diagram Tri-State Driver Amplifier Rxd Comparator Vcc2 Logic & Mode SD Controlled Driver Control Txd Vcc1 GND 18189 Pin Description Pin Number Function Description 1 VCC2 IRED Anode Connect IRED anode directly to VCC2. For voltages higher than 3.6 V an external resistor might be necessary for reducing the internal power dissipation.An unregulated separate power supply can be used at this pin. 2 IRED Cathode IRED cathode, internally connected to driver transistor 3 Txd 4 5 Active This input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the Txd pin is asserted for longer than 80 µs. When used in conjunction with the SD pin, this pin is also used to receiver speed mode. I HIGH Rxd Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 kΩ (typ.) in shutdown mode. O LOW SD Shutdown, also used for dynamic mode switching. Setting this pin active places the module into shutdown mode. On the falling edge of this signal, the state of the Txd pin is sampled and used to set receiver low bandwidth (Txd = Low, SIR) or high bandwidth (Txd = High, MIR and FIR) mode. Will be overwritten by the mode pin input, which must float, when dynamic programming is used. I HIGH 6 VCC1 Supply Voltage 7 Mode HIGH: High speed mode, MIR and FIR; LOW: Low speed mode, SIR only (see chapter "Mode Switching"). I Mode Output function: The mode pin can also be used to indicate the dynamically programmed mode. The maximum load is limited to 50 pF. High indicates MIR-, low indicates SIR-mode O GND Ground 8 www.vishay.com 2 I/O Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors Pinout TFDU5103 weight 200 mg "U" Option BabyFace (Universal) IRED Definitions: In the Vishay transceiver data sheets the following nomenclature is Detector used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s 1 2 3 4 5 6 FIR: 4 Mbit/s 7 8 VFIR: 16 Mbit/s 17087 MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. Absolute Maximum Ratings Reference point Ground (Pin 8): unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 +6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 + 6.5 V Input currents for all pins, except IRED anode pin 10 mA Output sinking current Power dissipation see derating curve, figure 5 Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature < 90 µs, ton < 20 % IRED anode voltage Voltage at all inputs and outputs Vin > VCC1 is allowed Load at mode pin when used as mode indicator Document Number 82618 Rev. 1.2, 24-Jun-04 25 mA 500 mW 125 °C Tamb - 25 + 85 °C Tstg - 25 + 85 °C 240 °C IIRED (DC) 125 mA IIRED (RP) 600 mA + 6.5 V see recommended solder profile (see figure 4) Average output current Repetitive pulse output current PD Typ. VIREDA VIN - 0.5 5.5 V 50 pF www.vishay.com 3 TFDU5103 VISHAY Vishay Semiconductors Eye safety information Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Typ. Virtual source size Parameter Method: (1 - 1/e) encircled energy d 2.5 2.8 Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie *)Due Test Conditions Max Unit mm *) (500)**) mW/sr to the internal limitation measures the device is a "class1" device **) IrDA specifies the max. intensity with 500 mW/sr www.vishay.com 4 Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC 2.7 Typ. Max Unit 5.5 V SD = Low, Ee = 0 klx ICC 2 3 mA Dynamic supply current (Idle)1) SD = Low, Ee = 1 klx2) ICC 2 3 mA Shutdown supply current SD = High, Mode = Floating Ee = 0 klx ISD 2.0 µA SD = High, Mode = Floating ISD 2.5 µA ISD 5 µA + 85 °C Dynamic supply current (Idle) 1) Ee = 1 klx2) SD = High, T = 85 °C, Mode = Floating, not ambient light sensitive Operating temperature range TA - 25 Output voltage low IOL = 1 mA, Cload = 15 pF VOL Output voltage high IOH = 500 µA, Cload = 15 pF VOH 0.8 x VCC 0.4 V V IOH = 250 µA, Cload = 15 pF VOH 0.9 x VCC V Output Rxd current limitation high state Short to Ground 20 mA Output Rxd current limitation low state Short to VCC1 20 mA Rxd to VCC1 impedance SD = High RRxD 400 600 kΩ VIL 0.5 0.5 V CMOS level 3) VIH VCC - 0.5 VCC + 0.5 V TTL level, VCC1 = 4.5 V Input voltage low (Txd, SD, Mode) Input voltage high (TxD, SD, Mode) 500 VIH 2.4 Input leakage current (Txd, SD, Mode) IL - 10 + 10 µA V Input leakage current Mode IICH -2 +2 µA Input capacitance (TxD, SD, Mode) CIN 5 pF 1) Receive mode only. In transmit mode, add additional 85 mA (typ) for IRED current. Add Rxd output current depending on Rxd load. 2) Standard Illuminant A 3) The typical threshold level is between 0.5 x VCC/2 (VCC = 3 V) and 0.4 x VCC (V CC = 5.5 V) . It is recommended to use the specified min/ max values to avoid increased operating current. Document Number 82618 Rev. 1.2, 24-Jun-04 www.vishay.com 5 TFDU5103 VISHAY Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Minimum detection threshold irradiance, SIR mode 9.6 kbit/s to 115.2 kbit/s λ = 850 nm to 900 nm Ee Minimum detection threshold irradiance, MIR mode 1.152 Mbit/s λ = 850 nm to 900 nm Ee Maximum detection threshold irradiance λ = 850 nm to 900 nm Ee No detection receiver input irradiance *) Rise time of output signal 10 % to 90 %, 15 pF tr (Rxd) Fall time of output signal 90 % to 10 %, 15 pF Ee Min Typ. Max Unit 25 (2.5) 35 (3.5) mW/m2 65 (6.5) (µW/cm 2) mW/m2 (µW/cm 2) 5 (500) kW/m2 (mW/cm2) 4 (0.4) mW/m2 (µW/cm 2) 10 40 ns tf (Rxd) 10 40 ns Rxd pulse width of output signal, input pulse length 50 % SIR mode 1.4 µs < PWopt < 25 µs tPW 1.5 1.8 2.1 µs Rxd pulse width of output signal, input pulse length 50 % MIR mode PWopt = 217 ns, 1.152 kbit/s tPW 110 250 270 ns input irradiance = 100 mW/m2, 1.152 Mbit/s 40 ns input irradiance = 100 mW/m2, 576 kbit/s 80 ns input irradiance = 100 mW/m2, ≤ 115.2 kbit/s 350 ns after completion of shutdown programming sequence Power on delay 500 µs 300 µs Stochastic jitter, leading edge Receiver start up time Latency tL 170 Note: All timing data measured with 1.152 Mbit/s are measured using the IrDA® MIR transmission header. *) This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps www.vishay.com 6 Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions Symbol Min Typ. Max Unit See derating curve. For 3.3 V operation no external resistor needed. For 5 V application that might be necessary depending on operating temperature range. ID 500 550 600 mA 1 µA 170 350 mW/sr 0.04 mW/sr IIRED -1 Output radiant intensity recommended appl. circuit α = 0 °, 15 ° Txd = High, SD = Low, VCC1 = VCC1 = 3.3 V Internally current-controlled, no external resistor Ie 120 Output radiant intensity VCC1 = 5.0 V, α = 0 °, 15 ° Txd = Low or SD = High, (Receiver is inactive as long as SD = High) Ie Output leakage IRED current α Output radiant intensity, angle of half intensity Peak - emission wavelength λp Spectral bandwidth ∆λ 880 ° 900 40 tropt, tfopt 10 input pulse width 217 ns, 1.152 kbit/s topt 207 input pulse width topt Optical rise time, fall time Optical output pulse duration ± 24 217 nm nm 40 ns 227 ns µs tTxd 0.1 µs < tTxd < 80 µs *) input pulse width tTxd ≥ 80 µs *) Optical overshoot topt 20 85 µs 25 % *) Typically the output pulse duration will follow the input pulse duration t and will be identical in length t. However, at pulse durations larger than 80 µs the optical output pulse durations is limited to 85 µs. This pulse duration limitation can already start at 20 µs Document Number 82618 Rev. 1.2, 24-Jun-04 www.vishay.com 7 TFDU5103 VISHAY Vishay Semiconductors Recommended Circuit Diagram Vishay Semiconductors transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (Txd, SD, Mode) and the output Rxd should be directly (DC) coupled to the I/O circuit. ˇΩ Test circuit Input Signal - total pulse duration - duty factor tp(tot) = δ = 0.00 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and reduces the influence of the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is only necessary for higher operating voltages and elevated temperatures, see derating curve in figure 7, to avoid too high internal power dissipation. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltage VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as near as possible to the transceiver power supply pins. An Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not apply to follow the fast current is rise time. In that case another 4.7 µF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" by Paul Horowitz and Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Recommended Application Circuit Components Component Recommended Value C1 4.7 µF, 16 V 293D 475X9 016B C2 0.1 µF, Ceramic VJ 1206 Y 104 J XXMT R1 5 V supply voltage: 2 Ω , 0.25 W ( recommended using two 1 Ω, 0.125 W resistor in series) 3.3 V supply voltage: no resistor necessary, the internal controller is able to control the current e.g. 2 x CRCW-1206-1R0-F-RT1 R2 47 Ω, 0.125 W CRCW-1206-47R0-F-RT1 www.vishay.com 8 Vishay Part Number Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Mode Switching The TFDU5103 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the Txd and SD inputs as described below or selected by setting the Mode Pin. The Mode Pin can be used to statically set the mode (Mode Pin: LOW: SIR, HIGH: 0.576 Mbit/s to 1.152 Mbit/s). If not used or in standby mode, the mode input should float or should not be loaded with more than 50 pF. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. After that Txd is enabled as normal Txd input and the transceiver is set for the high bandwidth (576 kbit/s to 1.152 kbit/s) mode. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set Txd input to logic "LOW". Wait ts ≥ 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of Txd, which determines speed setting). 4. Txd must be held for th ≥ 200 ns. After that Txd is enabled as normal Txd input and the transceiver is set for the lower bandwidth (9.6 kbit/s to 115.2 kbit/s) mode. 50% SD/Mode ts th High : FIR Txd 50% 50% Low : SIR Setting to the High Bandwidth Mode (0.576 Mbit/s to 1.152 Mbit/s) 1. Set SD input to logic "HIGH". 2. Set Txd input to logic "HIGH". Wait ts ≥ 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of Txd, which determines speed setting). 4. After waiting th ≥ 200 ns Txd can be set to logic "LOW". The hold time of Txd is limited by the maximum allowed pulse length. 14873 Figure 2. Mode Switching Timing Diagram Table 2. Truth table Inputs Outputs SD Txd Optical input Irradiance mW/m2 Rxd Transmitter high x x weakly pulled (500 kΩ) to VCC1 0 low high x low (active) Ie high > 80 µs x high 0 low <4 high 0 low > Min. Detection Threshold Irradiance < Max. Detection Threshold Irradiance low (active) 0 low > Max. Detection Threshold Irradiance x 0 Document Number 82618 Rev. 1.2, 24-Jun-04 www.vishay.com 9 TFDU5103 VISHAY Vishay Semiconductors Recommended Solder Profile Lead-Free, Recommended Solder Profile Solder Profile for Sn/Pb soldering The TFDU5103 is a lead-free transceiver and qualified for lead-free processing. For lead-free solder paste like Sn(3.0 - 4.0)Ag(0.5 - 0.9)Cu, there are two standard reflow profiles: Ramp-Soak-Spike (RSS) and Ramp-To-Spike (RTS). The Ramp-Soak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. Shown below in figure 4 is Vishay’s recommended profile for use with the TFDU5103 transceivers. For more details please refer to Application note: SMD Assembly Instruction. 240 10 s max. @ 230°C 220 Temperature (°C) 200 2°C - 4°C/s 180 160 140 120 120 s - 180 s 100 90 s max 80 60 2°C - 4°C/s 40 20 0 0 14874 50 100 150 200 250 300 350 Time ( s ) Figure 3. Recommended Solder Profile 280 260 T = 250°C for 20 s max Temperature/ °C 240 220 Tpeak = 260°C max. T = 217°C for 50 s max 200 180 160 20 s max. 140 120 90 s...120 s 2°C...4°C/s 100 50 s max. 2°C...4°C/s 80 60 40 20 0 0 19048 50 100 150 200 250 300 350 Time/s Figure 4. Solder Profile, RSS Recommendation www.vishay.com 10 Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors Current Derating Diagram Figure 5 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 Ω is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. Ambient Temperature ( °C) 90 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] @ duty cycle 20% Figure 5. Temperature Derating Diagram Document Number 82618 Rev. 1.2, 24-Jun-04 www.vishay.com 11 TFDU5103 VISHAY Vishay Semiconductors Package Dimensions in mm 7x1=7 0.6 2.5 1 8 1 www.vishay.com 12 18470 Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors Reel Dimensions W1 Reel Hub W2 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 Document Number 82618 Rev. 1.2, 24-Jun-04 W3 max. www.vishay.com 13 TFDU5103 VISHAY Vishay Semiconductors Tape Dimensions in mm 18269 www.vishay.com 14 Document Number 82618 Rev. 1.2, 24-Jun-04 TFDU5103 VISHAY Vishay Semiconductors 18283 Document Number 82618 Rev. 1.2, 24-Jun-04 www.vishay.com 15 TFDU5103 VISHAY Vishay Semiconductors Ozone Depleting Substances Policy Statement It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423 www.vishay.com 16 Document Number 82618 Rev. 1.2, 24-Jun-04