TFBS5607 Vishay Semiconductors Integrated Low Profile Transceiver Module for Telekom Applications 9.6 kbit/s to 1.152 Mbit/s Data Transmission Rate Description The miniaturized TFBS5607 is an ideal transceiver for applications in telecommunications like mobile phones, pagers, and PDAs of all kinds. The devices are both designed for optimum performance and minimum package size. The new features These devices cover the latest IrDA physical layer for Low Power SIR and MIR 1.152 Mbit/s IrDA mode. The device covers the supply voltage range from 5.5 V down to 2.7 V and with its low current consumption it is optimum suited for battery powered applications. Double eye safety protection by pulse duration and current limitation is integrated. The device is defined to operate over an extended low power IrDA range close to 1 m. A custom modification of current control for MIR low power standard is available on request. The transceivers is in a very low profile package, allowing to replace and upgrade a variety of common SIR devices to MIR functionality with the additional feature of variable logic voltage swing. The TFBS5607 is using the Vishay Semiconductors, IBM and Infineon order of the pinning. The devices are modifications of the TFDU5107 devices. An additional new feature as in TFDU5107 is the adjustable logic voltage Vddlogic swing. It can be set externally between 1.5 V and 5.5 V. Features Package: TFBS5607 Vishay Legacy Pinning Order Compatible to IrDA Low Power Standard (MIR and SIR with Lowest Current Consumption) Wide Supply Voltage Range (2.7 V to 5.5 V) Lowest Power Consumption, typically 500 µA (900 µA max.) in Receive Mode, <1 µA in Shutdown Mode Fewest External Components Logic Input and Output Voltage 1.5 V to 5.5 V Vishay’s well known High EMI Immunity Tri – State – Receiver Output with weak pull-up efficient in shut down mode Eye Safety Protection Integrated Applications Mobile Phones, Pagers, Hand–held Battery Operated Equipment Digital Still and Video Cameras Computers (WinCE, PalmPC, PDAs) Medical and Industrial Data Collection Document Number 82553 Rev. A1.3, 17-Jul-02 Extended IR Adapters www.vishay.com 1 (14) TFBS5607 Vishay Semiconductors Packages TFBS5607 Ordering Information Part Number Qty / Reel TFBS5607–TR3 2500 pcs Description Functional Block Diagram Vdd1 Vlogic Driver Amplifier SD Comparator Rxd IRED Anode AGC Logic Current controlled driver Txd IRED Cathode Mode GND Figure 1. Functional Block Diagram (mode input is for internal current selection of customized version for low power or full IrDA range) Definitions : In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR 576 kbit/s to 1152 kbit/s FIR 4 Mbit/s VFIR 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any obsoletes the former version. www.vishay.com 2 (14) Document Number 82553 Rev. A1.3, 17-Jul-02 TFBS5607 Vishay Semiconductors Pin Description Pin Function Description I/O Active TFBS560 7 1 IRED Anode IRED Anode to be externally connected to VCC through a current control resistor. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled VCC supply. 2 IRED Cathode 3 Txd Transmit Data Input I HIGH 4 Rxd Received Data Output, push–pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull–up or pull–down resistor is required. Pin is connected to Vlogic with a weak pull-up (500 kΩ) when device is in shutdown mode. Rxd output is quiet during transmission. O LOW 5 SD Shutdown, will switch the device into shutdown after a delay of 1 ms I HIGH 6 Vdd Supply Voltage 7 Vlogic Defines the input and output logic swing voltage 8 GND Ground IRED Cathode, internally connected to driver transistor I TFBS5607 1 Pin order: IREDA IRED C Txd Rxd SD Vdd Vlogic GND Figure 2. Pinning Document Number 82553 Rev. A1.3, 17-Jul-02 www.vishay.com 3 (14) TFBS5607 Vishay Semiconductors Absolute Maximum Ratings Reference Point Ground, Pin 8, unless otherwise noted Parameters Supplyy Voltage g Range g Input Current Output Sink Current, Rxd Rep. Pulsed IRED Current Test Conditions Symbol Min. 0 V < Vdd2 < 6 V 0 V < Vdd1 < 6 V 0 V < Vdd1 < 6 V 0 V < Vdd2 < 6 V all pins (IRED Anode excluded) Rxd IRED Anode, ton< 20%, < 20 µs Vdd1 Vdd2 Vlogic –0.5 –0.5 –0.5 Average IRED Current Power Dissipation Junction Temperature Ambient Temperature Range (Operating) Storage Temperature Range Soldering Temperature t = 20 s @215°C Transmitter Data and 2.7 V < Vdd1 < 5.5 V Shutdown Input Voltage Receiver Data Output Voltage Virtual source size Method: (1–1/e) encircled energy Max. Intensity for Class 1 EN60825, 1.1.2001 operation of IEC 60825 or Worst case IrDA pulse EN60825 pattern, lab. conditions. *) Typ. Max. Unit 6 6 6 V V V 10 mA IIRED(RP) 25 500 mA mA IIRED(DC) Ptot TJ Tamb –25 125 450 125 85 mA mW °C °C Tstg –25 85 240 6 °C °C V Vlogic+0.5 V mm 500*) save in all modes mW/sr 215 VTxd, VSD –0.5 VRxd d –0.5 2.5 Ie 2.8 The Jan. 2001 edition of the IEC825–1 or EN60825–1 gives no limitation below the IrDA standard maximum. IrDA max. limit is 500 mW/sr. The device is protected against Txd short by an internal shut–off when the pulse duration is exceeding maximum IrDA specification value of pulse duration. In addition the max. current is limited. www.vishay.com 4 (14) Document Number 82553 Rev. A1.3, 17-Jul-02 TFBS5607 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25°C, Vdd1 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions Symbol Min. Typ. Max. Unit Transceiver Supported Data Rates Rxd pulse duration 400 ns Base band SIR mode 9.6 1152 kbit/s Base band 1.152 Mbit/s 9.6 152 kbit/s Supply Voltage Range specified operation Vdd1 2.4 5.5 V Supply Voltage Vdd2 = 2.4 V to 5.5 V Vdd2 2.4 5.5 V IS 500 900 µA Supply Current shutdown mode Vdd1 = 2.4 V to 5.5 V ISSD 0.1 1 µA Average Supply Current *) Vdd1 = 2.4 V to 5.5 V IS 60 110 mA Supply Current receive mode Vdd1 = 2.4 V to 5.5 V Standard MIR transmit mode above Vdd1 = 3.3 V Ie > 100 mW/sr a serial resistor for reducing the internal power dissipation should be implemented, e.g. RL = 2.7 Ω Logic Voltage Range Vlogic 1.5 5.5 V Shutdown/ Mode clock pulse duration tprog 0.2 20 µs Shutdown delay ”Receive off” tprog 1 1.5 ms Shutdown delay ”Receive on” tprog 40 100 µs Transceiver “Power on“ Settling Time *) Vdd2 = 2.4 V to 5.5 V Time from switching on Vdd1 to established specified operation 50 µs Max. data is for 20% (25%) duty cycle for SIr (MIR) 1.152 Mbit/s low power mode. The typical value is given for the case of normal operation with statistical equal distribution of “0” and “1” states. Document Number 82553 Rev. A1.3, 17-Jul-02 www.vishay.com 5 (14) TFBS5607 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25°C, Vdd1 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions Symbol Min. Typ. Max. Unit Receiver Min. Detection Threshold Irradiance SIR 9.6 kbit/s to 1.152 Mbit/s *) |α| ≤ 15° Vdd1 = 2.4 V to 5.5 V Ee, min 40 80 mW/m 2 Min. Detection Threshold Irradiance SIR 576 kbit/s to 1.152 Mbit/s *) |α| ≤ 15° Vdd1 = 2.4 V to 5.5 V Ee, min 70 150 mW/m 2 Maximum Detection Threshold Irradiance |α| ≤ 90° Vdd1 = 3 V Ee, max |α| ≤ 90° Vdd1 = 5 V Ee, max Logic Low Receiver Input Irradiance Output Voltage Rxd Ee,max,low active 8000 15000 W/m 2 5000 W/m 2 mW/m 2 4 VOL 0.5 0.8 V C = 15 pF, R = 2.2 kΩ non active VOH Vdd1–0.5 V C = 15 pF, R = 2.2 kΩ Output Current Rxd VOL < 0.8 V 4 mA Rise Time @Load C = 15 pF 1.5 V ≤ Vlogic < 1.8 V tr 30 ns Fall Time @Load C = 15 pF 1.5 V ≤ Vlogic < 1.8 V tf 30 ns Rise Time @Load: C = 15 pF, R = 2.2 kΩ 1.8 V ≤ Vlogic < 5.5 V tr 20 25 70 ns Fall Time @Load: C = 15 pF, R = 2.2 kΩ 1.8 V ≤ Vlogic < 5.5 V tf 20 25 70 ns Rxd Signal Electrical Output 1.5 V ≤ Vlogic < 5.5 V Pulse Width tp 250 400 550 ns Latency tL 50 200 µs *) MIR mode Rxd output pulse duration 400 ns www.vishay.com 6 (14) Document Number 82553 Rev. A1.3, 17-Jul-02 TFBS5607 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25 °C, Vdd1 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions Symbol Min. Typ. Max. Unit Transmitter Logic CMOS High/Low Decision Threshold VIL(Txd) Logic Low Transmitter Input Voltage VIL(Txd) 0 0.2 x Vlogic V VIH(Txd) 0.8 x Vlogic Vlogic + 0.5 V Ie 40 Logic High Transmitter Input Voltage 1.5 V < Vlogic < 5.5 V Output Radiant Intensity, |α| ≤ 15° Vdd2 = 3 V Controlled IRED drive peak current *) Vdd1 = 2.7 V to 5.5 V 1/2 x Vlogic IIRED V 90 mW/ sr 450 mA Maximum Output Pulse width (eye safety protection) PWI > 23 µs PWOmin 23 80 µs Optical Pulse width PWI > 1.6 µs PWO 1.45 1.75 µs PWI > 217 ns PWO 210 226 ns 40 ns 850 900 nm Optical Rise/Falltime tr, tf Peak Wavelength of Emission λp Spectral Optical Radiation Bandwidth ∆λ Output Radiant Intensity Txd logic low level Ie Overshoot, Optical Rising Edge Peak to Peak Jitter *) tj 40 nm 0.04 µW/sr 25 % 0.2 µs The current through the IRED can be reduced and defined by an external resistor, the internal current limitation is set to 450 mA peak, nominal. For operating above VIRED = 4 V an external resistor is to be used for internal power dissipation reduction Document Number 82553 Rev. A1.3, 17-Jul-02 www.vishay.com 7 (14) TFBS5607 Vishay Semiconductors Identification The identification of the device can be recalled by setting the SD active followed by activating Txd for a short period. With the low going edge of Txd a single pulse is generated at Rxd. The SD is indendet to activate the shutdown function after a delay of 1 ms. Therefore the full sequence should be run with that 1 ms time limitation, see drawing. tSD: > 5 s for “real” shutdown > 1 ms SD tTxd: > 0.5 s to 2 s Txd tdelTxd: ≥ 1 s tdelRxd: ≥ 10 ns Rxd tRxd = 400 ns Figure 3. Timing for self identification Current Derating Diagram Recommended Solder Profile Peak Operating Current ( mA ) 600 240 210 Temperature ( °C ) 500 400 300 200 10 s max. @ 230°C Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25%. 2 - 4°C/s 180 150 120 120 - 180 s 90 60 100 90 s max. 2 - 4°C/s 30 0 –40 –20 0 14875 0 20 40 60 80 100 120 140 Temperature ( °C ) Figure 4. Current Derating as a Function of Ambient Temperature and Duty Cycle, see Absolute Maximum Ratings 0 50 100 14874 150 200 250 Time ( s ) 300 350 Figure 5. Recommended Solder Profile Vlogic Setting The logic voltage swing is set by applying an external voltage to the Vlogic pin. Table 1. Truth table Inputs Outputs SD Txd Optical input Irradiance mW/ m2 Rxd LED drive current resulting intensity Ie in mW/ sr high < 1 ms pulse x low going Txd triggers monostable to edit a 400 ns (nominal) low pulse 0 high > 1 ms x x floating (500 kΩ to Vdd) 0 low high x high > 40 low high > 80 µs x high 0 low low <4 high 0 low low ≥ 40 low, edge triggered pulse of 400 ns durating 0 www.vishay.com 8 (14) Document Number 82553 Rev. A1.3, 17-Jul-02 TFBS5607 Vishay Semiconductors TFBS5607 (Mechanical Dimensions) Dimensions in mm Document Number 82553 Rev. A1.3, 17-Jul-02 16503 www.vishay.com 9 (14) TFBS5607 Vishay Semiconductors Pad Layout The leads of the device should be soldered in the center position of the pads. 1.35 Mounting center Shield solder pad 1.25 0.1 2.05 0.6 1.75 Fiducial 0.95 7 x 0.95 = 6.65 Unit: mm 15250 Figure 6. Recommended Land Pattern 8.2 0.2 3.2 2.6 Solder Mask 16505 Figure 7. Adjacent Land Keep–out and Solder Mask Areas www.vishay.com 10 (14) Document Number 82553 Rev. A1.3, 17-Jul-02 TFBS5607 Vishay Semiconductors Tape and Reel Dimensions 16525 Trailer no devices Leader devices no devices End Start min. 200 min. 400 96 11818 A N W1 Reel Hub W2 Version B Document Number 82553 Rev. A1.3, 17-Jul-02 Tape Width 16 A 330 ± 1 16515 N 60 + 2.5 W1 16.4 + 2 W2 max 22.4 www.vishay.com 11 (14) TFBS5607 Vishay Semiconductors Appendix Application Hints Shut Down Recommended Circuit Diagram TFBS5607 To shut down the TFBS5600 into a standby mode the SD pin has to be set active. After a delay of < 1 ms it will switch to the standby mode. The TFBS5607 doesn’t need any external components when operated at a ”clean” power supply. In a more noisy ambient it is recommended to add a combination of a resistor and capacitor (R1, C1, C2) for noise suppression as shown in the figure below. A combination of a electrolytic for the low frequency range and a ceramic capacitor for suppressing the high frequency disturbance will be most effective. The capacitor C3 is only necessary when inductive wiring is used or the power supply cannot deliver the operating peak pulse current. However, a low impedance layout is the better and more cost efficient solution. The inputs TXD and SD are high impedance CMOS inputs. Therefore, the lines from the I/O to those inputs should be carefully designed not to pick up ambient noise. If long lines are used, loads at the Txd input of the TFBS5607 and at the Rxd input of the controller (!) are recommended. At the IRED Anode voltage supply line an additional capacitor might be necessary when inductive wiring is used. For adjusting the intensity depending on the application, a serial resistor in the Vcc2 supply to the IRED Anode pin can be used. Latency The receiver is in specified conditions after the defined latency. In a UART related application after that time (typically 50 µs) the receiver buffer of the UART must be cleared. Therefore, the transceiver has to wait at least the specified latency after receiving the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state. C1, (C3): 4.7 µF, see text C2: 470 nF R1 VCC1 C1 TFBS5607 C2 6 Vdd1 8 GND 4 Rxd VCC2 1 Vdd2, IRED Anode Txd 3 Txd SD 5 SD Vlog 7 Vlogic GND Rxd C3 Figure 8. Recommended Application Circuit Table 2. Recommended Application Circuit Components Component Recommended Value C1, C3 4.7 F, 16 V C2 0.47 µF, Ceramic R1 47 Ω, 0.125 W www.vishay.com 12 (14) Vishay Part Number 293D 475X9 016B 2T VJ 1206 Y 104 J XXMT CRCW–1206–47R0–F–RT1 Document Number 82553 Rev. A1.3, 17-Jul-02 TFBS5607 Vishay Semiconductors Revision History: A1.2, 18/02/2002: Final new revision A1.3, 17/07/2002: Typos corrected, operating voltage range adjusted to 2.7 V to 5.5 V, wavelength range of transmitter adapted to full IrDA range. Document Number 82553 Rev. A1.3, 17-Jul-02 www.vishay.com 13 (14) TFBS5607 Vishay Semiconductors Ozone Depleting Substances Policy Statement It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423 www.vishay.com 14 (14) Document Number 82553 Rev. A1.3, 17-Jul-02 Legal Disclaimer Notice Vishay Notice Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 91000 Revision: 08-Apr-05 www.vishay.com 1