NLX1G125 Non-Inverting 3-State Buffer The NLX1G125 is an advanced high−speed 2−input CMOS non−inverting 3−state buffer in ultra−small footprint. The NLX1G125 input structures provide protection when voltages up to 7.0 V are applied, regardless of the supply voltage. http://onsemi.com Features • • • • • • • • High Speed: tPD = 2.7 ns (Typ) @ VCC = 5.0 V Designed for 1.65 V to 5.5 V VCC Operation Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C 24 mA Balanced Output Source and Sink Capability Balanced Propagation Delays Overvoltage Tolerant (OVT) Input Pins Ultra−Small Packages These are Pb−Free Devices OE 1 IN A 2 5 MARKING DIAGRAM XXXX AYWW 5 PIN FLIP−CHIP CASE 499BG A1 XXXX A Y WW VCC = Specific Device Code = Assembly Location = Year = Work Week PIN ASSIGNMENT 1 GND 3 4 OUT Y OE 2 IN A 3 GND 4 OUT Y 5 VCC Figure 1. Pinout (Top View) FUNCTION TABLE OE EN IN A OUT Y A Input OE Input Y Output L H X L L H L H Z X = Don’t Care Figure 2. Logic Symbol ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. P0 1 Publication Order Number: NLX1G125/D NLX1G125 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage −0.5 to )7.0 V VIN DC Input Voltage −0.5 to )7.0 V DC Output Voltage −0.5 to )7.0 V VIN < GND −50 mA VOUT < GND −50 mA VOUT Parameter IIK DC Input Diode Current IOK DC Output Diode Current IOUT DC Output Sink Current $50 mA ICC DC Supply Current per Supply Pin $100 mA ±100 mA −65 to )150 °C IGND TSTG DC Ground Current per Ground Pin Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds TBD °C TJ Junction Temperature Under Bias TBD °C qJA Thermal Resistance (Note 1) TBD °C/W PD Power Dissipation in Still Air at 85°C TBD mW MSL Moisture Sensitivity FR Flammability Rating VESD ILATCHUP Level 1 Oxygen Index: 28 to 34 ESD Withstand Voltage UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Latchup Performance Above VCC and Below GND at 125 °C (Note 5) u2000 u200 N/A V ±500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA / JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Max Unit 1.65 1.5 5.5 5.5 V VCC Positive DC Supply Voltage VIN Digital Input Voltage (Note 6) 0 5.5 V Output Voltage 0 5.5 V −55 +125 °C 0 0 0 0 20 20 10 5.0 ns/V VOUT TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate Operating Data Retention Only Min VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V 6. Unused inputs may not be left open. All inputs must be tied to a high or low−logic input voltage level. http://onsemi.com 2 NLX1G125 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VIH Low−Level Input Voltage VIL VOH VOL Conditions Low−Level Input Voltage High− Level Output Voltage Low−Level Output Voltage VIN = VIH or VIL IOH = −100 mA VIN = VIH or VIL IOH = −4 mA IOH = −8 mA IOH = −12 mA IOH = −16 mA IOH = −24 mA IOH = −32 mA VIN = VIH or VIL IOL = 100 mA TA = 25 5C TA = −555C to +1255C VCC (V) Min 1.65 0.75 x VCC 0.75 x VCC 2.3 to 5.5 0.70 x VCC 0.70 x VCC Typ Max Min Max V 1.65 0.25 x VCC 0.25 x VCC 2.3 − 5.5 0.30 x VCC 0.30 x VCC 1.65 − 5.5 VCC−0.1 VCC VCC−0.1 1.65 2.3 2.7 3.0 3.0 4.5 1.29 1.9 2.2 2.4 2.3 3.8 1.52 2.15 2.4 2.8 2.68 4.2 1.29 1.9 2.2 2.4 2.3 3.8 1.65 − 5.5 VIN = VIH or VIL IOH = 4 mA IOH = 8 mA IOH = 12 mA IOH = 16 mA IOH = 24 mA IOH = 32 mA 1.65 2.3 2.7 3.0 3.0 4.5 0.08 0.1 0.12 0.15 0.22 0.22 Unit V V 0.1 0.1 0.24 0.3 0.4 0.4 0.55 0.55 0.24 0.3 0.4 0.4 0.55 0.55 V IIN Input Leakage Current 0 v VIN v 5.5V 0 to 5.5 ±0.1 ±1.0 mA IOZ 3−State Output Leakage Current VIN = VIH or VIL 0vVOUTv5.5V 0 ±0.5 ±5.0 mA IOFF Power−Off Output Leakage Current VIN = 5.5 V 0 1.0 10 mA ICC Quiescent Supply Current 0 v VIN v VCC 5.5 1.0 10 mA http://onsemi.com 3 NLX1G125 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 2.5 ns) Symbol tPLH, tPHL Parameter Propagation Delay, Input to Output (Figures 3 and 4, Table 1) VCC (V) Test Condition Min Typ Max Min Max Unit 1.65−1.95 RL = 1 MW, CL = 15 pF 2.0 6.0 10 2.0 10.5 ns 2.3−2.7 RL = 1 MW, CL = 15 pF 1.0 3.4 7.5 1.0 8.0 3.0−3.6 4.5−5.5 tPZH, tPZL tPHZ, tPLZ CIN Output Enable Time (Figures 5, 6and 7, Table 1) Output Disable Time (Figures 5, 6and 7, Table 1) TA = −555C to +1255C TA = 25 5C 1.65−1.95 RL = 1 MW, CL = 15 pF 0.8 2.5 5.2 0.8 5.5 RL = 500 W, CL = 50 pF 1.2 3.1 5.7 1.2 6.0 RL = 1 MW, CL = 15 pF 0.5 1.8 4.5 0.5 4.8 RL = 500 W, CL = 50 pF 0.8 2.3 5.0 0.8 5.3 RL = 250 W, CL = 50 pF 2.0 7.6 9.5 2.0 10 2.3−2.7 1.8 8.5 1.8 9.0 3.0−3.6 1.2 6.2 1.2 6.5 4.5−5.5 0.8 5.5 0.8 5.8 10 2.0 10.5 1.5 8.0 1.5 8.5 3.0−3.6 0.8 5.7 0.8 6.0 4.5−5.5 0.3 4.7 0.3 5.0 1.65−1.95 2.3−2.7 RL = R1 = 5−0 W, CL = 50 pF 2.0 8.0 ns ns Input Capacitance 5.5 VIN = 0 V or VCC 2.5 pF COUT Output Capacitance 5.5 VIN = 0 V or VCC 2.5 pF CPD Power Dissipation Capacitance (Note 7) 3.3 5.5 10 MHz VIN = 0 V or VCC 9.0 11 pF 7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC. http://onsemi.com 4 NLX1G125 tf = 3 ns tf = 3 ns 90% INPUT A and B OE = GND VCC 90% Vmi INPUT Vmi 10% 10% tPHL OUTPUT CL * GND RL tPLH VOH Vmo OUTPUT Y Vmo *Includes all probe and jig capacitance. A 1 MHz square input wave is recommended for propagation delay tests. VOL Figure 3. Switching Waveform 2 INPUT Figure 4. TPLH or TPHL VCC R1 = 500 W INPUT VCC OUTPUT CL = 50 pF OUTPUT CL = 50 pF RL = 500 W RL = 250 W A 1 MHz square input wave is recommended for propagation delay tests. A 1 MHz square input wave is recommended for propagation delay tests. Figure 5. TPZL or TPL Figure 6. TPZH or TPHZ 2.7 V Vmi Vmi OE 0V tPZH tPHZ VCC VOH − 0.3 V Vmo On ≈0V tPZL tPLZ ≈ 3.0 V Vmo On VOL + 0.3 V GND Figure 7. AC Output Enable and Disable Waveform Table 1. OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns VCC Symbol 3.3 V $ 0.3 V 2.7 V 2.5 V $ 0.2 V Vmi 1.5 V 1.5 V VCC/2 Vmo 1.5 V 1.5 V VCC/2 http://onsemi.com 5 NLX1G125 DEVICE ORDERING INFORMATION Device NLX1G125FCT1G Package Shipping† Flip−Chip 5 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NLX1G125 PACKAGE DIMENSIONS 5 PIN FLIP−CHIP CASE 499BG−01 ISSUE O ÈÈ ÈÈ D PIN A1 REFERENCE 4X A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. E 0.10 C DIM A A1 b D E e TOP VIEW A1 0.10 C MILLIMETERS MIN MAX 0.44 0.50 0.15 0.19 0.21 0.25 0.90 BSC 1.40 BSC 0.50 BSC A 0.05 C C SIDE VIEW SOLDERING FOOTPRINT* SEATING PLANE 0.50 PITCH 0.50 PITCH e/2 5X b 0.05 C A B 0.03 C e A1 e e C 5X 0.25 B PACKAGE OUTLINE A 1 2 BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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