P4C189 HIGH SPEED 16 x 4 STATIC CMOS RAM WITH INVERTING OUTPUTS FEATURES 5V Power Supply ±10% for both commercial and industrial temperature ranges. 16 x 4 Static RAM Fast Access Time – 35 ns Commercial and Industrial Separate I/O Available in the following packages: – 16-Pin PDIP Fully static operation with equal access and cycle times 3-STATE outputs for data bus applications Inverted Outputs DESCRIPTION of the written data. The P4C189 is a 64-bit high-speed Static RAM with a 16 x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. The output data is the complement The P4C189 is offered in a 16-Pin DIP package. Devices are offered in both commercial and industrial temperature ranges. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P7) Document # SRAM100 Rev OR 1 Revised October 2005 P4C189 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C I OUT DC Output Current 20 mA CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Grade(2) Commercial Industrial Ambient Temp Gnd Vcc Symbol Parameter Conditions Typ. Unit 0°C to 70°C 0V 5.0V ±10% CIN Input Capacitance VIN = 0V 5 pF –40°C to 85°C 0V 5.0V ±10% COUT Output Capacitance VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Test Conditions Parameter VOH Output High Voltage VCC = Min., VIN = VIH or VIL, IOH = –3.0 mA VOL Output Low Voltage VCC = Min., VIN = VIH or VIL, IOL = 24 mA VIH Input High Level VIL Input Low Level IIL Input Low Current IIH Input High Current VCC = Max, VIN = 2.7V ISC Output Short Circuit Current VCC = Max., VOUT = 0.0V ICC Power Supply Current VCC = Max. IL Output Leakage Current VOUT = VCC, VCC = Max. Min. Max. 0.5 V V 0.8 VIN = 0.5 V (except CS) -0.6 VIN = 0.5 V (CS) -1.2 -150 Unit V 2.4 2.0 Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM100 Rev OR P4C189 V mA 5 µA -60 mA Commercial 55 Industrial 70 mA 50 µA 4. This parameter is sampled and not 100% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 2 of 8 P4C189 FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/ reading operation of the memory. When chip select (CS) and write enable (WE) are LOW, the information on data inputs (D0 through D3) is written into the addressed memory word. Reading is performed with chip select (CS) LOW and write enable (WE) HIGH. The information stored in the addressed word is read out on the inverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select (CS) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE CS WE Output Standby H X High Z Read L H DOUT Write L L High Z Mode Notes: H = HIGH L = Low X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state. AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -35 Min Max 35 Unit ns t RC Read Cycle Time tAA tAC Address Access Time Chip Enable Access Time t OH Output Hold from Address Change 2 ns tLZ Chip Enable to Output in Low Z 2 ns t HZ Chip Disable to Output in High Z 35 ns 15 ns 10 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) Document # SRAM100 Rev OR Page 3 of 8 P4C189 TIMING WAVEFORM OF READ CYCLE NO. 2 (6) AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -35 Parameter Min Max Unit tWC Write Cycle Time 35 ns tCW Chip Enable Time to End of Write 15 ns tAW Address Valid to End of Write 15 ns tAS Address Set-up Time 0 ns tWP Write Pulse Width 15 ns t AH Address Hold Time from End of Write 2 ns tDW Data Valid to End of Write 15 ns t DH Data Hold Time 2 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 15 0 ns ns WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Document # SRAM100 Rev OR Page 4 of 8 P4C189 CS CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Notes: 9. CS and WE must be LOW for WRITE cycle. 10. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state. Document # SRAM100 Rev OR 11. Write Cycle Time is measured from the last valid address to the first transition address. Page 5 of 8 P4C189 ORDERING INFORMATION SELECTION GUIDE The P4C189 is available in the following temperature range, speed, and package options. Temperature Range Package Speed (ns) 35 Commercial Temperature Plastic DIP -35PC Industrial Temperature Plastic DIP -35PI Document # SRAM100 Rev OR Page 6 of 8 P4C189 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P7 PLASTIC DUAL IN-LINE PACKAGE 16 (300 mil) Min Max 0.145 0.200 0.020 0.014 0.023 0.040 0.060 0.008 0.016 0.740 0.780 0.240 0.260 0.300 0.320 0.100 BSC 0.310 0.365 0.125 0.150 0° 15° Document # SRAM100 Rev OR Page 7 of 8 P4C189 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM100 P4C189 HIGH SPEED 16 x 4 Static CMOS RAM with inverting outputs REV. ISSUE DATE ORIG. OF CHANGE OR Oct-05 JDB Document # SRAM100 Rev OR DESCRIPTION OF CHANGE New Data Sheet Page 8 of 8