P4C423 HIGH SPEED 256 x 4 STATIC CMOS RAM FEATURES Separate I/O High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35 ns (Commercial) – 15/20/25/35 ns (Military) Fully TTL Compatible Inputs and Outputs Resistant to single event upset and latchup resulting from advanced process and design improvements CMOS for Low Power – 495 mW Max. – 10/12/15/20/25 (Commercial) – 495 mW Max. – 15/20/25/35 (Military) Standard 24-pin 300 mil DIP package. Single 5V±10% Power Supply DESCRIPTION The P4C423 is a 1,024-bit high-speed (10ns) Static RAM with a 256 x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS 1) and active HIGH chip select two (CS 2) as well as 3-state outputs. In addition to high performance and high density, the device features latch-up protection, single event and upset protection. The P4C423 is offered in a 24-pin 300 mil DIP. Devices are offered in both commercial and military temperature ranges. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (C4) Document # SRAM108 REV OR 1 Revised October 2005 P4C423 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C I OUT DC Output Current 20 mA CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Vcc Parameter Conditions Typ. Unit Ambient Temp Commercial 0°C to 70°C 0V 5.0V ±10% CIN Input Capacitance VIN = 0V 5 pF –55°C to 125°C 0V 5.0V ±10% COUT Output Capacitance VOUT = 0V 7 pF Military Gnd Symbol Grade (2) DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol P4C422 Parameter Test Conditions VOH Output High Voltage IOH = –5.2 mA, VCC = Min.2.4 VOL Output Low Voltage IOL = +8 mA, VCC = Min. VIH Input High Voltage VIL Input Low Voltage VCL Input Clamp Diode Voltage IIN = –10 mA –1.5 I IX Input Load Current GND ≤ VIN ≤ VCC –10 10 µA I OZ Output Current (High Z) VOL ≤ VOUT ≤ VOH , Output Disabled –10 10 µA I OS Output Short Circuit Current(3) VCC= Max., VOUT = GND 90 mA Min Max Unit V 0.4 V 2.1 V 0.8 V V POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current Temperature Range -10 -12 -15 -20 -25 -35 Commercial Military 90 N/A 90 N/A 90 90 90 90 65 90 65 90 Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4. This parameter is sampled and not 100% tested. Document # SRAM108 REV OR Unit mA mA 5. Transition time is ≤ 3ns for 10, 12, and 15 ns products and ≤ 5ns for 20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input and output levels of 1.5V. The output loading is equivalent to the specified IOL/IOH with a load capacitance of 15 pF (10, 12) or 30 pF (15, 20, 25, 35) as in Fig. 1a and 1b respectively. 6. Transition time is ≤ 3ns for 10, 12, and 15 ns products and ≤ 5ns for 20, 25, and 35 ns products, see Fig 1d. Transition is measured at steady state HIGH level -500mV or steady state LOW level +500mV on the output from a level on the input with load shown in Fig. 1c. 7. tW is measured at tWSA = min.; tWSA is measured at tW = min. Page 2 of 8 P4C423 FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/ reading operation of the memory. When the chip select one (CS 1) and the write enable (WE) are LOW and the chip select two (CS 2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the “write recovery glitch.” Reading is performed with chip selct one (CS 1) LOW, chip select two (CS 2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select one (CS 1) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE CS2 CS1 WE OE Output Notes: Standby L X X X High Z Standby X H X X High Z DOUT Disabled H L X H High Z H L X HIGH Z Read H L H L DOUT Write H L L X High Z Mode = HIGH = Low = Don't Care = Implies outputs are disabled or off. This condition is defined as high impedance state for the P4C422. AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10% except as noted, All Temperature Ranges)(2) Parameter Sym. tRC Read Cycle Time (5) tACS Chip Select Time (5) tZRCS Chip Select to High-Z (6) tAOS Output Enable Time tZROS Output Enable to High-Z tAA Address Access Time (5) -10* -20 -15 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max 12 (6) -12 12 20 15 25 35 Unit ns 7.5 8 8 12 15 25 ns 8 10 12 15 20 30 ns 7.5 8 8 12 15 25 ns 8 10 12 15 20 30 ns 10 12 15 20 25 35 ns *VCC = 5V ± 5% TIMING WAVEFORM OF READ CYCLE Document # SRAM108 REV OR Page 3 of 8 P4C423 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10% except as noted, All Temperature Ranges)(2) -10* Parameter Sym. -15 -12 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time (5) tZWS Write Enable to High-Z tWR Write Recovery Time tW Write Pulse Width tWSD 10 (6) 15 12 35 25 20 Unit ns 8 10 12 15 20 30 ns 8 10 12 15 20 25 ns 8 9 11 13 15 20 ns Data Setup Time Prior to Write (5) 0 0 0 2 5 5 ns tWHD Data Hold Time (5) 2 2 2 5 5 5 ns tWSA Address Setup Time 0 0 0 2 5 5 ns tWHA Address Hold Time (5) 2 2 4 5 5 5 ns tWSCS Chip Select Setup Time 0 0 0 2 5 5 ns tWHCS Chip Select Hold Time (5) 2 2 2 5 5 5 ns (5,7) (5,7) (5) *VCC = 5V ± 5% TIMING WAVEFORM OF WRITE CYCLE Document # SRAM108 REV OR Page 4 of 8 P4C423 AC TEST LOADS & WAVEFORMS Figure 1a Figure 1b Figure 1c Figure 1d Document # SRAM108 REV OR Page 5 of 8 P4C423 ORDERING INFORMATION SELECTION GUIDE The P4C423 is available in the following temperature range, speed, and package options. Temperature Range Package Speed (ns) 10 12 15 20 25 35 Side Brazed DIP -10CC -12CC -15CC -20CC -25CC -35CC Military Temperature Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM Military Processed* Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB Commercial Temperature *Military temperature range with MIL-STD-883, Class B compliance. N/A = Not Available Document # SRAM108 REV OR Page 6 of 8 P4C423 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C4 SIDE BRAZED DUAL IN-LINE PACKAGE 24 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.280 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - Document # SRAM108 REV OR Page 7 of 8 P4C423 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM108 P4C423 HIGH SPEED 256 x 4 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE ORIG 1997 JDB Document # SRAM108 REV OR DESCRIPTION OF CHANGE New Data Sheet Page 8 of 8