NTLJD4116N Power MOSFET 30 V, 4.6 A, mCoolt Dual N−Channel, 2x2 mm WDFN Package Features • WDFN Package Provides Exposed Drain Pad for Excellent Thermal • • • • • Conduction 2x2 mm Footprint Same as SC−88 Lowest RDS(on) Solution in 2x2 mm Package 1.5 V RDS(on) Rating for Operation at Low Voltage Gate Drive Logic Level Low Profile (< 0.8 mm) for Easy Fit in Thin Environments This is a Pb−Free Device http://onsemi.com V(BR)DSS RDS(on) MAX 70 mW @ 4.5 V 30 V 4.6 A 90 mW @ 2.5 V 125 mW @ 1.8 V 250 mW @ 1.5 V D Applications • DC−DC Converters (Buck and Boost Circuits) • Low Side Load Switch • Optimized for Battery and Load Management Applications in • ID MAX (Note 1) G Portable Equipment such as, Cell Phones, PDA’s, Media Players, etc. Level Shift for High Side Load Switch S N−CHANNEL MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±8.0 V ID 3.7 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C 2.7 t≤5s TA = 25°C 4.6 Steady State PD Power Dissipation (Note 2) Pulsed Drain Current ID TA = 85°C TA = 25°C tp = 10 ms 6 5 4 PIN CONNECTIONS A 2.5 D1 1.8 PD 0.71 W IDM 20 A −55 to 150 °C Source Current (Body Diode) (Note 2) IS 2.0 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu. © Semiconductor Components Industries, LLC, 2006 1 2 JFMG G 3 JF = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) W 1.5 TJ, TSTG Operating Junction and Storage Temperature May, 2006 − Rev. 4 1 2.3 TA = 25°C Steady State WDFN6 CASE 506AN TA = 25°C t≤5s Continuous Drain Current (Note 2) MARKING DIAGRAM 1 S1 1 G1 2 6 D1 5 G2 4 S2 D2 D2 3 (Top View) ORDERING INFORMATION Device Package Shipping † NTLJD4116NT1G WDFN6 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTLJD4116N/D NTLJD4116N THERMAL RESISTANCE RATINGS Parameter Symbol Max Junction−to−Ambient – Steady State (Note 3) RqJA 83 Junction−to−Ambient – Steady State Min Pad (Note 4) RqJA 177 Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA 54 Unit SINGLE OPERATION (SELF−HEATED) °C/W DUAL OPERATION (EQUALLY HEATED) Junction−to−Ambient – Steady State (Note 3) RqJA 58 Junction−to−Ambient – Steady State Min Pad (Note 4) RqJA 133 Junction−to−Ambient – t ≤ 5 s (Note 3) RqJA 40 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). http://onsemi.com 2 °C/W NTLJD4116N MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Conditions Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = 250 mA, Ref to 25°C Parameter Typ Max Unit OFF CHARACTERISTICS TJ = 25°C Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = 250 mA VDS = 24 V, VGS = 0 V V 18.1 mV/°C 1.0 TJ = 85°C mA 10 100 nA 1.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Gate Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(TH)/TJ 0.7 2.8 RDS(on) Forward Transconductance 0.4 gFS mV/°C VGS = 4.5, ID = 2.0 A 47 70 VGS = 2.5, ID = 2.0 A 56 90 VGS = 1.8, ID = 1.8 A 88 125 VGS = 1.5, ID = 1.5 A 133 250 VDS = 5.0 V, ID = 2.0 A 4.5 S 427 pF mW CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance VGS = 0 V, f = 1.0 MHz, VDS = 15 V 51 CRSS 32 Total Gate Charge QG(TOT) 5.4 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 1.24 RG 0.37 W td(ON) 4.8 ns tr 11.8 Gate Resistance VGS = 4.5 V, VDS = 15 V, ID = 2.0 A 6.5 nC 0.5 0.8 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(OFF) VGS = 4.5 V, VDD = 15 V, ID = 2.0 A, RG = 2.0 W tf 14.2 1.7 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Recovery Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time VSD VGS = 0 V, IS = 2.0 A TJ = 25°C 0.78 TJ = 125°C 0.62 tRR ta tb 1.2 V 10.5 VGS = 0 V, dISD/dt = 100 A/ms, IS = 2.0 A QRR 7.6 2.9 5.0 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 ns nC NTLJD4116N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 5 VGS = 1.7 V to 8 V 6 TJ = 25°C VDS ≥ 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 1.6 V 4 3 1.5 V 2 1.4 V 1.3 V 1 1.2 V 0 1 2 3 TJ = 25°C TJ = 100°C TJ = −55°C 5 4 0 1 0.5 1.5 2.5 2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.07 VGS = 4.5 V TJ = 100°C 0.06 0.05 TJ = 25°C 0.04 TJ = −55°C 0.03 0.02 1.0 1.5 2.0 2.5 3 0.14 TJ = 25°C 0.13 0.12 0.11 0.1 VGS = 1.8 V 0.09 0.08 0.07 VGS = 2.5 V 0.06 VGS = 4.5 V 0.05 0.04 1 2 3 4 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current and Gate Voltage 5 100,000 1.6 VGS = 0 V ID = 2 A VGS = 4.5 V 1.4 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 2 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 4 1.2 1.0 10,000 TJ = 150°C 1000 TJ = 100°C 100 0.8 0.6 −50 −25 0 25 50 75 100 125 150 10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 NTLJD4116N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C 1000 800 600 Ciss 400 Crss 200 Coss 0 5 5 0 VGS 15 10 20 25 5 15 4 VGS VDS 12 3 9 QGS 2 QGD 6 1 0 1 VDS Figure 7. Capacitance Variation 1000 3 ID = 2.0 A TJ = 25°C 0 30 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 6 2 3 4 5 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 3 100 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 2.0 A VGS = 4.5 V td(off) tf tr 10 td(on) 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance TJ = 125°C TJ = 150°C 2 TJ = 25°C 1 0 0.3 1 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 10 TC = 25°C TJ = 150°C SINGLE PULSE 10 ms 100 ms 1 ms 1 0.1 0.01 10 ms *See Note 2 on Page 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.9 Figure 10. Diode Forward Voltage versus Current 100 −ID, DRAIN CURRENT (AMPS) t, TIME (ns) 18 QT VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V dc 1 10 100 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 NTLJD4116N EFFECTIVE TRANSIENT THERMAL RESISTANCE TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 1000 100 D = 0.5 0.2 0.1 *See Note 2 on Page 1 10 P(pk) 0.05 0.02 1 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.1 0.000001 0.00001 0.0001 0.001 0.01 0.1 t, TIME (s) Figure 12. Thermal Response http://onsemi.com 6 1 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) 10 100 1000 NTLJD4116N PACKAGE DIMENSIONS WDFN6, 2x2 CASE 506AN−01 ISSUE B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 0.10 C 2X ÍÍÍ ÍÍÍ ÍÍÍ E DIM A A1 A3 b D D2 E E2 e K L J 0.10 C 2X A3 0.10 C MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 0.57 0.77 2.00 BSC 0.90 1.10 0.65 BSC 0.25 REF 0.20 0.30 0.15 REF A 6X 0.08 C C SEATING PLANE D2 D2 6X SOLDERMASK DEFINED MOUNTING FOOTPRINT* A1 2.30 6X e L 1 6X 0.35 0.43 4X 3 1 2X E2 6X K 4 6 6X b J BOTTOM VIEW 0.65 PITCH 6X 0.25 0.10 C A 0.05 C B 2X NOTE 3 0.72 1.05 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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