ONSEMI NTLJS2103P

NTLJS2103P
Power MOSFET
−12 V, −7.7 A, mCoolt Single P−Channel,
2x2 mm, WDFN Package
Features
• WDFN Package Provides Exposed Drain Pad for Excellent Thermal
•
•
•
•
•
Conduction
2x2 mm Footprint Same as SC−88 Package
Lowest RDS(on) Solution in 2x2 mm Package
1.2 V RDS(on) Rating for Operation at Low Voltage Logic Level Gate
Drive
Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
This is a Pb−Free Device
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RDS(on) TYP
ID MAX (Note 1)
25 mW @ −4.5 V
−5.9 A
35 mW @ −2.5 V
−5.3 A
45 mW @ −1.8 V
−2.0 A
60 mW @ −1.5 V
−1.0 A
95 mW @ −1.2 V
−0.2 A
V(BR)DSS
−12 V
Applications
S
• High Side Load Switch
• DC−DC Converters (Buck and Boost Circuits)
• Optimized for Battery and Load Management Applications in
•
G
P−CHANNEL MOSFET
Portable Equipment
Li−Ion Battery Linear Mode Charging
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
Value
Unit
Drain−to−Source Voltage
VDSS
−12
V
Gate−to−Source Voltage
VGS
±8.0
V
ID
−5.9
A
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Steady
State
TA = 25°C
TA = 85°C
−4.2
t≤5s
TA = 25°C
−7.7
Steady
State
PD
Power Dissipation
(Note 2)
ID
TA = 85°C
A
−3.5
−2.5
0.7
IDM
−24
A
TJ, TSTG
−55 to
150
°C
Source Current (Body Diode) (Note 2)
IS
−2.7
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
TA = 25°C
tp = 10 ms
Operating Junction and Storage Temperature
W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size,
(30 mm2, 2 oz Cu).
© Semiconductor Components Industries, LLC, 2009
July, 2009 − Rev. 2
1
2 J7MG
G
3
6
5
4
J7 = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
PD
Pulsed Drain Current
Pin 1
3.3
TA = 25°C
Steady
State
WDFN6
CASE 506AP
W
1.9
MARKING
DIAGRAM
D
TA = 25°C
t≤5s
Continuous Drain
Current (Note 2)
S
1
D
1
D
2
G
3
D
S
6
D
5
D
4
S
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NTLJS2103PTAG
WDFN6
(Pb−Free)
3000/Tape & Reel
NTLJS2103PTBG
WDFN6
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTLJS2103P/D
NTLJS2103P
THERMAL RESISTANCE RATINGS
Symbol
Max
Junction−to−Ambient – Steady State (Note 3)
Parameter
RqJA
65
Junction−to−Ambient – t ≤ 5 s (Note 3)
RqJA
38
Junction−to−Ambient – Steady State Min Pad (Note 4)
RqJA
180
Unit
°C/W
3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu).
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
−12
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, Ref to 25°C
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
VDS = −12 V, VGS = 0 V
V
−8.0
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−5.0
IGSS
VDS = 0 V, VGS = ±8.0 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = −250 mA
Negative Gate Threshold
Temperature Coefficient
VGS(TH)/TJ
±0.1
mA
mA
ON CHARACTERISTICS (Note 5)
Drain−to−Source On−Resistance
−0.8
2.6
RDS(on)
Forward Transconductance
−0.3
gFS
V
mV/°C
VGS = −4.5, ID = −5.9 A
25
40
VGS = −4.5, ID = −3.0 A
25
40
VGS = −2.5, ID = −5.3 A
35
50
VGS = −2.5, ID = −3.0 A
35
50
VGS = −1.8, ID = −2.0 A
45
75
VGS = −1.5, ID = −1.0 A
60
100
VGS = −1.2, ID = −200 mA
95
400
VDS = −6.0 V, ID = −2.0 A
8.8
S
1157
pF
mW
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1.0 MHz,
VDS = −6.0 V
300
200
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
3.6
RG
15.7
W
td(ON)
8.0
ns
Gate Resistance
12.8
VGS = −4.5 V, VDS = −9.6 V,
ID = −5.9 A
15
nC
0.4
1.6
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = −4.5 V, VDD = −8.0 V,
ID = −5.9 A, RG = 2.0 W
tf
27
74
88
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Recovery Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.62
TJ = 85°C
0.56
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V, IS = −1.0 A
27
VGS = 0 V, dISD/dt = 100 A/ms,
IS = −1.0 A
QRR
10
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2
V
50
ns
17
14
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.0
nC
NTLJS2103P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
20
−ID, DRAIN CURRENT (AMPS)
TJ = 25°C
−2 V
−2.5 V
16
−1.8 V
12
−1.5 V
8
4
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = −4.5 V
−1.0 V
0
0.5
1.0
1.5
2.0
−1.1 V
2.5
3.0
3.5
−1.2 V
4.0
4.5
5.0
10
8
6
ID = −5.9 A
0.14
0.12
0.10
0.08
ID = −0.2 A
0.02
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
5.0
0.75
TJ = −55°C
1.0
1.25
1.5
1.75
2.0
2.25
0.20
TJ = 25°C
0.18
−1.2 V
0.16
0.14
0.10
0.08
0.06
VGS = −2.5 V
0.04
0.02
0.00
VGS = −4.5 V
0
−IDSS, LEAKAGE (nA)
1.1
1.0
0.9
2
4
6
8
10
12
14
16
18
20
−ID, DRAIN CURRENT (AMPS)
100000
1.2
VGS = −1.8 V
VGS = −1.5 V
0.12
VGS = 0 V
VGS = −4.5 V
ID = −5.9 A
1.3
2.5
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.5
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = 125°C
2
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.4
TJ = 25°C
4
Figure 2. Transfer Characteristics
0.16
0
12
Figure 1. On−Region Characteristics
0.18
0.00
14
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
0.04
16
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.20
0.06
VDS = −5 V
18
0
0.5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
20
TJ = 150°C
10000
TJ = 125°C
0.8
0.7
−50
−25
0
25
50
75
100
125
150
1000
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
12
NTLJS2103P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
C, CAPACITANCE (pF)
1600
Ciss
1400
-V GS, GATE-TO-SOURCE VOLTAGE (VOLTS)
VGS = 0 V
TJ = 25°C
f = 1 MHz
1200
1000
800
600
Coss
400
200
0
Crss
0
2
4
6
8
10
12
5
10
4
-VDS
QGD
4
VDS = −9.6 V
ID = −5.9 A
TJ = 25°C
1
0
0
2
4
6
8
10
2
14
12
0
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
VGS = −4.5 V
VDD = −8.0 V
ID = −5.9 A
−IS, SOURCE CURRENT (AMPS)
10000
t, TIME (ns)
8
6
2 QGS
Figure 7. Capacitance Variation
td(off)
tf
100
tr
10
td(on)
1
-VGS
3
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
12
QT
-V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1800
10
10
TJ = 150°C
1
100
VGS = 0 V
0
0.2
0.4
TJ = 25°C
0.6
0.8
1.0
1.2
1.4
RG, GATE RESISTANCE (OHMS)
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
0.8
60
ID = −250 mA
0.7
50
POWER (WATTS)
−VGS(th) (V)
0.6
0.5
0.4
0.3
0.2
30
20
10
0.1
0
−50
40
−25
0
25
50
75
100
125
0
0.001
150
0.01
0.1
1
10
100
SINGLE PULSE TIME (s)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
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4
1000
NTLJS2103P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−ID, DRAIN CURRENT (A)
100
1 ms
10
10 ms
1
VGS = −8 V
SINGLE PULSE
dc
0.1 TC = 25°C
RDS(on) LIMIT
Package Limit
Thermal Limit
0.01
0.1
1
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
R(t), EFFECTIVE TRANSIENT THERMAL
RESPONSE NORMALIZED (°C/W)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
1
Duty Cycle = 0.5
0.2
0.1
P(pk)
0.1
0.05
0.01
0.0001
Test Type = 1 sq in 2 oz
RqJA = 1 sq in 2 oz
t1
t2
DUTY CYCLE, D = t1/t2
Single Pulse
0.001
0.01
0.1
PULSE TIME (s)
1
Figure 14. FET Thermal Response
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5
10
100
1000
NTLJS2103P
PACKAGE DIMENSIONS
WDFN6 2x2
CASE 506AP−01
ISSUE B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND
IS MEASURED BETWEEN 0.15 AND 0.20mm FROM
TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL
LEAD IS CONNECTED TO TERMINAL LEAD # 4.
6. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
A
B
PIN ONE
REFERENCE
0.10 C
2X
2X
ÍÍ
ÍÍ
E
DIM
A
A1
A3
b
b1
D
D2
E
E2
e
K
L
L2
J
J1
0.10 C
A3
0.10 C
A
7X
0.08 C
A1
C
D2
6X
L
SEATING
PLANE
e
L2
3
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
SOLDERMASK DEFINED
MOUNTING FOOTPRINT
4X
1
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
0.51
0.61
2.00 BSC
1.00
1.20
2.00 BSC
1.10
1.30
0.65 BSC
0.15 REF
0.20
0.30
0.20
0.30
0.27 REF
0.65 REF
2.30
b1
6X
0.10 C A
E2
1.10
6X
B
6X
0.35
0.43
0.05 C
1
NOTE 5
K
6
4
b
J
J1
6X
0.10 C A
0.05 C
0.60
1.25
0.35
B
NOTE 3
0.34
BOTTOM VIEW
0.65
PITCH
0.66
DIMENSIONS: MILLIMETERS
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NTLJS2103P/D