NUP4106 Low Capacitance Surface Mount TVS for High-Speed Data Interfaces The NUP4106 transient voltage suppressor is designed to protect equipment attached to high speed communication lines from ESD and lightning. http://onsemi.com SO−8 LOW CAPACITANCE VOLTAGE SUPPRESSOR 500 WATTS PEAK POWER 3.3 VOLTS Features • SO−8 Package • Peak Power − 500 W 8 x 20 mS • ESD Rating: IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact) • UL Flammability Rating of 94 V−0 • This is a Pb−Free Device PIN CONFIGURATION AND SCHEMATIC Typical Applications • • • • • • High Speed Communication Line Protection T1/E1 Secondary Protection T3/E3 Secondary Protection Analog Video Protection Base Stations I2C Bus Protection I/O 1 1 8 GND REF 1 2 7 I/O 4 REF 1 3 6 I/O 3 I/O 2 4 5 GND SOIC−8 CASE 751 PLASTIC 8 MAXIMUM RATINGS 1 Rating Peak Power Dissipation 8 x 20 mS @ TA = 25°C (Note 1) Junction and Storage Temperature Range Lead Solder Temperature − Maximum 10 Seconds Duration IEC 61000−4−2 Contact Air Symbol Value Unit Ppk 500 W TJ, Tstg −55 to +150 °C TL 260 °C ESD ±8 ±15 kV MARKING DIAGRAM 8 P4106 AYWWG G 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Non−repetitive current pulse 8 x 20 mS exponential decay waveform Pin 2/3 to Pin 5/8 A Y WW G = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NUP4106DR2G SO−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 February, 2009 − Rev. 0 1 Publication Order Number: NUP4106/D NUP4106 ELECTRICAL CHARACTERISTICS Symbol Min Typ Max Unit Reverse Breakdown Voltage @ It = 1.0 mA Characteristic VBR 5.0 − − V Reverse Leakage Current @ VRWN = 3.3 V IR N/A − 5.0 mA Maximum Clamping Voltage @ IPP = 1.0 A, 8 x 20 mS VC N/A − 7.0 V Maximum Clamping Voltage @ IPP = 10 A, 8 x 20 mS VC N/A − 10 V Maximum Clamping Voltage @ IPP = 25 A, 8 x 20 mS VC N/A − 15 V Between I/O Pins and Ground @ VR = 0 V, 1.0 MHz Capacitance − 8.0 15 pF Between I/O Pins @ VR = 0 Volts, 1.0 MHz Capacitance − 4.0 − pF ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) Symbol IF Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VC VBR VRWM Working Peak Reverse Voltage VBR V IR VF IT Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IT Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation C IPP Uni−Directional TVS Capacitance @ VR = 0 and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. TYPICAL CHARACTERISTICS tr 90 14 PEAK VALUE IRSM @ 8 ms 12 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 CLAMPING VOLTAGE (V) % OF PEAK PULSE CURRENT 100 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 8 6 4 2 10 0 10 0 20 40 60 0 80 0 10 20 30 40 50 PEAK PULSE CURRENT (A) t, TIME (ms) Figure 2. Clamping Voltage vs. Peak Pulse Current (8 x 20 ms Waveform) Figure 1. 8 x 20 ms Pulse Waveform http://onsemi.com 2 NUP4106 APPLICATIONS INFORMATION Option 2 Protection of four data lines with bias and power supply isolation resistor. The NUP4106 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4106 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SO−8). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions avoiding damage to the power supply and other downstream components. I/O 1 I/O 2 VCC 10 K 8 2 7 3 6 4 5 I/O 3 NUP4106 Configuration Options The NUP4106 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 4, 6 and 7. The negative reference is connected at pins 5 and 8. These pins must be connected directly to ground using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. I/O 4 Figure 4. The NUP4106 can be isolated from the power supply by connecting a series resistor between pins 2 and 3 and VCC. A 10 kW resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. Option 3 Protection of four data lines using the internal TVS diode as reference. I/O 1 I/O 2 Option 1 Protection of four data lines and the power supply using VCC as reference. I/O 1 I/O 2 VCC 1 1 8 I/O 3 2 7 I/O 4 3 6 4 5 1 8 NC 2 7 NC 3 6 4 5 Figure 5. In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pins 2 and 3 are not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc=Vf + VTVS). I/O 3 I/O 4 Figure 3. For this configuration, connect pins 2 and 3 directly to the positive supply rail (VCC). The data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. http://onsemi.com 3 NUP4106 ESD Protection of Power Supply Lines When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: Power Supply IESDpos VCC Protected Data Line Device L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4106 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. D1 IESDpos D2 IESDneg IESDneg VF + VCC −VF Figure 6. Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. Power Supply IESDpos D5 D7 D2 D4 D6 D8 Figure 8. NUP4106 Equivalent Circuit During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. IESDpos D1 D3 0 Power Supply VCC Protected Device D1 VCC IESDneg D1 Data Line D2 Protected Device VC = VCC + Vf + (L diESD/dt) IESDneg IESDpos Data Line D2 VC = −Vf − (L diESD/dt) Figure 7. Figure 9. An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the The resulting clamping voltage on the protected IC will be: Vc = VFD1 + VTVS. The clamping voltage of the TVS diode is provided in Figure 2 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. http://onsemi.com 4 NUP4106 TYPICAL APPLICATIONS UPSTREAM USB PORT VBUS VBUS VBUS VBUS D+ RT D+ RT D− VBUS GND USB Controller D− VBUS NUP4106 CT CT DOWNSTREAM USB PORT GND VBUS NUP2201MR6 VBUS RT D+ RT D− GND CT CT DOWNSTREAM USB PORT Figure 10. ESD Protection for USB Port RJ45 Connector TX+ TX+ TX− TX− PHY Ethernet (10/100) Coupling Transformers RX+ RX+ RX− RX− NUP4106 VCC GND N/C N/C Figure 11. Protection for Ethernet 10/100 (Differential Mode) http://onsemi.com 5 NUP4106 R1 RTIP R3 R2 RRING T1 VCC T1/E1 TRANSCEIVER NUP4106 R4 TTIP R5 TRING T2 Figure 12. TI/E1 Interface Protection http://onsemi.com 6 NUP4106 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J SOLDERING FOOTPRINT* MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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