ONSEMI NTD4963N-35G

NTD4963N
Power MOSFET
30 V, 44 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Three Package Variations for Design Flexibility
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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V(BR)DSS
RDS(ON) MAX
9.6 mW @ 10 V
30 V
Applications
ID MAX
44 A
16 mW @ 4.5 V
• CPU Power Delivery
• DC−DC Converters
• Recommended for High Side (Control)
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Unit
30
V
VGS
±20
V
ID
10.0
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
1.64
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
8.1
A
Power Dissipation
RqJA (Note 2)
TA = 85°C
Steady
State
TA = 85°C
1.1
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
44
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
35.7
W
TA = 25°C
IDM
132
A
TA = 25°C
IDmaxPkg
35
A
TJ,
TSTG
−55 to
+175
°C
TC = 85°C
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
32
IS
30
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 26 Apk, L = 0.1 mH, RG = 25 W)
EAS
33.8
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
4
4
4
1 2
5.8
PD
tp=10ms
S
N−CHANNEL MOSFET
7.2
TA = 25°C
Pulsed Drain
Current
G
1
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
2 3
1
2
3
CASE 369AC
CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
4
Drain
YWW
49
63NG
Value
VDSS
YWW
49
63NG
Gate−to−Source Voltage
Symbol
YWW
49
63NG
Parameter
Drain−to−Source Voltage
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
Y
WW
4963N
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 0
1
Publication Order Number:
NTD4963N/D
NTD4963N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
4.1
°C/W
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient – Steady State (Note 3)
RqJA
77
Junction−to−Ambient – Steady State (Note 4)
RqJA
118
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
5
VGS = 10 V
VGS = 4.5 V
Forward Transconductance
gFS
1.45
ID = 30 A
8.2
ID = 15 A
8.2
ID = 30 A
13.6
ID = 15 A
13.6
VDS = 1.5 V, ID = 30 A
40
mV/°C
9.6
16
mW
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
115
Total Gate Charge
QG(TOT)
8.1
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
1035
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V, ID = 30 A
220
1.2
3.5
pF
nC
3.5
VGS = 10 V, VDS = 15 V, ID = 30 A
16.2
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
12
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
20
14
3
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
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2
ns
NTD4963N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
td(ON)
Turn−On Delay Time
Rise Time
7.0
tr
Turn−Off Delay Time
td(OFF)
Fall Time
17
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
ns
20
tf
2
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.96
TJ = 125°C
0.83
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.2
V
17
9
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
ns
8
QRR
6
nC
Source Inductance (Note 7)
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK (Note 7)
LD
Gate Inductance (Note 7)
LG
3.46
Gate Resistance
RG
1.0
PACKAGE PARASITIC VALUES
1.88
TA = 25°C
W
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
ORDERING INFORMATION
Package
Shipping†
NTD4963NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4963N−1G
IPAK
(Pb−Free)
75 Units / Rail
NTD4963N−35G
IPAK Trimmed Lead
(Pb−Free)
75 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTD4963N
TYPICAL PERFORMANCE CURVES
VGS = 4.4 V
TJ = 25°C
VDS = 10 V
4.2 V
40
4.0 V
30
3.8 V
ID, DRAIN CURRENT (A)
50
3.6 V
20
3.4 V
10
3.2 V
2.8 V
0
2E−02
1.9E−02
1.8E−02
1.7E−02
1.6E−02
1.5E−02
1.4E−02
1.3E−02
1.2E−02
1.1E−02
1.0E−02
9E−03
8E−03
7E−03
6E−03
5E−03
1
4
3
2
50
40
30
TJ = 25°C
20
10
TJ = 125°C
0
5
1
2
1.5
TJ = −55°C
3
2.5
4
3.5
5
5.5
45
50
4.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
60
4.6 V thru 10 V
20E−03
ID = 30 A
TJ = 25°C
TJ = 25°C
VGS = 4.5 V
15E−03
10E−03
4
3
6
5
8
7
9
10
VGS = 10 V
5E−03
0E+00
10
15
20
25
30
35
40
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
1.8
1.6
ID = 30 A
VGS = 10 V
1.4
1.2
1.0
TJ = 150°C
TJ = 125°C
100
10
TJ = 25°C
1
0.8
0.6
−50
VGS = 0 V
1,000
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (A)
60
0.1
−25
0
25
50
75
100
125
150
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTD4963N
1200
Ciss
VGS = 0 V
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL PERFORMANCE CURVES
TJ = 25°C
C, CAPACITANCE (pF)
1000
800
600
400
Coss
200
0
Crss
0
10
5
15
20
25
30
10
QT
9
8
7
6
Qgs
5
4
3
ID = 30 A
TJ = 25°C
VDD = 15 V
VGS = 30 A
2
1
0
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IS, SOURCE CURRENT (A)
t, TIME (ns)
100
td(off)
tr
10
td(on)
tf
1
10
RG, GATE RESISTANCE (W)
25
TJ = 25°C
20
15
10
5
0
100
0.4
10 ms
100 ms
10
1 ms
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
0.6
0.7
0.8
0.9
1.0
Figure 10. Diode Forward Voltage vs. Current
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D, DRAIN CURRENT (A)
VGS = 30 V
Single Pulse
TC = 25°C
0.5
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
0.01
18
VGS = 0 V
VDD = 15 V
ID = 15 A
VGS = 11.5 V
100
16
30
1000
1000
10
4
6
12
14
8
QG, TOTAL GATE CHARGE (nC)
2
Figure 8. Gate−to−Source and Drain−to−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
1
Qgd
35
ID = 26 A
30
25
20
15
10
5
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
150
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
NTD4963N
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369AA−01
ISSUE A
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
H
J
L
R
S
U
V
Z
H
3
U
F
J
L
D
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
2 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.025 0.035
0.018 0.024
0.030 0.045
0.386 0.410
0.018 0.023
0.090 BSC
0.180 0.215
0.024 0.040
0.020
−−−
0.035 0.050
0.155
−−−
T
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.63
0.89
0.46
0.61
0.77
1.14
9.80 10.40
0.46
0.58
2.29 BSC
4.57
5.45
0.60
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD4963N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
B
V
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
D
H
3 PL
0.13 (0.005) W
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
IPAK (STRAIGHT LEAD DPAK)
CASE 369D−01
ISSUE B
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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7
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NTD4963N/D