ONSEMI NTD4913N

NTD4913N
Power MOSFET
30 V, 32 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
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V(BR)DSS
Applications
• CPU Power Delivery
• DC−DC Converters
RDS(ON) MAX
ID MAX
10.5 mW @ 10 V
30 V
32 A
15 mW @ 4.5 V
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
10.5
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
TA = 100°C
TA = 25°C
PD
2.5
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
7.7
A
Power Dissipation
RqJA (Note 2)
Continuous Drain
Current RqJC
(Note 1)
TA = 100°C
TA = 25°C
PD
1.36
TC = 25°C
ID
32
W
A
23
TC = 25°C
PD
24
W
TA = 25°C
IDM
132
A
TA = 25°C
IDmaxPkg
60
A
TJ,
TSTG
−55 to
+175
°C
IS
20
A
Drain to Source dV/dt
dV/dt
8.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 21 Apk, L = 0.1 mH, RG = 25 W)
EAS
22
mJ
TL
260
°C
Pulsed Drain
Current
tp=10ms
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
4
4
4
5.4
TC = 100°C
Power Dissipation
RqJC (Note 1)
S
N−CHANNEL MOSFET
7.4
Power Dissipation
RqJA (Note 1)
Steady
State
G
1 2
1
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
2 3
1
2
3
CASE 369AC
CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
4
Drain
YWW
49
13NG
Value
YWW
49
13NG
Symbol
YWW
49
13NG
Parameter
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
Y
WW
4913N
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 0
1
Publication Order Number:
NTD4913N/D
NTD4913N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
6.2
Junction−to−TAB (Drain)
RqJC−TAB
4.3
Junction−to−Ambient – Steady State (Note 3)
RqJA
59
Junction−to−Ambient – Steady State (Note 4)
RqJA
110
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
15
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.2
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V
gFS
1.67
4.0
VGS = 4.5 V
Forward Transconductance
1.0
ID = 30 A
8.2
ID = 15 A
8.2
ID = 30 A
12.5
ID = 15 A
12.5
VDS = 1.5 V, ID = 30 A
39
mV/°C
10.5
15
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
12.5
Total Gate Charge
QG(TOT)
6.2
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
1013
VGS = 0 V, f = 1.0 MHz, VDS = 15 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
370
1.7
3.7
pF
nC
0.9
VGS = 10 V, VDS = 15 V;
ID = 30 A
13
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
10
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
21
14.7
2.3
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
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2
ns
NTD4913N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
td(ON)
tr
Turn−Off Delay Time
Fall Time
td(OFF)
7.1
VGS = 10 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
18
ns
19
1.7
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.92
TJ = 125°C
0.70
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.1
V
26
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 30 A
14
ns
12
QRR
15
nC
Source Inductance (Note 7)
LS
2.99
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK (Note 7)
LD
Gate Inductance (Note 7)
LG
4.9
Gate Resistance
RG
1.0
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
2.0
W
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
ORDERING INFORMATION
Package
Shipping†
NTD4913NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4913N−1G
DPAK−3
(Pb−Free)
75 Units / Rail
NTD4913N−35G
IPAK Trimmed Lead
(3.5 " 0.15 mm)
(Pb−Free)
75 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTD4913N
TYPICAL CHARACTERISTICS
10 V
VGS = 3.8 V
5.0
4.5
40
35
50
TJ = 25°C
3.6 V
3.4 V
30
3.2 V
25
20
3.0 V
15
2.8 V
10
5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
7V
45
55
4.0 V
2.6 V
2.4 V
0
1
2
3
4
35
30
25
15
TJ = −55°C
2.0
2.5
3.0
3.5
4.0
4.5
Figure 2. Transfer Characteristics
0.022
0.020
0.018
0.016
0.014
0.012
0.010
4.0
5.0
6.0
7.0
8.0
9.0
VGS (V)
10
0.015
0.014
TJ = 25°C
0.013
VGS = 4.5 V
0.012
0.011
0.010
0.009
VGS = 10 V
0.008
0.007
0.006
0.005
0.004
15
20
25
30
35
40
45
50
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.2
10,000
VGS = 0 V
ID = 30 A
VGS = 10 V
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = 125°C
10
Figure 1. On−Region Characteristics
0.024
2.0
TJ = 25°C
20
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 30 A
TJ = 25°C
3.0
40
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.026
0.008
VDS = 10 V
45
5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
50
ID, DRAIN CURRENT (A)
55
TJ = 150°C
1000
1.6
1.4
1.2
1.0
TJ = 125°C
100
TJ = 85°C
0.8
0.6
−50 −25
0
25
50
75
100
125
150
175
10
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTD4913N
C, CAPACITANCE (pF)
1400
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
1200
Ciss
1000
800
600
Coss
400
200
0
Crss
0
5
10
15
20
25
30
15.0
13.5
Qgd
6.0
Qgs
4.5
VDD = 15 V
VGS = 10 V
ID = 30 A
3.0
1.5
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
30
IS, SOURCE CURRENT (A)
t, TIME (ns)
7.5
Qg, TOTAL GATE CHARGE (nC)
100
td(off)
tf
tr
td(on)
10
1
10
VGS = 0 V
25
20
15
TJ = 125°C
10
5
0
100
TJ = 25°C
0
0.2
0.4
0.6
0.8
1.0
1.2
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
1000
ID, DRAIN CURRENT (A)
9.0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDD = 15 V
ID = 15 A
VGS = 10 V
100
10 ms
10
100 ms
1 ms
VGS = 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
1
0.1
QT
10.5
1000
1
TJ = 25°C
12.0
0.1
1
10 ms
dc
10
100
25
ID = 21 A
20
15
10
5
0
25
50
75
100
125
150
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4913N
TYPICAL CHARACTERISTICS
100
R(t) (°C/W)
10
1
0.1
Duty Cycle = 50%
20%
10%
5%
2%
1%
Single Pulse
0.01
Psi Tab−A
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
PULSE TIME (sec)
Figure 13. FET Thermal Response
45
40
VDS = 1.5 V
35
30
GFS (S)
0.001
25
20
15
10
5
0
0
5
10
15
20
25
ID (A)
Figure 14. GFS vs. ID
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6
30
35
40
100
1000
NTD4913N
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369AA−01
ISSUE A
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
−T−
E
R
4
A
S
1
2
3
DIM
A
B
C
D
E
F
H
J
L
R
S
U
V
Z
Z
H
U
F
J
L
D 2 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.025 0.035
0.018 0.024
0.030 0.045
0.386 0.410
0.018 0.023
0.090 BSC
0.180 0.215
0.024 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.63
0.89
0.46
0.61
0.77
1.14
9.80 10.40
0.46
0.58
2.29 BSC
4.57
5.45
0.60
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD4913N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
B
V
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
D
H
3 PL
0.13 (0.005) W
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
IPAK (STRAIGHT LEAD DPAK)
CASE 369D−01
ISSUE B
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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8
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For additional information, please contact your local
Sales Representative
NTD4913N/D