NTD4805N Power MOSFET 30 V, 88 A, Single N−Channel, DPAK/IPAK Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS Applications • CPU Power Delivery • DC−DC Converters • Low Side Switching RDS(on) MAX ID MAX 5.0 mW @ 10 V 30 V 88 A 7.4 mW @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Symbol Value Unit VDSS 30 V VGS "20 V ID 16 A S 4 Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C PD 2.24 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 12.6 A 4 4 TA = 25°C TC = 25°C Power Dissipation (RqJC) (Note 1) TC = 25°C 9.8 PD ID TC = 85°C 1 2 1.35 W A 88 68 PD 66 IDM 175 A TA = 25°C IDmaxPkg 45 A Operating Junction and Storage Temperature TJ, Tstg −55 to 175 Source Current (Body Diode) °C IS 55 A dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 30 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 24 A, RG = 25 W) EAS 288 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL Drain to Source dV/dt CASE 369C DPAK (Bend Lead) STYLE 2 2 3 1 2 3 CASE 369AC CASE 369D 3 IPAK DPAK (Straight Lead) (Straight Lead) STYLE 2 W TA = 25°C tp=10ms Current Limited by Package 1 3 °C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 48 05NG TA = 85°C YWW 48 05NG Steady State Continuous Drain Current (RqJC) (Note 1) Pulsed Drain Current 12.6 YWW 48 05NG Power Dissipation (RqJA) (Note 2) TA = 85°C N−Channel G 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4805N G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 0 1 Publication Order Number: NTD4805N/D NTD4805N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 2.25 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient − Steady State (Note 1) RqJA 67 Junction−to−Ambient − Steady State (Note 2) RqJA 111 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 27 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.5 5.86 VGS = 10 to 11.5 V ID = 30 A 4.3 ID = 15 A 4.2 VGS = 4.5 V ID = 30 A 6.0 ID = 15 A 5.8 VDS = 15 V, ID = 15 A mV/°C 5.0 mW 7.4 17 S 2865 pF CHARGES AND CAPACITANCES Input Capacitance Ciss VGS = 0 V, f = 1.0 MHz, VDS = 12 V Output Capacitance Coss Reverse Transfer Capacitance Crss 338 Total Gate Charge QG(TOT) 20.5 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge VGS = 4.5 V, VDS = 15 V, ID = 30 A QGD QG(TOT) 610 26 nC 4.05 8.28 8.36 VGS = 11.5 V, VDS = 15 V, ID = 30 A 48 nC 18.3 ns SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 30 A, RG = 3.0 W 101.5 16.3 tf 10.6 td(on) 8.1 tr td(off) VGS = 11.5 V, VDS = 15 V, ID = 30 A, RG = 3.0 W tf 23.1 27.1 5.7 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4805N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.87 1.2 V TJ = 125°C 0.76 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 25.7 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A ns 13.1 12.6 QRR 18 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 0.8 PACKAGE PARASITIC VALUES TA = 25°C http://onsemi.com 3 1.88 W NTD4805N TYPICAL PERFORMANCE CURVES 180 10 V 6V 3.8 V 5V 4.5 V 90 80 3.6 V 70 60 3.4 V 50 40 30 3.2 V 20 3V 10 0 2.8 V 0 1 2 3 VDS ≥ 10 V 160 140 120 100 80 60 TJ = 125°C 40 TJ = 25°C 20 TJ = −55°C 0 5 4 0 2 1 3 4 5 6 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.045 ID = 30 A TJ = 25°C 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 3 4 5 6 7 8 9 10 0.01 TJ = 25°C 0.009 0.008 VGS = 4.5 V 0.007 0.006 0.005 0.004 VGS = 11.5 V 0.003 0.002 0.001 0 30 35 40 45 50 55 60 65 70 75 80 85 90 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.0 100,000 VGS = 0 V ID = 30 A VGS = 10 V TJ = 175°C 10,000 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 4V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 110 100 1.5 1.0 0.5 −50 −25 1000 TJ = 125°C 100 10 0 25 50 75 100 125 150 175 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 25 NTD4805N 5000 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 4000 C, CAPACITANCE (pF) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES 3000 Ciss 2000 Crss 1000 Coss 0 10 Crss 0 5 VGS 5 10 15 20 25 VDS 7 6 5 2 ID = 30 A VGS = 4.5 V TJ = 25°C 1 0 0 5 10 15 20 QG, TOTAL GATE CHARGE (nC) 25 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 30 1000 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 30 A VGS = 11.5 V 100 td(off) tr td(on) 10 tf 1 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 25 100 15 10 5 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 100 ms 1 ms VGS = 20 V SINGLE PULSE TC = 25°C 1 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 10 ms 10 0.8 0.9 0.6 0.7 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 Figure 10. Diode Forward Voltage vs. Current 1000 100 TJ = 25°C 20 0 0.5 1 I D, DRAIN CURRENT (AMPS) Q2 3 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) t, TIME (ns) QT Q1 4 450 400 ID = 29 A 350 300 250 200 150 100 50 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4805N TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 100°C 125°C 25°C 10 1 1 10 100 PULSE WIDTH (ms) 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E−05 1.0E−04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E−03 1.0E−02 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E−01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping † NTD4805NT4G DPAK (Pb−Free) 2500 Tape & Reel NTD4805N−1G IPAK (Pb−Free) 75 Units/Rail NTD4805N−35G IPAK Trimmed Lead (3.5 " 0.15 mm) (Pb−Free) 75 Units/Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4805N PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE −T− E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D 2 PL 0.13 (0.005) G M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 3 IPAK, STRAIGHT LEAD CASE 369AC−01 ISSUE O B V C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G H D NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. 3 PL 0.13 (0.005) W http://onsemi.com 7 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 NTD4805N PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) DIM A B C D E F G H J K R S V Z T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 8 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NTD4805N/D