CYPRESS CY24239

39
CY24239
Spread Spectrum Frequency Timing Generator
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• –1.2% and –2.4% Spread Spectrum support
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• Seventeen SDRAM outputs provide support for
4 DIMMs
• SMBus interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 350 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:16 Delay: ..........................3.7 ns typ.
VDDQ3: .................................................................... 3.3V±5%
Table 1. Mode Input Table
Mode
0
1
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
CPU1:2
FS3 FS2 FS1 FS0
(MHz)
1
1
1
1
91.66
1
1
1
0
75.0
1
1
0
1
100.0
1
1
0
0
83.3
1
0
1
1
66.6
1
0
1
0
105.0
1
0
0
1
110.0
1
0
0
0
133.3
0
1
1
1
91.66
0
1
1
0
75.0
0
1
0
1
100.0
0
1
0
0
83.3
0
0
1
1
91.66
0
0
1
0
75.0
0
0
0
1
100.0
0
0
0
0
83.3
Pin Configuration[1]
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
XTAL
OSC
PLL Ref Freq
VDDQ3
IOAPIC_F
Stop
Clock
Control
I/O Pin
Control
IOAPIC0
VDDQ3
CPU_F
Stop
Clock
Control
PLL 1
CPU1
CPU2
÷2,3,4
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
Stop
Clock
Control
PCI2
PCI3
SMBus
Logic
PCI4
PCI5
VDDQ3
48MHz/FS1
PLL2
SDRAMIN
24MHz/FS0
VDDQ3
SDRAM0:16
Stop
Clock
Control
17
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY24239
CLK_STOP#
SDATA
SCLK
Spread
Spectrum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
–1.2%
–1.2%
–1.2%
–1.2%
–2.4%
–2.4%
–2.4%
–2.4%
Pin 3
PCI_STOP#
REF0
Block Diagram
X1
X2
PCI_F,
PCI0:5
(MHz)
30.5
25.0
33.3
27.76
33.3
26.3
27.5
33.3
30.5
25.0
33.3
27.76
30.5
25.0
33.3
27.76
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ3
IOAPIC0
IOAPIC_F
GND
CPU_F
CPU1
VDDQ3
CPU2
GND
CLK_STOP#
SDRAM16
VDDQ3
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDDQ3
24MHz/FS0
48MHz/FS1
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07038 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised May 18, 2001
CY24239
Pin Definitions
Pin Name
CPU1:2
Pin No.
51, 49
CPU_F
52
PCI1:5
11, 12, 13, 14,
16
9
PCI0/FS3
PCI_F/MODE
8
CLK_STOP#
47
IOAPIC_F
54
IOAPIC0
55
48MHz/FS1
29
24MHz/FS0
30
REF1/FS2
2
REF0
(PCI_STOP#)
3
SDRAMIN
17
SDRAM0:16
SCLK
SDATA
X1
X2
VDDQ3
GND
44, 43, 41, 40,
39, 38, 36, 35,
22, 21, 19, 18,
33, 32, 25, 24,
46
28
27
5
Pin
Type
Pin Description
O
CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. These outputs are affected by the CLK_STOP# input.
O
Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the CLK_STOP# input.
O
PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. These outputs are affected by the PCI_STOP# input.
I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs
or through serial input interface, see Table 2 and Table 6. This output is affected by the
PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and
PCI outputs.
I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Table 2 and Table 6. This output is not affected by the PCI_STOP# input.
When an input, selects function of pin 3 as described in Table 1.
I
CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs
start beginning with a full clock cycle (2–3 CPU clock latency).
O
Free-running IOAPIC Output: This output is a buffered version of the reference input
which is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied
to VDDQ3.
I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set
by voltage applied to VDDQ3. This output is disabled when CLK_STOP# is set LOW.
I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power-up, FS1
input will be latched, setting output frequencies as described in Table 2.
I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input
will be latched, setting output frequencies as described in Table 2.
I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2
input will be latched, setting output frequencies as described in Table 2.
I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.
The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of
PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides
a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins
(14.318 MHz).
I
Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs
(SDRAM0:16).
O
Buffered Outputs: These seventeen dedicated outputs provide copies of the signal
provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated
when CLK_STOP# input is set LOW.
I
I/O
I
6
I
1, 7, 15, 20,
31, 37, 45, 50,
56
4, 10, 23, 26,
34, 42, 48, 53
P
Document #: 38-07038 Rev. **
G
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers,
PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Connect to 3.3V.
Ground Connections: Connect all ground pins to the common system ground plane.
Page 2 of 15
CY24239
Functional Description
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon powerup these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon CY24239 power-up, the first 2 ms of operation is used
for input logic selection. During this period, the five I/O pins (2,
8, 9, 29, 30) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pins and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled, converting the l/O pins into operating clock outputs.
The 2-ms timer starts when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output (<40Ω, nominal), which is minimally affected by the 10-kΩ strap to ground or VDD. As with the series
termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length to
prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
VDD
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
CY24239
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
Clock Load
R
Output
Buffer
10 kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
VDD
Series Termination Resistor
10 kΩ
CY24239
R
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
Clock Load
Resistor Value R
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Document #: 38-07038 Rev. **
Page 3 of 15
CY24239
Spread Spectrum Frequency Timing Generator
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is specified in Table 6. Figure 4
details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the
SMBus data stream. Refer to Table 7 for more details.
EMI Reduction
Spread
Spectrum
Enabled
NonSpread
Spectrum
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX
MIN
Figure 4. Typical Modulation Profile
Document #: 38-07038 Rev. **
Page 4 of 15
CY24239
Serial Data Interface
The CY24239 features a two-pin, serial data interface that can
be used to configure internal register settings that control particular device functions. Upon power-up, the CY24239 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only
(to the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power management functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the CY24239 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held low.
and system power. Examples are clock outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections alternate
to the selections that are provided by the FS0:3
pins. Frequency is changed in a smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency transition allows CPU frequency change under
normal system operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, inter- Production PCB testing.
nal PLL is bypassed. Refer to Table 5.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing.
ten as 0.
Table 4. Byte Writing Sequence
Byte Sequence
Byte Name
1
Slave Address
11010010
Commands the CY24239 to accept the bits in Data Bytes 0–7 for internal
register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the CY24239 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the CY24239, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another addressed slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the CY24239, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 5
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
The data bits in Data Bytes 0–7 set internal CY24239 registers that
control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 5, Data Byte Serial Configuration
Map.
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
Don’t Care
Unused by the CY24239, therefore bit values are ignored (“don’t care”).
11
Data Byte 7
Document #: 38-07038 Rev. **
Bit Sequence
Byte Description
Page 5 of 15
CY24239
Writing Data Bytes
Each bit in Data Bytes 0–7 controls a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Bit Control
Pin Name
Control Function
0
1
Default
--
--
0
Data Byte 0
7
--
--
(Reserved)
6
--
--
SEL2
Refer to Table 6
0
5
--
--
SEL1
Refer to Table 6
0
Refer to Table 6
0
4
--
--
SEL0
3
--
--
Frequency Table Selection
2
--
--
SEL3
1
--
--
(Reserved)
0
--
Test Mode
7
--
6
Frequency ConFrequency Controlled by FS(3:0) Ta- trolled by SEL(3:0)
ble 2
Table 6
Refer to Table 6
0
0
--
--
0
--
Normal
Three-stated
0
--
--
--
--
0
--
--
--
--
--
0
5
--
--
--
--
--
0
4
--
--
--
--
--
0
3
46
SDRAM16
Clock Output Disable
LOW
Active
1
2
49
CPU2
Clock Output Disable
LOW
Active
1
1
51
CPU1
Clock Output Disable
LOW
Active
1
0
52
CPU_F
Clock Output Disable
LOW
Active
1
--
--
0
Data Byte 1
Data Byte 2
7
--
--
(Reserved)
6
8
PCI_F
Clock Output Disable
LOW
Active
1
5
16
PCI5
Clock Output Disable
LOW
Active
1
4
14
PCI4
Clock Output Disable
LOW
Active
1
3
13
PCI3
Clock Output Disable
LOW
Active
1
2
12
PCI2
Clock Output Disable
LOW
Active
1
1
11
PCI1
Clock Output Disable
LOW
Active
1
0
9
PCI0
Clock Output Disable
LOW
Active
1
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
29
48MHz
Clock Output Disable
LOW
Active
1
4
30
24MHz
Clock Output Disable
LOW
Active
1
3
33, 32,
25, 24
SDRAM12:15
Clock Output Disable
LOW
Active
1
Data Byte 3
Document #: 38-07038 Rev. **
Page 6 of 15
CY24239
Table 5. Data Bytes 0–7 Serial Configuration Map (continued)
Affected Pin
Bit(s)
Pin No.
Pin Name
2
22, 21,
19, 18
SDRAM8:11
1
39, 38,
36, 35
0
44, 43,
41, 40
Bit Control
Control Function
0
1
Default
Clock Output Disable
LOW
Active
1
SDRAM4:7
Clock Output Disable
LOW
Active
1
SDRAM0:3
Clock Output Disable
LOW
Active
1
Data Byte 4
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
54
IOAPIC_F
Disabled
LOW
Active
1
4
55
IOAPICO
Disabled
LOW
Active
1
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
2
REF1
Clock Output Disable
LOW
Active
1
0
3
REF0
Clock Output Disable
LOW
Active
1
Data Byte 5
Document #: 38-07038 Rev. **
Page 7 of 15
CY24239
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Spread Spectrum
Data Byte 0, Bit 3 = 1
Bit 2
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Percentage
1
1
1
1
91.66
30.5
OFF
1
1
1
0
75.0
25.0
OFF
1
1
0
1
100.0
33.3
OFF
1
1
0
0
83.3
27.76
OFF
1
0
1
1
66.6
33.3
OFF
1
0
1
0
105.0
26.3
OFF
1
0
0
1
110.0
27.5
OFF
1
0
0
0
133.3
33.3
OFF
0
1
1
1
91.66
30.5
–1.2%
0
1
1
0
75.0
25.0
–1.2%
0
1
0
1
100.0
33.3
–1.2%
0
1
0
0
83.3
27.76
–1.2%
0
0
1
1
91.66
30.5
–2.4%
0
0
1
0
75.0
25.0
–2.4%
0
0
0
1
100.0
33.3
–2.4%
0
0
0
0
83.3
27.76
–2.4%
Table 7. Select Function for Data Byte 0, Bits 0
Input Conditions
Output Conditions
Data Byte 0
Bit 0
CPU_F, 1:2
PCI_F,
PCI0:5
REF0:1,
IOAPIC0,_F
48MHZ
24MHZ
Normal Operation
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Three-state
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Function
Note:
2. CPU and PCI frequency selections are listed in Table 2 and Table 6.
Document #: 38-07038 Rev. **
Page 8 of 15
CY24239
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
TA
Operating Temperature
0 to +70
°C
ESDPROT
Input ESD Protection
2 (min.)
kV
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
3.3V Supply Current
CPU_F, 1:2 = 100 MHz
Outputs Loaded[3]
370
mA
Logic Inputs
VIL
Input Low Voltage
VIH
Input High Voltage
GND – 0.3
0.8
V
2.0
VDD + 0.3
V
[4]
IIL
Input Low Current
–25
µA
IIH
Input High Current[4]
10
µA
IIL
Input Low Current (SEL100/66#)
–5
µA
IIH
Input High Current (SEL100/66#)
+5
µA
50
mV
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
3.1
V
VOH
Output High Voltage
CPU_F, 1:2 IOAPIC
IOH = –1 mA
2.2
V
IOL
Output Low Current
CPU_F, 1:2
VOL = 1.25V
60
73
85
mA
PCI_F, PCI0:5
VOL = 1.5V
96
110
130
mA
IOAPIC0, IOAPIC_F
VOL = 1.25V
72
92
110
mA
REF0:1
VOL = 1.5V
61
71
80
mA
48-MHz
VOL = 1.5V
60
70
80
mA
24-MHz
VOL = 1.5V
60
70
80
mA
SDRAM0:16
VOL = 1.5V
95
110
130
mA
CPU_F, 1:2
VOL = 1.25V
43
60
80
mA
PCI_F, PCI0:5
VOL = 1.5V
76
96
120
mA
IOAPIC0, IOAPIC_F
VOL = 1.25V
60
90
130
mA
REF0:1
VOL = 1.5V
50
60
72
mA
48-MHz
VOL = 1.5V
50
60
72
mA
24-MHz
VOL = 1.5V
50
60
72
mA
SDRAM0:16
VOL = 1.5V
75
95
120
mA
IOH
Output High Current
Notes:
3. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors.
4. CY24239 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
Document #: 38-07038 Rev. **
Page 9 of 15
CY24239
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[5]
CLOAD
Load Capacitance, Imposed on
External Crystal[6]
CIN,X1
X1 Input Capacitance[7]
VDDQ3 = 3.3V
Pin X2 unconnected
1.65
V
14
pF
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
COUT
LIN
Except X1 and X2
5
pF
Output Pin Capacitance
6
pF
Input Pin Inductance
7
nH
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.
CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
tP
Period
tH
tL
Test Condition/
Comments
CPU = 100 MHz
Min.
Typ.
Max.
Unit
10.5
ns
Measured on rising edge at 1.25
10
High Time
Duration of clock cycle above 2.0V
3.0
ns
Low Time
Duration of clock cycle below 0.4V
2.8
ns
tR
Output Rise
Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Measured from 2.0V to 0.4V
Rate
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
%
tJC
Jitter,
Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between two
adjacent cycles.
250
ps
350
ps
3
ms
tSK
Output Skew
Measured on rising edge at 1.25V
fST
Frequency
Stabilization
from Power-up
(cold start)
Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist
prior to frequency stabilization.
Zo
AC Output
Impedance
Average value during switching transition.
Used for determining series termination
value.
20
Ω
Notes:
5. X1 input threshold voltage (typical) is VDDQ3/2.
6. The CY24239 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
20 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07038 Rev. **
Page 10 of 15
CY24239
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
tSK
4
V/ns
1
4
V/ns
45
55
%
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
1.5
Ω
15
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
Test Condition/Comments
Min.
Frequency generated by crystal oscillator
Typ.
Max.
14.318
Unit
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Ω
15
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Document #: 38-07038 Rev. **
Typ.
Max.
14.318
Unit
MHz
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
25
Ω
Page 11 of 15
CY24239
SDRAM 0:16 Clock Outputs (Lump Capacitance Test Load = 22 pF)
Parameter
Test Condition/
Comments
Description
SDRAMIN =
100 MHz
Min.
Typ.
Max.
Unit
10.5
ns
tP
Period
Measured on rising edge at 1.5V
10
tH
High Time
Duration of clock cycle above 2.4V
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
2.0
ns
tR
Output Rise Edge
Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge
Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.5V
45
55
%
tSK
Output Skew
Measured on rising and falling edge at
1.5V
250
ps
tPD
Propagation
Delay
Measured from SDRAMIN
3.7
ns
Zo
AC Output
Impedance
Average value during switching transition. Used for determining series termination value.
15
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Document #: 38-07038 Rev. **
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
25
Ω
Page 12 of 15
CY24239
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
fD
Deviation from 24 MHz
(24.004 – 24)/24
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
2
V/ns
0.5
2
V/ns
45
55
%
3
ms
25
Ω
Ordering Information
Ordering Code
CY24239PVC
Package Type
56-pin SSOP (300 mils)
Document #: 38-07038 Rev. **
Page 13 of 15
CY24239
Package Diagram
56-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07038 Rev. **
Page 14 of 15
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY24239
Document Title:CY24239 Spread Spectrum Frequency Timing Generator
Document Number:38-07038
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
106975
05/24/01
IKA
New Data Sheet
Document #: 38-07038 Rev. **
Page 15 of 15