TrilithIC BTS 7710 G Data Sheet 1 Overview 1.1 Features • • • • • • • • • • • • • • • Quad D-MOS switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications Low RDS ON: 70 mτ high-side switch, 40 mτ low-side switch (typical values @ 25 C) Maximum peak current: typ. 15 A @ 25 C= Very low quiescent current: typ. 5 ←A @ 25 C= Small outline, enhanced power P-DSO-package Load and GND-short-circuit-protection Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Internal clamp diodes Isolated sources for external current sensing Under-voltage detection with hysteresis PWM frequencies up to 50 kHz P-DSO-28-14 Type Ordering Code Package BTS 7710 G Q67007-A9399 P-DSO-28-14 1.2 Description The BTS 7710 G is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated leadframes. The sources are connected to individual pins, so the BTS 7710 G can be used in H-bridge- as well as in any other configuration. The double high-side is manufactured in SMART SIPMOS® technology which combines low RDS ON vertical DMOS power stages with CMOS control circuitry. The high-side switch is fully protected and contains the control and diagnosis circuitry. To achieve low RDS ON and fast switching performance, the low-side switches are manufactured in S-FET logic level technology. The equivalent standard product is the BUZ 103 SL. In contrast to the BTS 7710 GP, which consists of the same chips in an P-TO263-15 package, the P-DSO-28-14 package offers a smaller outline and a lower price for applications, which do not need the thermal properties of the P-TO263-15. Data Sheet 1 2001-02-01 BTS 7710 G 1.3 Pin Configuration (top view) DL1 1 28 DL1 IL1 2 27 SL1 DL1 3 26 SL1 LS-Leadframe N.C. 4 25 DL1 DHVS 5 24 DHVS GND 6 23 SH1 IH1 7 22 SH1 HS-Leadframe ST 8 21 SH2 IH2 9 20 SH2 DHVS 10 19 DHVS N.C. 11 18 DL2 LS-Leadframe DL2 12 17 SL2 IL2 13 16 SL2 DL2 14 15 DL2 Figure 1 Data Sheet 2 2001-02-01 BTS 7710 G 1.4 Pin Definitions and Functions Pin No. Symbol Function 1, 3, 25, 28 DL1 Drain of low-side switch1, leadframe 1 1) 2 IL1 Analog input of low-side switch1 4 N.C. not connected 5, 10, 19, 24 DHVS Drain of high-side switches and power supply voltage, leadframe 2 1) 6 GND Ground 7 IH1 Digital input of high-side switch1 8 ST Status of high-side switches; open Drain output 9 IH2 Digital input of high-side switch2 11 N.C. not connected 12, 14, 15, 18 DL2 Drain of low-side switch2, leadframe 3 1) 13 IL2 Analog input of low-side switch2 16,17 SL2 Source of low-side switch2 20,21 SH2 Source of high-side switch2 22,23 SH1 Source of high-side switch1 26,27 SL1 Source of low-side switch1 1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe. Pins written in bold type need power wiring. Data Sheet 3 2001-02-01 BTS 7710 G 1.5 Functional Block Diagram DHVS 5,10,19,24 8 ST Diagnosis IH1 IH2 GND 7 9 Biasing and Protection Driver IN OUT 0 0 L L 0 1 L H 1 0 H L 1 1 H H RO1 RO2 20,21 SH2 12,14,15,18 DL2 22, 23 SH1 1,3,25,28 DL1 6 2 IL1 13 IL2 26, 27 SL1 16, 17 SL2 Figure 2 Block Diagram Data Sheet 4 2001-02-01 BTS 7710 G 1.6 Circuit Description Input Circuit The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical power-MOS-FETs. Output Stages The output stages consist of an low RDS ON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when commutating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against – output short circuit to ground – overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-VoltageDrop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. Overtemperature Protection The high-side switches incorporate an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. Undervoltage-Lockout (UVLO) When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF. Data Sheet 5 2001-02-01 BTS 7710 G Status Flag The status flag output is an open drain output with Zener-diode which requires a pull-up resistor, c.f. the application circuit on page 14. Various errors as listed in the table “Diagnosis” are detected by switching the open drain output ST to low. A open load detection is not available. Freewheeling condition does not cause an error. 2 Truthtable and Diagnosis (valid only for the High-Side-Switches) Flag IH1 IH2 SH1 Inputs Normal operation; identical with functional truth table Overtemperature high-side switch1 Overtemperature high-side switch2 Overtemperature both high-side switches Undervoltage SH2 ST Remarks Outputs 0 0 1 1 0 1 0 1 L L H H L H L H 1 1 1 1 0 1 X X L L X X 1 0 detected X X 0 1 X X L L 1 0 detected 0 X 1 0 1 X L L L L L L 1 0 0 detected detected X X L L 1 not detected Inputs: Outputs: Status: 0 = Logic LOW Z = Output in tristate condition 1 = No error 1 = Logic HIGH L = Output in sink condition 0 = Error X = don’t care H = Output in source condition stand-by mode switch2 active switch1 active both switches active X = Voltage level undefined Data Sheet 6 2001-02-01 BTS 7710 G 3 Electrical Characteristics 3.1 Absolute Maximum Ratings – 40 C < Tj < 150 C Parameter Symbol Limit Values min. Unit Remarks max. High-Side-Switches (Pins DHVS, IH1,2 and SH1,2) Supply voltage Supply voltage for full short circuit protection HS-drain current* HS-input current HS-input voltage Note: * single pulse VS VS(SCP) – 0.3 IS IIH VIH 42 V – 28 V – –8 ** A TA = 25°C; t < 100 ms –5 5 mA Pin IH1 and IH2 – 10 16 V Pin IH1 and IH2 – 0.3 5.4 V – –5 5 mA Pin ST ** internally limited Status Output ST Status pull up voltage Status Output current VST IST Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2) Drain- source break down voltage VDSL 55 – V VIL = 0 V; ID 1 mA LS-drain current* TA = 25°C IDL –8 8 A – 11 A – 24 A t < 100 ms t < 10 ms t < 1 ms VIL – 20 20 V Pin IL1 and IL2 Tj Tstg – 40 150 C – – 55 150 C – LS-input voltage Note: * single pulse Temperatures Junction temperature Storage temperature Data Sheet 7 2001-02-01 BTS 7710 G 3.1 Absolute Maximum Ratings (cont’d) – 40 C < Tj < 150 C Parameter Symbol Limit Values min. Unit Remarks max. Thermal Resistances (one HS-LS-Path active) LS-junction case HS-junction case Junction ambient Rthja = Tj(HS)/(P(HS)+P(LS)) RthjC L RthjC H Rthja – 20 K/W measured to pin 3 or 12 – 20 K/W measured to pin 19 – 60 K/W device soldered to reference PCB with 6 cm2 cooling area ESD Protection (Human Body Model acc. MIL STD 883D, method 3015.7 and EOS/ ESD assn. standard S5.1 - 1993) Input LS-Switch Input HS-Switch Status HS-Switch Output LS and HS-Switch VESD VESD VESD VESD – 0.5 kV – 1 kV – 2 kV – 8 kV all other pins connected to Ground Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 3.2 Operating Range – 40 C < Tj < 150 C Parameter Symbol Limit Values min. Unit Remarks max. Supply voltage VS VUVOFF 42 V After VS rising above VUVON Input voltages HS VIH VIL IST Tj – 0.3 15 V – – 0.3 20 V – 0 2 mA – – 40 150 C – Input voltages LS Output current Junction temperature Note: In the operating range the functions given in the circuit description are fulfilled. Data Sheet 8 2001-02-01 BTS 7710 G 3.3 Electrical Characteristics ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. – 5 8 ←A IH1 = IH2 = 0 V Tj = 25 C – – 12 ←A IH1 = IH2 = 0 V – 1.5 2.6 mA Current Consumption HS-switch Quiescent current Supply current IS IS IH1 or IH2 = 5 V VS = 12 V – 3 5.2 mA IH1 and IH2 = 5 V VS = 12 V Leakage current of highside switch ISH LK – – 6 ←A VIH = VSH = 0 V Leakage current through logic GND in free wheeling condition ILKCL = IFH + ISH – – 10 mA IFH = 3 A – 10 100 nA – – 10 ←A VIL = 20 V; VDSL = 0 V Tj = 25 C VIL = 0 V VDSL = 40 V – – 4.5 V 1.8 – 3.2 V – 1 – V Current Consumption LS-switch Input current IIL Leakage current of lowside IDL LK switch Under Voltage Lockout (UVLO) HS-switch VUVON Switch-OFF voltage VUVOFF Switch ON/OFF hysteresis VUVHY Switch-ON voltage Data Sheet 9 VS increasing VS decreasing VUVON – VUVOFF 2001-02-01 BTS 7710 G 3.3 Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Condition Output stages Inverse diode of high-side switch; Forward-voltage VFH – 0.8 1.2 V IFH = 3A Inverse diode of lowside switch; Forward-voltage VFL – 0.8 1.2 V IFL = 3 A Static drain-source on-resistance of highside switch RDS ON H – 70 90 mτ ISH = 1 A Tj = 25 C Static drain-source on-resistance of lowside switch RDS ON L – 40 50 mτ ISL = 1 A; VIL = 5 V Tj = 25 C Static path on-resistance RDS ON – – 260 mτ RDS ON H + RDS ON L ISH = 1 A; 15 18 20 A 13 15 17 A 9 11 13 A Tj = – 40 °C Tj = + 25 °C Tj = + 150 °C 8 15 35 kτ VDSL = 3 V Thermal shutdown junction Tj SD temperature 155 180 190 C – Thermal switch-on junction Tj SO temperature 150 170 180 C – – 10 – C αT = TjSD – TjSO Short Circuit of highside switch to GND Initial peak SC current Initial peak SC current Initial peak SC current ISCP H ISCP H ISCP H Short Circuit of highside switch to VS Output pull-down-resistor RO Thermal Shutdown Temperature hysteresis Data Sheet αT 10 2001-02-01 BTS 7710 G 3.3 Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values min. Unit Test Condition typ. max. – 0.2 0.6 V – – 10 ←A – V Status Flag Output ST of highside switch Low output voltage Leakage current Zener-limit-voltage VST L IST LK VST Z 5.4 IST = 1.6 mA VST = 5 V IST = 1.6 mA Switching times of highside switch Turn-ON-time; to 90% VSH tON – 75 160 ←s RLoad = 12 τ VS = 12 V Turn-OFF-time; to 10% VSH tOFF – 60 160 ←s RLoad = 12 τ VS = 12 V Slew rate on 10 to 30% VSH dV/dtON – – 1.5 V/←s RLoad = 12 τ VS = 12 V Slew rate off 70 to 40% VSH -dV/ – – 2.0 V/←s RLoad = 12 τ VS = 12 V dtOFF Note: switching times are guaranteed by design Switching times of low-side switch Turn-ON delay time; VIL = 5V; RG = 7τ td_ON_L – 9 14 ns resistive load ISL = 3 A; VS = 30 V Switch-ON time; VIL= 5V; RG = 7τ tON_L – 25 40 ns resistive load ISL = 3 A; VS = 30 V Switch-OFF delay time; VIL= 5V; RG = 7τ td_OFF_L – 36 55 ns resistive load ISL = 3 A; VS = 30 V Switch-OFF time; VIL= 5V; RG = 7τ tOFF_L – 22 33 ns resistive load ISL = 3 A; VS = 30 V Data Sheet 11 2001-02-01 BTS 7710 G 3.3 Electrical Characteristics (cont’d) ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. – 4 6 nC – 10 16 nC Input charge total; QIS QID QI – 28 43 nC Input plateau voltage; V(plateau) – 2.75 - V Gate charge of lowside switch Input to source charge; Input to drain charge; ISL = 3 A; VS = 14 V ISL = 3 A; VS = 14 V ISL = 3 A; VS = 14 V VIL = 0 to 10 V ISL = 3 A; VS = 14 V Note: switching times and input charges are guaranteed by design Control Inputs of highside switches IH 1, 2 H-input voltage L-input voltage Input voltage hysterese H-input current L-input current Input series resistance Zener limit voltage VIH High VIH Low VIH HY IIH High IIH Low RI VIH Z – – 2.5 V – 1 – – V – – 0.3 – V – 15 30 60 ←A 5 – 20 ←A VGH = 5 V VGH = 0.4 V 2.7 4 5.5 kτ – 5.4 – – V IGH = 1.6 mA VIL th 0.9 1.7 2.2 V IDL = 1 mA Control Inputs IL1, 2 Gate-threshold-voltage Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Data Sheet 12 2001-02-01 BTS 7710 G VS=12V IS CL 100µF CS 470nF IFH1,2 DHVS IST LK IST 5,10,19,24 ST 8 Diagnosis VST IIH1 VSTL IH1 7 IH2 9 VIH1 VIH2 -VFH1 Biasing and Protection RO1 GND VDSH1 -VFH2 Gate Driver VSTZ IIH1 VDSH2 Gate Driver RO2 20,21 12,14,15,18 SH2 ISH2 DL2 IDL2 IDL LK 2 VUVON SH1 ISH1 VUVOFF DL1 IDL1 6 IGND 22,23 ILKCL 1,3,25,28 IDL LK 1 VIL1 IIL1 IL1 2 IIL2 IL2 13 VIL th 1 VIL2 26,27 VIL th 2 16,17 SL1 SL2 ISCP L 1 ISCP L 2 ISL1 ISL2 VDSL1 VDSL2 -VFL1 -VFL2 Figure 3 Test Circuit HS-Source-Current Named during Short Circuit Named during LeakageCond. ISH1,2 ISCP H IDL LK Data Sheet 13 2001-02-01 BTS 7710 G Watchdog Reset Q RQ 100 kτ τ WD R CQ 22µF TLE 4278G I VS=12V D CS 10µF D01 Z39 CD 47nF VCC DHVS 5,10,19,24 RS ST 8 10 kτ τ Diagnosis IH1 7 IH2 9 Biasing and Protection Gate Driver RO1 GND Gate Driver RO2 20,21 12,14,15,18 SH2 DL2 6 µP 22,23 1,3,25,28 IL1 2 IL2 13 26,27 GND SL1 SH1 M DL1 16,17 SL2 Figure 4 Application Circuit Data Sheet 14 2001-02-01 BTS 7710 G 4 Package Outlines x 8˚ ma 7.6 -0.2 1) +0.09 0.35 x 45˚ 0.23 2.65 max 2.45 -0.2 0.2 -0.1 P-DSO-28-14 (Plastic Transistor Single Outline Package) 0.4 +0.8 1.27 0.35 +0.15 2) 0.1 0.2 28x 28 1 10.3 ±0.3 15 18.1 -0.4 1) 14 1) Does not include plastic or metal protrusions of 0.15 max rer side 2) Does not include dambar protrusion of 0.05 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 15 GPS05123 GPS05123 Index Marking Dimensions in mm 2001-02-01 BTS 7710 G Published by Infineon Technologies AG i Gr., Bereichs Kommunikation St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet 16 2001-02-01