fax id: 1079 1CY 621 48 CY62148 PRELIMINARY 512K x 8 Static RAM Features an automatic power-down feature that reduces power consumption by more than 99% when deselected. • 4.5V−5.5V operation • CMOS for optimum speed/power • Low active power — 660 mW (max.) • Low standby power (L version) — 2.75 mW (max.) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE options Writing to the device is accomplished by taking chip enable one (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable one (CE) and output enable (OE) LOW while forcing write enable (WE). Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Functional Description The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. This device has The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62148 is available in a standard 450-mil-wide body width SOIC package. Logic Block Diagram Pin Configuration Top View SOIC A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 512K x 8 ARRAY I/O3 I/O4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 WE OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 62148-1 Selection Guide CY62148–55 Maximum Access Time (ns) Maximum Operating Current Commercial Maximum CMOS Standby Current Commercial L CY62148–70 55 70 120 mA 120 mA 2 mA 2 mA 0.5 mA 0.5 mA Shaded areas contain advance information Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1996 - Revised July 31, 1997 CY62148 PRELIMINARY DC Input Voltage[1] ................................. –0.5V to VCC +0.5V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Range Commercial Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................–0.5V to VCC +0.5V Industrial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Electrical Characteristics Over the Operating Range[3] 62148–55 Parameter Description Test Conditions Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –1 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 2.4 VIH Input HIGH Voltage 2.2 VCC + 0.3 VIL Input LOW Voltage[1] –0.3 IIX Input Load Current GND ≤ VI ≤ VCC IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com’l ISB1 Automatic CE Power-Down Current — TTL Inputs Max. VCC, CE ≥ VIH VIN ≥ VIH or VIN ≤ VIL, f = fMAX ISB2 Automatic CE Power-Down Current — CMOS Inputs Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f=0 62148–70 Min. Max. 2.4 0.4 V 0.4 V 2.2 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –5 +5 –5 +5 µA 120 120 mA Com’l 15 15 mA Com’l 2 2 mA 500 500 µA L Shaded areas contain advance information Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. 2 Unit Max. Unit 10 pF 10 pF CY62148 PRELIMINARY AC Test Loads and Waveforms ALL INPUT PULSES R1 480Ω R1 481Ω 5V 5V OUTPUT 3.0V 90% OUTPUT R2 255Ω 30 pF R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) INCLUDING JIG AND SCOPE (b) 90% 10% GND 10% ≤ 3ns ≤ 3 ns 109–3 109–4 THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: Switching Characteristics[3,6] Over the Operating Range 62148–55 Parameter Description Min. Max. 62148–70 Min. Max. Unit READ CYCLE tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 20 35 ns tLZOE OE LOW to Low Z 55 3 OE HIGH to High tLZCE CE LOW to Low Z[8] tHZCE CE HIGH to High tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 70 20 ns 25 3 20 0 ns ns 25 0 55 ns ns 0 3 Z[7, 8] ns 3 0 Z[7, 8] tHZOE 70 ns ns 70 ns WRITE CYCLE[9] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tSD Data Set-Up to Write End 45 55 ns tHD Data Hold from Write End 0 0 ns 3 3 ns tLZWE tHZWE WE HIGH to Low Z[8] WE LOW to High Z[7,8] 20 25 ns Shaded areas contain advance information. Notes 6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 3 CY62148 PRELIMINARY Switching Waveforms Read Cycle No.1[10,11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 62148-5 Read Cycle No. 2 (OE Controlled)[11,12] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB 62148-6 Write Cycle No. 1 (CE Controlled)[13,14] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID 62148-7 Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 4 CY62148 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 15 tHZOE Write Cycle No.3 (WE Controlled, OE 62148-8 LOW)[13,14] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATAI/O NOTE 15 tHD DATA VALID tLZWE tHZWE 62148-9 Note: 15. During this period the I/Os are in the output state and input signals should not be applied 5 CY62148 PRELIMINARY Truth Table CE1 OE WE H X X High Z I/O0 – I/O7 Power-Down Mode X X X High Z Power-Down Standby (I SB) Standby (I SB) Power L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current Conditions Min. No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Ordering Code Package Name Package Type 500 µA (Mil) 2 mA 0 ns tRC ns Operating Range S34 32-Lead (450-Mil) Molded SOIC Commercial 55 CY62148L–55SC S34 32-Lead (450-Mil) Molded SOIC Commercial 70 CY62148–70SC S34 32-Lead (450-Mil) Molded SOIC Commercial 70 CY62148L–70SC S34 32-Lead (450-Mil) Molded SOIC Commercial 70 CY62148-70SI S34 32-Lead (450-Mil) Molded SOIC Industrial 70 CY62148L-70SI S34 32-Lead (450-Mil) Molded SOIC Industrial 6 µA (Ind’l) CY62148–55SC Document #: 38-00564-A V 200 55 Shaded areas contain advance information. Unit (Com’l) Ordering Information Speed (ns) Max 2.0 PRELIMINARY Package Diagrams 32-Lead (450 Mil) Molded SOIC S34 7 CY62148