CY62128B MoBL™ 128K x 8 Static RAM and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. 1CY62128B MoBL™ Features • 4.5V–5.5V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) — 82.5 mW (max.) (15 mA) • Low standby power (70 ns, LL version) — 110 µW (max.) (15 µA) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options Functional Description The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages. Logic Block Diagram Pin Configurations Top View SOIC INPUT BUFFER I/O 2 SENSE AMPS 512x 256x 8 ARRAY I/O 3 I/O 4 I/O 5 COLUMN DECODER CE1 CE2 WE I/O 6 POWER DOWN A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 I/O 7 OE A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reverse TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GN G G ND 16 gnc g I/O 1 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 NC A16 A14 A12 I/O 0 V CC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 62128-1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A11 A2 A9 A1 A8 A13 A0 I/O0 WE I/O1 CE2 A15 I/O2 GND VCC NC I/O3 A16 I/O4 A14 I/O5 A12 I/O6 A7 I/O7 A6 CE1 A5 A10 A4 OE Cypress Semiconductor Corporation • 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 STSOP Top View (not to scale) 3901 North First Street 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 • OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 San Jose 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 • TSOP I Top View (not to scale) CA 95134 • 32 31 30 29 28 27 26 25 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O I/O6 6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 408-943-2600 March 29, 2001 CY62128B MoBL™ Selection Guide CY62128B-55 CY62128B-70 Maximum Access Time Maximum Operating Current (ICC) Maximum CMOS Standby Current (ISB2) Maximum Ratings Unit 55 70 ns Industrial LL 20 15 mA Commericial LL 20 15 mA Industrial LL 15 15 µA Commericial LL 15 15 µA Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State ....................................–0.5V to VCC + 0.5V Industrial Commercial DC Input Voltage .................................–0.5V to VCC + 0.5V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 2 Ambient Temperature V –40°C to +85°C 5V ± 10% 0°C to +70°C 5V ± 10% CY62128B MoBL™ Electrical Characteristics Over the Operating Range 62128B-55 Parameter Description Test Conditions Min. Typ.  62128B-70 Max. VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current GND ≤ VI ≤ VCC IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled IOS Output Short Circuit Current VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Ind’l LL 7.5 20 ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE1 ≥ VIH or CE2 < VIL, VIN ≥ VIH or VIN ≤ VIL, f = fMAX Ind’l LL 0.1 ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 Ind’l LL ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE1 ≥ VIH or CE2 < VIL, VIN ≥ VIH or VIN ≤ VIL, f = fMAX ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 Min. Typ. Max. 2.4 Unit V 0.4 V 2.2 VCC + 0.3 0.4 2.2 VCC + 0.3 V –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA –300 mA 6 15 mA 2 0.1 1 mA 2.5 15 2.5 15 µA LL 7.5 20 6 15 mA Com LL 0.1 2 0.1 1 mA Com LL 2.5 15 2.5 15 µA –300 Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 9 pF 9 pF Notes: 3. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25°C, and tAA = 70 ns 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. 3 CY62128B MoBL™ AC Test Loads and Waveforms R1 1800 Ω 5V ALL INPUT PULSES R1 1800Ω 5V OUTPUT VCC 90% OUTPUT R2 990Ω 100 pF R2 990 Ω 5 pF INCLUDING JIG AND SCOPE (a) INCLUDING JIG AND SCOPE (b) 90% 10% GND 10% Fall TIme: 1 V/ns Rise TIme: 1 V/ns Equivalent to: THÉVENIN EQUIVALENT 639 Ω 1.77V OUTPUT Switching Characteristics Over the Operating Range 62128B-55 Parameter Description Min. Max. 62128B-70 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 20 35 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High 55 55 5 70 CE1 LOW to Low Z, CE2 HIGH to Low tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[7, 8] 5 tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up 5 0 CE1 HIGH to Power-Down, CE2 LOW to Power-Down ns 25 20 ns ns 25 0 55 ns ns 0 20 Z ns 5 0 Z[7, 8] tLZCE tPD 70 ns ns 70 ns  WRITE CYCLE tWC Write Cycle Time 55 70 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z 5 5 ns tHZWE WE LOW to High Z[7, 8] 20 25 ns Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 4 CY62128B MoBL™ Data Retention Characteristics (Over the Operating Range for “LL” version only) Parameter Conditions Description Min. Typ. Max. Unit VDR VCC for Data Retention ICCDR Data Retention Current Ind.’l LL VCC = VDR = 3.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V 1.5 15 µA ICCDR Data Retention Current Com. LL VCC = VDR = 3.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V 1.5 15 µA tCDR Chip Deselect to Data Retention Time 0 ns tR Operation Recovery Time 70 ns 2.0 V Switching Waveforms Read Cycle No.1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Notes: 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 5 CY62128B MoBL™ Switching Waveforms (continued) Write Cycle No. 1 (CE1 or CE2 Controlled)[14, 15] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE OE tSD DATA I/O DATAIN VALID NOTE 16 tHZOE Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state 16. During this period the I/Os are in the output state and input signals should not be applied.. 6 tHD CY62128B MoBL™ Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW)[14, 15] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE tSD NOTE 16 DATAI/O tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 OE WE I/O0–I/O7 Mode H X X X High Z Power-Down Standby (ISB) X L X X High Z Power-Down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) 7 Power CY62128B MoBL™ Ordering Information Speed (ns) 55 70 Ordering Code Package Name CY62128BLL-55SI S34 CY62128BLL-55SC CY62128BLL-55ZI Package Type Operating Range 32-Lead 450-Mil SOIC Industrial S34 32-Lead 450-Mil SOIC Commercial Z32 32-Lead TSOP Type I Industrial 32-Lead TSOP Type I Commercial CY62128BLL-55ZC Z32 CY62128BLL-55ZAI ZA32 32-Lead STSOP Type I Industrial Commercial CY62128BLL-55ZAC ZA32 32-Lead STSOP Type I CY62128BLL-70ZRI ZR32 32-Lead Reverse TSOP Type I Industrial CY62128BLL-70ZRC ZR32 32-Lead Reverse TSOP Type I Commercial CY62128BLL-70SI S34 32-Lead 450-Mil SOICI Industrial CY62128BLL-70SC CY62128BLL-70ZI S34 32-Lead 450-Mil SOIC I Commercial Z32 32-Lead TSOP Type I Industrial 32-Lead TSOP Type I Commercial CY62128BLL-70ZC Z32 CY62128BLL-70ZAI ZA32 32-Lead STSOP Type I Industrial Commercial CY62128BLL-70ZAC ZA32 32-Lead STSOP Type I CY62128BLL-70ZRI ZR32 32-Lead Reverse TSOP Type I Industrial CY62128BLL-70ZRC ZR32 32-Lead Reverse TSOP Type I Commercial Document #: 38-00524-*F 8 CY62128B MoBL™ Package Diagrams 32-Lead (450 Mil) Molded SOIC S34 51-85081-A 32-Lead (450 Mil) Molded SOIC S34 51-85081-A 9 CY62128B MoBL™ Package Diagrams (continued) 32-Lead Thin Small Outline Package Z32 51-85056-C 10 CY62128B MoBL™ Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package ZA32 51-85094-B 11 CY62128B MoBL™ Package Diagrams (continued) 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-B © Cypress Semiconductor Corporation, 2001. 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